dd78bc11fb
The "inv" (invalidate) instruction is generally less safe than "finv" (flush and invalidate), as it will drop dirty data from the cache. It turns out we have almost no need for "inv" (other than for the older 32-bit architecture in some limited cases), so convert to "finv" where possible and delete the extra "inv" infrastructure. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
43 lines
1.8 KiB
C
43 lines
1.8 KiB
C
/*
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* Copyright 2011 Tilera Corporation. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation, version 2.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for
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* more details.
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*/
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#ifndef _ASM_TILE_CACHECTL_H
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#define _ASM_TILE_CACHECTL_H
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/*
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* Options for cacheflush system call.
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*
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* The ICACHE flush is performed on all cores currently running the
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* current process's address space. The intent is for user
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* applications to be able to modify code, invoke the system call,
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* then allow arbitrary other threads in the same address space to see
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* the newly-modified code. Passing a length of CHIP_L1I_CACHE_SIZE()
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* or more invalidates the entire icache on all cores in the address
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* spaces. (Note: currently this option invalidates the entire icache
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* regardless of the requested address and length, but we may choose
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* to honor the arguments at some point.)
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*
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* Flush and invalidation of memory can normally be performed with the
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* __insn_flush() and __insn_finv() instructions from userspace.
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* The DCACHE option to the system call allows userspace
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* to flush the entire L1+L2 data cache from the core. In this case,
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* the address and length arguments are not used. The DCACHE flush is
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* restricted to the current core, not all cores in the address space.
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*/
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#define ICACHE (1<<0) /* invalidate L1 instruction cache */
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#define DCACHE (1<<1) /* flush and invalidate data cache */
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#define BCACHE (ICACHE|DCACHE) /* flush both caches */
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#endif /* _ASM_TILE_CACHECTL_H */
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