![Dongjin Kim](/assets/img/avatar_default.png)
This patch adds to enable High Speed Inter Chip on Exynos4X12. Both channels are controlled by usbphy driver based on the patch series of usbphy driver submitted by Tomasz Figa. [1] https://patchwork.kernel.org/patch/2576121 [2] https://patchwork.kernel.org/patch/2576131 [3] https://patchwork.kernel.org/patch/2576141 [4] https://patchwork.kernel.org/patch/2576151 [5] https://patchwork.kernel.org/patch/2576161 [6] https://patchwork.kernel.org/patch/2576171 Signed-off-by: Dongjin Kim <tobetter@gmail.com> Cc: Tomasz Figa <t.figa@samsung.com> Cc: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
242 lines
5.6 KiB
C
242 lines
5.6 KiB
C
/* linux/drivers/usb/phy/phy-samsung-usb.c
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*
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* Copyright (c) 2012 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* Author: Praveen Paneri <p.paneri@samsung.com>
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*
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* Samsung USB-PHY helper driver with common function calls;
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* interacts with Samsung USB 2.0 PHY controller driver and later
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* with Samsung USB 3.0 PHY driver.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/clk.h>
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#include <linux/device.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/usb/samsung_usb_phy.h>
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#include "phy-samsung-usb.h"
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int samsung_usbphy_parse_dt(struct samsung_usbphy *sphy)
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{
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struct device_node *usbphy_sys;
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/* Getting node for system controller interface for usb-phy */
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usbphy_sys = of_get_child_by_name(sphy->dev->of_node, "usbphy-sys");
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if (!usbphy_sys) {
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dev_err(sphy->dev, "No sys-controller interface for usb-phy\n");
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return -ENODEV;
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}
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sphy->pmuregs = of_iomap(usbphy_sys, 0);
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if (sphy->pmuregs == NULL) {
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dev_err(sphy->dev, "Can't get usb-phy pmu control register\n");
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goto err0;
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}
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sphy->sysreg = of_iomap(usbphy_sys, 1);
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/*
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* Not returning error code here, since this situation is not fatal.
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* Few SoCs may not have this switch available
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*/
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if (sphy->sysreg == NULL)
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dev_warn(sphy->dev, "Can't get usb-phy sysreg cfg register\n");
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of_node_put(usbphy_sys);
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return 0;
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err0:
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of_node_put(usbphy_sys);
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return -ENXIO;
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}
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EXPORT_SYMBOL_GPL(samsung_usbphy_parse_dt);
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/*
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* Set isolation here for phy.
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* Here 'on = true' would mean USB PHY block is isolated, hence
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* de-activated and vice-versa.
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*/
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void samsung_usbphy_set_isolation_4210(struct samsung_usbphy *sphy, bool on)
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{
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void __iomem *reg = NULL;
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u32 reg_val;
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u32 en_mask = 0;
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if (!sphy->pmuregs) {
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dev_warn(sphy->dev, "Can't set pmu isolation\n");
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return;
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}
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if (sphy->phy_type == USB_PHY_TYPE_DEVICE) {
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reg = sphy->pmuregs + sphy->drv_data->devphy_reg_offset;
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en_mask = sphy->drv_data->devphy_en_mask;
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} else if (sphy->phy_type == USB_PHY_TYPE_HOST) {
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reg = sphy->pmuregs + sphy->drv_data->hostphy_reg_offset;
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en_mask = sphy->drv_data->hostphy_en_mask;
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}
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reg_val = readl(reg);
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if (on)
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reg_val &= ~en_mask;
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else
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reg_val |= en_mask;
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writel(reg_val, reg);
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if (sphy->drv_data->cpu_type == TYPE_EXYNOS4X12) {
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writel(reg_val, sphy->pmuregs + EXYNOS4X12_PHY_HSIC_CTRL0);
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writel(reg_val, sphy->pmuregs + EXYNOS4X12_PHY_HSIC_CTRL1);
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}
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}
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EXPORT_SYMBOL_GPL(samsung_usbphy_set_isolation_4210);
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/*
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* Configure the mode of working of usb-phy here: HOST/DEVICE.
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*/
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void samsung_usbphy_cfg_sel(struct samsung_usbphy *sphy)
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{
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u32 reg;
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if (!sphy->sysreg) {
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dev_warn(sphy->dev, "Can't configure specified phy mode\n");
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return;
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}
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reg = readl(sphy->sysreg);
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if (sphy->phy_type == USB_PHY_TYPE_DEVICE)
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reg &= ~EXYNOS_USB20PHY_CFG_HOST_LINK;
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else if (sphy->phy_type == USB_PHY_TYPE_HOST)
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reg |= EXYNOS_USB20PHY_CFG_HOST_LINK;
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writel(reg, sphy->sysreg);
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}
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EXPORT_SYMBOL_GPL(samsung_usbphy_cfg_sel);
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/*
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* PHYs are different for USB Device and USB Host.
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* This make sure that correct PHY type is selected before
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* any operation on PHY.
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*/
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int samsung_usbphy_set_type(struct usb_phy *phy,
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enum samsung_usb_phy_type phy_type)
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{
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struct samsung_usbphy *sphy = phy_to_sphy(phy);
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sphy->phy_type = phy_type;
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return 0;
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}
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EXPORT_SYMBOL_GPL(samsung_usbphy_set_type);
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int samsung_usbphy_rate_to_clksel_64xx(struct samsung_usbphy *sphy,
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unsigned long rate)
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{
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unsigned int clksel;
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switch (rate) {
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case 12 * MHZ:
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clksel = PHYCLK_CLKSEL_12M;
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break;
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case 24 * MHZ:
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clksel = PHYCLK_CLKSEL_24M;
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break;
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case 48 * MHZ:
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clksel = PHYCLK_CLKSEL_48M;
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break;
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default:
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dev_err(sphy->dev,
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"Invalid reference clock frequency: %lu\n", rate);
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return -EINVAL;
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}
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return clksel;
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}
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EXPORT_SYMBOL_GPL(samsung_usbphy_rate_to_clksel_64xx);
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int samsung_usbphy_rate_to_clksel_4x12(struct samsung_usbphy *sphy,
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unsigned long rate)
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{
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unsigned int clksel;
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switch (rate) {
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case 9600 * KHZ:
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clksel = FSEL_CLKSEL_9600K;
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break;
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case 10 * MHZ:
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clksel = FSEL_CLKSEL_10M;
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break;
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case 12 * MHZ:
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clksel = FSEL_CLKSEL_12M;
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break;
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case 19200 * KHZ:
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clksel = FSEL_CLKSEL_19200K;
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break;
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case 20 * MHZ:
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clksel = FSEL_CLKSEL_20M;
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break;
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case 24 * MHZ:
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clksel = FSEL_CLKSEL_24M;
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break;
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case 50 * MHZ:
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clksel = FSEL_CLKSEL_50M;
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break;
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default:
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dev_err(sphy->dev,
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"Invalid reference clock frequency: %lu\n", rate);
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return -EINVAL;
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}
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return clksel;
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}
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EXPORT_SYMBOL_GPL(samsung_usbphy_rate_to_clksel_4x12);
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/*
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* Returns reference clock frequency selection value
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*/
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int samsung_usbphy_get_refclk_freq(struct samsung_usbphy *sphy)
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{
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struct clk *ref_clk;
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unsigned long rate;
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int refclk_freq;
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/*
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* In exynos5250 USB host and device PHY use
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* external crystal clock XXTI
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*/
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if (sphy->drv_data->cpu_type == TYPE_EXYNOS5250)
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ref_clk = clk_get(sphy->dev, "ext_xtal");
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else
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ref_clk = clk_get(sphy->dev, "xusbxti");
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if (IS_ERR(ref_clk)) {
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dev_err(sphy->dev, "Failed to get reference clock\n");
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return PTR_ERR(ref_clk);
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}
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rate = clk_get_rate(ref_clk);
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refclk_freq = sphy->drv_data->rate_to_clksel(sphy, rate);
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clk_put(ref_clk);
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return refclk_freq;
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}
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EXPORT_SYMBOL_GPL(samsung_usbphy_get_refclk_freq);
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