5b0f5a3f60
- support both v2 and v1 style smd channels - support both v2 and v1 smsm shared state - update smsm state defines and smem item enum - prep work for dealing with smd to qdsp6 - simplify some smem access to minimize use of smem_alloc() at runtime Signed-off-by: Brian Swetland <swetland@google.com> Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
206 lines
5.4 KiB
C
206 lines
5.4 KiB
C
/* arch/arm/mach-msm/smd_private.h
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*
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* Copyright (C) 2007 Google, Inc.
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* Copyright (c) 2007 QUALCOMM Incorporated
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef _ARCH_ARM_MACH_MSM_MSM_SMD_PRIVATE_H_
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#define _ARCH_ARM_MACH_MSM_MSM_SMD_PRIVATE_H_
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struct smem_heap_info
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{
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unsigned initialized;
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unsigned free_offset;
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unsigned heap_remaining;
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unsigned reserved;
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};
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struct smem_heap_entry
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{
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unsigned allocated;
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unsigned offset;
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unsigned size;
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unsigned reserved;
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};
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struct smem_proc_comm
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{
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unsigned command;
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unsigned status;
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unsigned data1;
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unsigned data2;
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};
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#define PC_APPS 0
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#define PC_MODEM 1
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#define VERSION_SMD 0
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#define VERSION_QDSP6 4
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#define VERSION_APPS_SBL 6
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#define VERSION_MODEM_SBL 7
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#define VERSION_APPS 8
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#define VERSION_MODEM 9
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struct smem_shared
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{
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struct smem_proc_comm proc_comm[4];
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unsigned version[32];
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struct smem_heap_info heap_info;
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struct smem_heap_entry heap_toc[512];
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};
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#define SMSM_V1_SIZE (sizeof(unsigned) * 8)
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#define SMSM_V1_STATE_APPS 0x0000
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#define SMSM_V1_STATE_MODEM 0x0004
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#define SMSM_V1_STATE_DSP 0x0008
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#define SMSM_V2_SIZE (sizeof(unsigned) * 4)
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#define SMSM_V2_STATE_APPS 0x0004
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#define SMSM_V2_STATE_MODEM 0x000C
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struct smsm_interrupt_info
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{
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uint32_t aArm_en_mask;
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uint32_t aArm_interrupts_pending;
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uint32_t aArm_wakeup_reason;
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};
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#define SZ_DIAG_ERR_MSG 0xC8
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#define ID_DIAG_ERR_MSG SMEM_DIAG_ERR_MESSAGE
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#define ID_SMD_CHANNELS SMEM_SMD_BASE_ID
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#define ID_SHARED_STATE SMEM_SMSM_SHARED_STATE
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#define ID_CH_ALLOC_TBL SMEM_CHANNEL_ALLOC_TBL
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#define SMSM_INIT 0x00000001
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#define SMSM_SMDINIT 0x00000008
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#define SMSM_RPCINIT 0x00000020
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#define SMSM_RESET 0x00000040
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#define SMSM_RSA 0x00000080
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#define SMSM_RUN 0x00000100
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#define SMSM_PWRC 0x00000200
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#define SMSM_TIMEWAIT 0x00000400
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#define SMSM_TIMEINIT 0x00000800
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#define SMSM_PWRC_EARLY_EXIT 0x00001000
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#define SMSM_WFPI 0x00002000
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#define SMSM_SLEEP 0x00004000
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#define SMSM_SLEEPEXIT 0x00008000
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#define SMSM_APPS_REBOOT 0x00020000
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#define SMSM_SYSTEM_POWER_DOWN 0x00040000
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#define SMSM_SYSTEM_REBOOT 0x00080000
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#define SMSM_SYSTEM_DOWNLOAD 0x00100000
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#define SMSM_PWRC_SUSPEND 0x00200000
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#define SMSM_APPS_SHUTDOWN 0x00400000
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#define SMSM_SMD_LOOPBACK 0x00800000
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#define SMSM_RUN_QUIET 0x01000000
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#define SMSM_MODEM_WAIT 0x02000000
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#define SMSM_MODEM_BREAK 0x04000000
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#define SMSM_MODEM_CONTINUE 0x08000000
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#define SMSM_UNKNOWN 0x80000000
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#define SMSM_WKUP_REASON_RPC 0x00000001
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#define SMSM_WKUP_REASON_INT 0x00000002
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#define SMSM_WKUP_REASON_GPIO 0x00000004
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#define SMSM_WKUP_REASON_TIMER 0x00000008
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#define SMSM_WKUP_REASON_ALARM 0x00000010
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#define SMSM_WKUP_REASON_RESET 0x00000020
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void *smem_alloc(unsigned id, unsigned size);
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int smsm_change_state(uint32_t clear_mask, uint32_t set_mask);
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uint32_t smsm_get_state(void);
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int smsm_set_sleep_duration(uint32_t delay);
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int smsm_set_interrupt_info(struct smsm_interrupt_info *info);
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void smsm_print_sleep_info(void);
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#define SMEM_NUM_SMD_CHANNELS 64
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typedef enum
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{
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/* fixed items */
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SMEM_PROC_COMM = 0,
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SMEM_HEAP_INFO,
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SMEM_ALLOCATION_TABLE,
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SMEM_VERSION_INFO,
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SMEM_HW_RESET_DETECT,
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SMEM_AARM_WARM_BOOT,
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SMEM_DIAG_ERR_MESSAGE,
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SMEM_SPINLOCK_ARRAY,
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SMEM_MEMORY_BARRIER_LOCATION,
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/* dynamic items */
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SMEM_AARM_PARTITION_TABLE,
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SMEM_AARM_BAD_BLOCK_TABLE,
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SMEM_RESERVE_BAD_BLOCKS,
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SMEM_WM_UUID,
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SMEM_CHANNEL_ALLOC_TBL,
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SMEM_SMD_BASE_ID,
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SMEM_SMEM_LOG_IDX = SMEM_SMD_BASE_ID + SMEM_NUM_SMD_CHANNELS,
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SMEM_SMEM_LOG_EVENTS,
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SMEM_SMEM_STATIC_LOG_IDX,
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SMEM_SMEM_STATIC_LOG_EVENTS,
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SMEM_SMEM_SLOW_CLOCK_SYNC,
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SMEM_SMEM_SLOW_CLOCK_VALUE,
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SMEM_BIO_LED_BUF,
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SMEM_SMSM_SHARED_STATE,
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SMEM_SMSM_INT_INFO,
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SMEM_SMSM_SLEEP_DELAY,
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SMEM_SMSM_LIMIT_SLEEP,
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SMEM_SLEEP_POWER_COLLAPSE_DISABLED,
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SMEM_KEYPAD_KEYS_PRESSED,
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SMEM_KEYPAD_STATE_UPDATED,
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SMEM_KEYPAD_STATE_IDX,
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SMEM_GPIO_INT,
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SMEM_MDDI_LCD_IDX,
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SMEM_MDDI_HOST_DRIVER_STATE,
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SMEM_MDDI_LCD_DISP_STATE,
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SMEM_LCD_CUR_PANEL,
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SMEM_MARM_BOOT_SEGMENT_INFO,
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SMEM_AARM_BOOT_SEGMENT_INFO,
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SMEM_SLEEP_STATIC,
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SMEM_SCORPION_FREQUENCY,
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SMEM_SMD_PROFILES,
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SMEM_TSSC_BUSY,
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SMEM_HS_SUSPEND_FILTER_INFO,
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SMEM_BATT_INFO,
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SMEM_APPS_BOOT_MODE,
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SMEM_VERSION_FIRST,
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SMEM_VERSION_LAST = SMEM_VERSION_FIRST + 24,
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SMEM_OSS_RRCASN1_BUF1,
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SMEM_OSS_RRCASN1_BUF2,
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SMEM_ID_VENDOR0,
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SMEM_ID_VENDOR1,
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SMEM_ID_VENDOR2,
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SMEM_HW_SW_BUILD_ID,
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SMEM_SMD_BLOCK_PORT_BASE_ID,
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SMEM_SMD_BLOCK_PORT_PROC0_HEAP = SMEM_SMD_BLOCK_PORT_BASE_ID + SMEM_NUM_SMD_CHANNELS,
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SMEM_SMD_BLOCK_PORT_PROC1_HEAP = SMEM_SMD_BLOCK_PORT_PROC0_HEAP + SMEM_NUM_SMD_CHANNELS,
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SMEM_I2C_MUTEX = SMEM_SMD_BLOCK_PORT_PROC1_HEAP + SMEM_NUM_SMD_CHANNELS,
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SMEM_SCLK_CONVERSION,
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SMEM_SMD_SMSM_INTR_MUX,
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SMEM_SMSM_CPU_INTR_MASK,
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SMEM_APPS_DEM_SLAVE_DATA,
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SMEM_QDSP6_DEM_SLAVE_DATA,
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SMEM_CLKREGIM_BSP,
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SMEM_CLKREGIM_SOURCES,
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SMEM_SMD_FIFO_BASE_ID,
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SMEM_USABLE_RAM_PARTITION_TABLE = SMEM_SMD_FIFO_BASE_ID + SMEM_NUM_SMD_CHANNELS,
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SMEM_POWER_ON_STATUS_INFO,
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SMEM_DAL_AREA,
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SMEM_SMEM_LOG_POWER_IDX,
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SMEM_SMEM_LOG_POWER_WRAP,
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SMEM_SMEM_LOG_POWER_EVENTS,
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SMEM_ERR_CRASH_LOG,
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SMEM_ERR_F3_TRACE_LOG,
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SMEM_NUM_ITEMS,
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} smem_mem_type;
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#endif
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