384 lines
11 KiB
C
384 lines
11 KiB
C
/*
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* Copyright (C) 2012 - Virtual Open Systems and Columbia University
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* Authors: Rusty Russell <rusty@rustcorp.com.au>
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* Christoffer Dall <c.dall@virtualopensystems.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, version 2, as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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#include <linux/mm.h>
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#include <linux/kvm_host.h>
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#include <asm/kvm_arm.h>
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#include <asm/kvm_host.h>
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#include <asm/kvm_emulate.h>
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#include <asm/kvm_coproc.h>
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#include <asm/cacheflush.h>
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#include <asm/cputype.h>
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#include <trace/events/kvm.h>
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#include "trace.h"
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#include "coproc.h"
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/******************************************************************************
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* Co-processor emulation
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*****************************************************************************/
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int kvm_handle_cp10_id(struct kvm_vcpu *vcpu, struct kvm_run *run)
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{
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kvm_inject_undefined(vcpu);
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return 1;
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}
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int kvm_handle_cp_0_13_access(struct kvm_vcpu *vcpu, struct kvm_run *run)
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{
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/*
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* We can get here, if the host has been built without VFPv3 support,
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* but the guest attempted a floating point operation.
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*/
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kvm_inject_undefined(vcpu);
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return 1;
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}
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int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu, struct kvm_run *run)
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{
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kvm_inject_undefined(vcpu);
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return 1;
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}
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int kvm_handle_cp14_access(struct kvm_vcpu *vcpu, struct kvm_run *run)
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{
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kvm_inject_undefined(vcpu);
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return 1;
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}
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/* See note at ARM ARM B1.14.4 */
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static bool access_dcsw(struct kvm_vcpu *vcpu,
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const struct coproc_params *p,
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const struct coproc_reg *r)
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{
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u32 val;
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int cpu;
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cpu = get_cpu();
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if (!p->is_write)
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return read_from_write_only(vcpu, p);
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cpumask_setall(&vcpu->arch.require_dcache_flush);
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cpumask_clear_cpu(cpu, &vcpu->arch.require_dcache_flush);
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/* If we were already preempted, take the long way around */
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if (cpu != vcpu->arch.last_pcpu) {
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flush_cache_all();
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goto done;
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}
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val = *vcpu_reg(vcpu, p->Rt1);
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switch (p->CRm) {
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case 6: /* Upgrade DCISW to DCCISW, as per HCR.SWIO */
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case 14: /* DCCISW */
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asm volatile("mcr p15, 0, %0, c7, c14, 2" : : "r" (val));
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break;
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case 10: /* DCCSW */
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asm volatile("mcr p15, 0, %0, c7, c10, 2" : : "r" (val));
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break;
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}
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done:
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put_cpu();
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return true;
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}
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/*
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* We could trap ID_DFR0 and tell the guest we don't support performance
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* monitoring. Unfortunately the patch to make the kernel check ID_DFR0 was
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* NAKed, so it will read the PMCR anyway.
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*
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* Therefore we tell the guest we have 0 counters. Unfortunately, we
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* must always support PMCCNTR (the cycle counter): we just RAZ/WI for
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* all PM registers, which doesn't crash the guest kernel at least.
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*/
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static bool pm_fake(struct kvm_vcpu *vcpu,
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const struct coproc_params *p,
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const struct coproc_reg *r)
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{
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if (p->is_write)
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return ignore_write(vcpu, p);
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else
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return read_zero(vcpu, p);
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}
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#define access_pmcr pm_fake
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#define access_pmcntenset pm_fake
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#define access_pmcntenclr pm_fake
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#define access_pmovsr pm_fake
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#define access_pmselr pm_fake
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#define access_pmceid0 pm_fake
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#define access_pmceid1 pm_fake
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#define access_pmccntr pm_fake
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#define access_pmxevtyper pm_fake
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#define access_pmxevcntr pm_fake
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#define access_pmuserenr pm_fake
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#define access_pmintenset pm_fake
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#define access_pmintenclr pm_fake
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/* Architected CP15 registers.
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* Important: Must be sorted ascending by CRn, CRM, Op1, Op2
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*/
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static const struct coproc_reg cp15_regs[] = {
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/* CSSELR: swapped by interrupt.S. */
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{ CRn( 0), CRm( 0), Op1( 2), Op2( 0), is32,
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NULL, reset_unknown, c0_CSSELR },
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/* TTBR0/TTBR1: swapped by interrupt.S. */
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{ CRm( 2), Op1( 0), is64, NULL, reset_unknown64, c2_TTBR0 },
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{ CRm( 2), Op1( 1), is64, NULL, reset_unknown64, c2_TTBR1 },
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/* TTBCR: swapped by interrupt.S. */
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{ CRn( 2), CRm( 0), Op1( 0), Op2( 2), is32,
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NULL, reset_val, c2_TTBCR, 0x00000000 },
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/* DACR: swapped by interrupt.S. */
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{ CRn( 3), CRm( 0), Op1( 0), Op2( 0), is32,
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NULL, reset_unknown, c3_DACR },
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/* DFSR/IFSR/ADFSR/AIFSR: swapped by interrupt.S. */
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{ CRn( 5), CRm( 0), Op1( 0), Op2( 0), is32,
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NULL, reset_unknown, c5_DFSR },
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{ CRn( 5), CRm( 0), Op1( 0), Op2( 1), is32,
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NULL, reset_unknown, c5_IFSR },
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{ CRn( 5), CRm( 1), Op1( 0), Op2( 0), is32,
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NULL, reset_unknown, c5_ADFSR },
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{ CRn( 5), CRm( 1), Op1( 0), Op2( 1), is32,
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NULL, reset_unknown, c5_AIFSR },
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/* DFAR/IFAR: swapped by interrupt.S. */
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{ CRn( 6), CRm( 0), Op1( 0), Op2( 0), is32,
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NULL, reset_unknown, c6_DFAR },
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{ CRn( 6), CRm( 0), Op1( 0), Op2( 2), is32,
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NULL, reset_unknown, c6_IFAR },
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/*
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* DC{C,I,CI}SW operations:
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*/
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{ CRn( 7), CRm( 6), Op1( 0), Op2( 2), is32, access_dcsw},
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{ CRn( 7), CRm(10), Op1( 0), Op2( 2), is32, access_dcsw},
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{ CRn( 7), CRm(14), Op1( 0), Op2( 2), is32, access_dcsw},
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/*
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* Dummy performance monitor implementation.
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*/
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{ CRn( 9), CRm(12), Op1( 0), Op2( 0), is32, access_pmcr},
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{ CRn( 9), CRm(12), Op1( 0), Op2( 1), is32, access_pmcntenset},
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{ CRn( 9), CRm(12), Op1( 0), Op2( 2), is32, access_pmcntenclr},
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{ CRn( 9), CRm(12), Op1( 0), Op2( 3), is32, access_pmovsr},
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{ CRn( 9), CRm(12), Op1( 0), Op2( 5), is32, access_pmselr},
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{ CRn( 9), CRm(12), Op1( 0), Op2( 6), is32, access_pmceid0},
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{ CRn( 9), CRm(12), Op1( 0), Op2( 7), is32, access_pmceid1},
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{ CRn( 9), CRm(13), Op1( 0), Op2( 0), is32, access_pmccntr},
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{ CRn( 9), CRm(13), Op1( 0), Op2( 1), is32, access_pmxevtyper},
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{ CRn( 9), CRm(13), Op1( 0), Op2( 2), is32, access_pmxevcntr},
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{ CRn( 9), CRm(14), Op1( 0), Op2( 0), is32, access_pmuserenr},
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{ CRn( 9), CRm(14), Op1( 0), Op2( 1), is32, access_pmintenset},
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{ CRn( 9), CRm(14), Op1( 0), Op2( 2), is32, access_pmintenclr},
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/* PRRR/NMRR (aka MAIR0/MAIR1): swapped by interrupt.S. */
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{ CRn(10), CRm( 2), Op1( 0), Op2( 0), is32,
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NULL, reset_unknown, c10_PRRR},
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{ CRn(10), CRm( 2), Op1( 0), Op2( 1), is32,
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NULL, reset_unknown, c10_NMRR},
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/* VBAR: swapped by interrupt.S. */
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{ CRn(12), CRm( 0), Op1( 0), Op2( 0), is32,
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NULL, reset_val, c12_VBAR, 0x00000000 },
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/* CONTEXTIDR/TPIDRURW/TPIDRURO/TPIDRPRW: swapped by interrupt.S. */
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{ CRn(13), CRm( 0), Op1( 0), Op2( 1), is32,
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NULL, reset_val, c13_CID, 0x00000000 },
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{ CRn(13), CRm( 0), Op1( 0), Op2( 2), is32,
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NULL, reset_unknown, c13_TID_URW },
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{ CRn(13), CRm( 0), Op1( 0), Op2( 3), is32,
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NULL, reset_unknown, c13_TID_URO },
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{ CRn(13), CRm( 0), Op1( 0), Op2( 4), is32,
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NULL, reset_unknown, c13_TID_PRIV },
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};
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/* Target specific emulation tables */
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static struct kvm_coproc_target_table *target_tables[KVM_ARM_NUM_TARGETS];
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void kvm_register_target_coproc_table(struct kvm_coproc_target_table *table)
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{
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target_tables[table->target] = table;
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}
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/* Get specific register table for this target. */
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static const struct coproc_reg *get_target_table(unsigned target, size_t *num)
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{
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struct kvm_coproc_target_table *table;
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table = target_tables[target];
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*num = table->num;
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return table->table;
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}
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static const struct coproc_reg *find_reg(const struct coproc_params *params,
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const struct coproc_reg table[],
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unsigned int num)
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{
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unsigned int i;
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for (i = 0; i < num; i++) {
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const struct coproc_reg *r = &table[i];
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if (params->is_64bit != r->is_64)
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continue;
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if (params->CRn != r->CRn)
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continue;
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if (params->CRm != r->CRm)
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continue;
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if (params->Op1 != r->Op1)
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continue;
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if (params->Op2 != r->Op2)
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continue;
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return r;
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}
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return NULL;
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}
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static int emulate_cp15(struct kvm_vcpu *vcpu,
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const struct coproc_params *params)
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{
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size_t num;
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const struct coproc_reg *table, *r;
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trace_kvm_emulate_cp15_imp(params->Op1, params->Rt1, params->CRn,
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params->CRm, params->Op2, params->is_write);
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table = get_target_table(vcpu->arch.target, &num);
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/* Search target-specific then generic table. */
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r = find_reg(params, table, num);
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if (!r)
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r = find_reg(params, cp15_regs, ARRAY_SIZE(cp15_regs));
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if (likely(r)) {
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/* If we don't have an accessor, we should never get here! */
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BUG_ON(!r->access);
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if (likely(r->access(vcpu, params, r))) {
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/* Skip instruction, since it was emulated */
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kvm_skip_instr(vcpu, (vcpu->arch.hsr >> 25) & 1);
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return 1;
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}
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/* If access function fails, it should complain. */
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} else {
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kvm_err("Unsupported guest CP15 access at: %08x\n",
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*vcpu_pc(vcpu));
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print_cp_instr(params);
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}
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kvm_inject_undefined(vcpu);
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return 1;
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}
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/**
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* kvm_handle_cp15_64 -- handles a mrrc/mcrr trap on a guest CP15 access
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* @vcpu: The VCPU pointer
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* @run: The kvm_run struct
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*/
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int kvm_handle_cp15_64(struct kvm_vcpu *vcpu, struct kvm_run *run)
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{
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struct coproc_params params;
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params.CRm = (vcpu->arch.hsr >> 1) & 0xf;
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params.Rt1 = (vcpu->arch.hsr >> 5) & 0xf;
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params.is_write = ((vcpu->arch.hsr & 1) == 0);
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params.is_64bit = true;
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params.Op1 = (vcpu->arch.hsr >> 16) & 0xf;
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params.Op2 = 0;
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params.Rt2 = (vcpu->arch.hsr >> 10) & 0xf;
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params.CRn = 0;
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return emulate_cp15(vcpu, ¶ms);
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}
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static void reset_coproc_regs(struct kvm_vcpu *vcpu,
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const struct coproc_reg *table, size_t num)
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{
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unsigned long i;
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for (i = 0; i < num; i++)
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if (table[i].reset)
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table[i].reset(vcpu, &table[i]);
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}
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/**
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* kvm_handle_cp15_32 -- handles a mrc/mcr trap on a guest CP15 access
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* @vcpu: The VCPU pointer
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* @run: The kvm_run struct
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*/
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int kvm_handle_cp15_32(struct kvm_vcpu *vcpu, struct kvm_run *run)
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{
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struct coproc_params params;
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params.CRm = (vcpu->arch.hsr >> 1) & 0xf;
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params.Rt1 = (vcpu->arch.hsr >> 5) & 0xf;
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params.is_write = ((vcpu->arch.hsr & 1) == 0);
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params.is_64bit = false;
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params.CRn = (vcpu->arch.hsr >> 10) & 0xf;
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params.Op1 = (vcpu->arch.hsr >> 14) & 0x7;
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params.Op2 = (vcpu->arch.hsr >> 17) & 0x7;
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params.Rt2 = 0;
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return emulate_cp15(vcpu, ¶ms);
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}
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void kvm_coproc_table_init(void)
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{
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unsigned int i;
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/* Make sure tables are unique and in order. */
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for (i = 1; i < ARRAY_SIZE(cp15_regs); i++)
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BUG_ON(cmp_reg(&cp15_regs[i-1], &cp15_regs[i]) >= 0);
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}
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/**
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* kvm_reset_coprocs - sets cp15 registers to reset value
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* @vcpu: The VCPU pointer
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*
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* This function finds the right table above and sets the registers on the
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* virtual CPU struct to their architecturally defined reset values.
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*/
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void kvm_reset_coprocs(struct kvm_vcpu *vcpu)
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{
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size_t num;
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const struct coproc_reg *table;
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/* Catch someone adding a register without putting in reset entry. */
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memset(vcpu->arch.cp15, 0x42, sizeof(vcpu->arch.cp15));
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/* Generic chip reset first (so target could override). */
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reset_coproc_regs(vcpu, cp15_regs, ARRAY_SIZE(cp15_regs));
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table = get_target_table(vcpu->arch.target, &num);
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reset_coproc_regs(vcpu, table, num);
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for (num = 1; num < NR_CP15_REGS; num++)
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if (vcpu->arch.cp15[num] == 0x42424242)
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panic("Didn't reset vcpu->arch.cp15[%zi]", num);
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}
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