4505153954
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not write to the free software foundation inc 59 temple place suite 330 boston ma 02111 1307 usa extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 136 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190530000436.384967451@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
119 lines
3.6 KiB
C
119 lines
3.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* amd8111_edac.h, EDAC defs for AMD8111 hypertransport chip
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*
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* Copyright (c) 2008 Wind River Systems, Inc.
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*
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* Authors: Cao Qingtao <qingtao.cao@windriver.com>
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* Benjamin Walsh <benjamin.walsh@windriver.com>
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* Hu Yongqi <yongqi.hu@windriver.com>
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*/
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#ifndef _AMD8111_EDAC_H_
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#define _AMD8111_EDAC_H_
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/************************************************************
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* PCI Bridge Status and Command Register, DevA:0x04
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************************************************************/
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#define REG_PCI_STSCMD 0x04
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enum pci_stscmd_bits {
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PCI_STSCMD_SSE = BIT(30),
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PCI_STSCMD_RMA = BIT(29),
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PCI_STSCMD_RTA = BIT(28),
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PCI_STSCMD_SERREN = BIT(8),
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PCI_STSCMD_CLEAR_MASK = (PCI_STSCMD_SSE |
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PCI_STSCMD_RMA |
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PCI_STSCMD_RTA)
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};
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/************************************************************
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* PCI Bridge Memory Base-Limit Register, DevA:0x1c
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************************************************************/
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#define REG_MEM_LIM 0x1c
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enum mem_limit_bits {
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MEM_LIMIT_DPE = BIT(31),
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MEM_LIMIT_RSE = BIT(30),
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MEM_LIMIT_RMA = BIT(29),
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MEM_LIMIT_RTA = BIT(28),
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MEM_LIMIT_STA = BIT(27),
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MEM_LIMIT_MDPE = BIT(24),
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MEM_LIMIT_CLEAR_MASK = (MEM_LIMIT_DPE |
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MEM_LIMIT_RSE |
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MEM_LIMIT_RMA |
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MEM_LIMIT_RTA |
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MEM_LIMIT_STA |
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MEM_LIMIT_MDPE)
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};
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/************************************************************
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* HyperTransport Link Control Register, DevA:0xc4
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************************************************************/
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#define REG_HT_LINK 0xc4
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enum ht_link_bits {
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HT_LINK_LKFAIL = BIT(4),
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HT_LINK_CRCFEN = BIT(1),
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HT_LINK_CLEAR_MASK = (HT_LINK_LKFAIL)
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};
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/************************************************************
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* PCI Bridge Interrupt and Bridge Control, DevA:0x3c
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************************************************************/
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#define REG_PCI_INTBRG_CTRL 0x3c
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enum pci_intbrg_ctrl_bits {
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PCI_INTBRG_CTRL_DTSERREN = BIT(27),
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PCI_INTBRG_CTRL_DTSTAT = BIT(26),
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PCI_INTBRG_CTRL_MARSP = BIT(21),
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PCI_INTBRG_CTRL_SERREN = BIT(17),
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PCI_INTBRG_CTRL_PEREN = BIT(16),
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PCI_INTBRG_CTRL_CLEAR_MASK = (PCI_INTBRG_CTRL_DTSTAT),
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PCI_INTBRG_CTRL_POLL_MASK = (PCI_INTBRG_CTRL_DTSERREN |
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PCI_INTBRG_CTRL_MARSP |
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PCI_INTBRG_CTRL_SERREN)
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};
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/************************************************************
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* I/O Control 1 Register, DevB:0x40
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************************************************************/
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#define REG_IO_CTRL_1 0x40
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enum io_ctrl_1_bits {
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IO_CTRL_1_NMIONERR = BIT(7),
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IO_CTRL_1_LPC_ERR = BIT(6),
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IO_CTRL_1_PW2LPC = BIT(1),
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IO_CTRL_1_CLEAR_MASK = (IO_CTRL_1_LPC_ERR | IO_CTRL_1_PW2LPC)
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};
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/************************************************************
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* Legacy I/O Space Registers
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************************************************************/
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#define REG_AT_COMPAT 0x61
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enum at_compat_bits {
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AT_COMPAT_SERR = BIT(7),
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AT_COMPAT_IOCHK = BIT(6),
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AT_COMPAT_CLRIOCHK = BIT(3),
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AT_COMPAT_CLRSERR = BIT(2),
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};
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struct amd8111_dev_info {
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u16 err_dev; /* PCI Device ID */
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struct pci_dev *dev;
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int edac_idx; /* device index */
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char *ctl_name;
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struct edac_device_ctl_info *edac_dev;
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void (*init)(struct amd8111_dev_info *dev_info);
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void (*exit)(struct amd8111_dev_info *dev_info);
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void (*check)(struct edac_device_ctl_info *edac_dev);
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};
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struct amd8111_pci_info {
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u16 err_dev; /* PCI Device ID */
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struct pci_dev *dev;
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int edac_idx; /* pci index */
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const char *ctl_name;
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struct edac_pci_ctl_info *edac_dev;
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void (*init)(struct amd8111_pci_info *dev_info);
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void (*exit)(struct amd8111_pci_info *dev_info);
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void (*check)(struct edac_pci_ctl_info *edac_dev);
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};
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#endif /* _AMD8111_EDAC_H_ */
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