108 lines
3.6 KiB
Plaintext
108 lines
3.6 KiB
Plaintext
Freescale i.MX8QXP/QM JPEG encoder/decoder
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=========================
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jpegdec node
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--------------
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This is the device node for the JPEG decoder in i.MXQXP/QM SoC, an
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ISO/IEC 10918-1 JPEG standard compliant decoder, for Baseline
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and Extended Sequential DCT modes.
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Required properties:
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- compatible : "fsl,imx8-jpgdec";
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- reg : base address and length of the register set for the device;
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- interrupts : list of interrupts for jpeg decoder
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- clocks : list of clock specifiers, see
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Documentation/devicetree/bindings/clock/clock-bindings.txt for details;
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- assigned-clock-rates : the value should be 200MHz;
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- power-domains : a list of phandle to the power domain, see
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Documentation/devicetree/bindings/power/power_domain.txt for details;
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Optional properties:
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- clock-names : must contain clock names to match entries in the
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clock property;
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- power-domain-name : must contain matching names for entries in the
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the power-domains property.
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example:
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jpegdec: jpegdec@58400000 {
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compatible = "fsl,imx8-jpgdec";
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reg = <0x58400000 0x00050000 >;
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interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&img_jpeg_dec_clk 0>,
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<&img_jpeg_dec_clk 1>;
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clock-names = "per", "ipg";
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assigned-clocks = <&img_jpeg_dec_clk 0>,
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<&img_jpeg_dec_clk 1>;
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assigned-clock-rates = <200000000>;
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power-domains = <&pd IMX_SC_R_ISI_CH0>,
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<&pd IMX_SC_R_MJPEG_DEC_MP>,
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<&pd IMX_SC_R_MJPEG_DEC_S0>,
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<&pd IMX_SC_R_MJPEG_DEC_S1>,
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<&pd IMX_SC_R_MJPEG_DEC_S2>,
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<&pd IMX_SC_R_MJPEG_DEC_S3>;
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power-domain-names = "pd_isi_ch0", "pd_dec_mp",
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"pd_dec_s0", "pd_dec_s1",
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"pd_dec_s2", "pd_dec_s3";
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status = "disabled";
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jpegenc node
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--------------
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This is the device node for the JPEG encoder in i.MXQXP/QM SoC,
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similar with the JPEG decoder above.
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Required properties:
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- compatible : "fsl,imx8-jpgenc";
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- reg : base address and length of the register set for the device;
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- interrupts : list of interrupts for jpeg encoder
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- clocks : list of clock specifiers, see
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Documentation/devicetree/bindings/clock/clock-bindings.txt for details;
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- assigned-clock-rates : the value should be 200MHz;
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- power-domains : a list of phandle to the power domain, see
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Documentation/devicetree/bindings/power/power_domain.txt for details;
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Optional properties:
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- clock-names : must contain clock names to match entries in the
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clock property;
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- power-domain-name : must contain matching names for entries in the
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the power-domains property.
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example:
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jpegenc: jpegenc@58450000 {
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compatible = "fsl,imx8-jpgenc";
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reg = <0x58450000 0x00050000 >;
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interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&img_jpeg_enc_clk 0>,
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<&img_jpeg_enc_clk 1>;
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clock-names = "per", "ipg";
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assigned-clocks = <&img_jpeg_enc_clk 0>,
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<&img_jpeg_enc_clk 1>;
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assigned-clock-rates = <200000000>;
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power-domains = <&pd IMX_SC_R_ISI_CH0>,
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<&pd IMX_SC_R_MJPEG_ENC_MP>,
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<&pd IMX_SC_R_MJPEG_ENC_S0>,
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<&pd IMX_SC_R_MJPEG_ENC_S1>,
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<&pd IMX_SC_R_MJPEG_ENC_S2>,
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<&pd IMX_SC_R_MJPEG_ENC_S3>;
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power-domain-names = "pd_isi_ch0", "pd_enc_mp",
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"pd_enc_s0", "pd_enc_s1",
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"pd_enc_s2", "pd_enc_s3";
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status = "disabled";
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};
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