c91e02bd97
Use perf framework to manage hardware instruction and data breakpoints. Add two new ptrace calls: PTRACE_GETHBPREGS and PTRACE_SETHBPREGS to query and set instruction and data breakpoints. Address bit 0 choose instruction (0) or data (1) break register, bits 31..1 are the register number. Both calls transfer two 32-bit words: address (0) and control (1). Instruction breakpoint contorl word is 0 to clear breakpoint, 1 to set. Data breakpoint control word bit 31 is 'trigger on store', bit 30 is 'trigger on load, bits 29..0 are length. Length 0 is used to clear a breakpoint. To set a breakpoint length must be a power of 2 in the range 1..64 and the address must be length-aligned. Introduce new thread_info flag: TIF_DB_DISABLED. Set it if debug exception is raised by the kernel code accessing watched userspace address and disable corresponding data breakpoint. On exit to userspace check that flag and, if set, restore all data breakpoints. Handle debug exceptions raised with PS.EXCM set. This may happen when window overflow/underflow handler or fast exception handler hits data breakpoint, in which case save and disable all data breakpoints, single-step faulting instruction and restore data breakpoints. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
83 lines
2 KiB
C
83 lines
2 KiB
C
/*
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* Xtensa IRQ flags handling functions
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2001 - 2005 Tensilica Inc.
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* Copyright (C) 2015 Cadence Design Systems Inc.
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*/
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#ifndef _XTENSA_IRQFLAGS_H
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#define _XTENSA_IRQFLAGS_H
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#include <linux/types.h>
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#include <asm/processor.h>
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static inline unsigned long arch_local_save_flags(void)
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{
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unsigned long flags;
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asm volatile("rsr %0, ps" : "=a" (flags));
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return flags;
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}
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static inline unsigned long arch_local_irq_save(void)
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{
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unsigned long flags;
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#if XTENSA_FAKE_NMI
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#if defined(CONFIG_DEBUG_KERNEL) && (LOCKLEVEL | TOPLEVEL) >= XCHAL_DEBUGLEVEL
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unsigned long tmp;
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asm volatile("rsr %0, ps\t\n"
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"extui %1, %0, 0, 4\t\n"
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"bgei %1, "__stringify(LOCKLEVEL)", 1f\t\n"
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"rsil %0, "__stringify(LOCKLEVEL)"\n"
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"1:"
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: "=a" (flags), "=a" (tmp) :: "memory");
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#else
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asm volatile("rsr %0, ps\t\n"
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"or %0, %0, %1\t\n"
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"xsr %0, ps\t\n"
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"rsync"
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: "=&a" (flags) : "a" (LOCKLEVEL) : "memory");
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#endif
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#else
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asm volatile("rsil %0, "__stringify(LOCKLEVEL)
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: "=a" (flags) :: "memory");
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#endif
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return flags;
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}
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static inline void arch_local_irq_disable(void)
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{
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arch_local_irq_save();
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}
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static inline void arch_local_irq_enable(void)
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{
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unsigned long flags;
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asm volatile("rsil %0, 0" : "=a" (flags) :: "memory");
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}
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static inline void arch_local_irq_restore(unsigned long flags)
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{
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asm volatile("wsr %0, ps; rsync"
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:: "a" (flags) : "memory");
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}
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static inline bool arch_irqs_disabled_flags(unsigned long flags)
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{
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#if XCHAL_EXCM_LEVEL < LOCKLEVEL || (1 << PS_EXCM_BIT) < LOCKLEVEL
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#error "XCHAL_EXCM_LEVEL and 1<<PS_EXCM_BIT must be no less than LOCKLEVEL"
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#endif
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return (flags & (PS_INTLEVEL_MASK | (1 << PS_EXCM_BIT))) >= LOCKLEVEL;
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}
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static inline bool arch_irqs_disabled(void)
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{
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return arch_irqs_disabled_flags(arch_local_save_flags());
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}
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#endif /* _XTENSA_IRQFLAGS_H */
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