a9f2fc628e
Make kernel load address explicit, independent of the selected MMU configuration and configurable from Kconfig. Do not restrict it to the first 512MB of the physical address space. Cleanup kernel memory layout macros: - rename VECBASE_RESET_VADDR to VECBASE_VADDR, XC_VADDR to VECTOR_VADDR; - drop VIRTUAL_MEMORY_ADDRESS and LOAD_MEMORY_ADDRESS; - introduce PHYS_OFFSET and use it in __va and __pa definitions; - synchronize MMU/noMMU vectors, drop unused NMI vector; - replace hardcoded vectors offset of 0x3000 with Kconfig symbol. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
75 lines
2.1 KiB
C
75 lines
2.1 KiB
C
/*
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* Kernel virtual memory layout definitions.
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*
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* This file is subject to the terms and conditions of the GNU General
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* Public License. See the file "COPYING" in the main directory of
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* this archive for more details.
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*
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* Copyright (C) 2016 Cadence Design Systems Inc.
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*/
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#ifndef _XTENSA_KMEM_LAYOUT_H
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#define _XTENSA_KMEM_LAYOUT_H
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#include <asm/types.h>
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#ifdef CONFIG_MMU
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/*
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* Fixed TLB translations in the processor.
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*/
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#define XCHAL_PAGE_TABLE_VADDR __XTENSA_UL_CONST(0x80000000)
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#define XCHAL_PAGE_TABLE_SIZE __XTENSA_UL_CONST(0x00400000)
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#if defined(CONFIG_XTENSA_KSEG_MMU_V2)
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#define XCHAL_KSEG_CACHED_VADDR __XTENSA_UL_CONST(0xd0000000)
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#define XCHAL_KSEG_BYPASS_VADDR __XTENSA_UL_CONST(0xd8000000)
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#define XCHAL_KSEG_SIZE __XTENSA_UL_CONST(0x08000000)
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#define XCHAL_KSEG_ALIGNMENT __XTENSA_UL_CONST(0x08000000)
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#define XCHAL_KSEG_TLB_WAY 5
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#define XCHAL_KIO_TLB_WAY 6
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#elif defined(CONFIG_XTENSA_KSEG_256M)
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#define XCHAL_KSEG_CACHED_VADDR __XTENSA_UL_CONST(0xb0000000)
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#define XCHAL_KSEG_BYPASS_VADDR __XTENSA_UL_CONST(0xc0000000)
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#define XCHAL_KSEG_SIZE __XTENSA_UL_CONST(0x10000000)
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#define XCHAL_KSEG_ALIGNMENT __XTENSA_UL_CONST(0x10000000)
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#define XCHAL_KSEG_TLB_WAY 6
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#define XCHAL_KIO_TLB_WAY 6
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#elif defined(CONFIG_XTENSA_KSEG_512M)
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#define XCHAL_KSEG_CACHED_VADDR __XTENSA_UL_CONST(0xa0000000)
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#define XCHAL_KSEG_BYPASS_VADDR __XTENSA_UL_CONST(0xc0000000)
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#define XCHAL_KSEG_SIZE __XTENSA_UL_CONST(0x20000000)
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#define XCHAL_KSEG_ALIGNMENT __XTENSA_UL_CONST(0x10000000)
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#define XCHAL_KSEG_TLB_WAY 6
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#define XCHAL_KIO_TLB_WAY 6
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#else
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#error Unsupported KSEG configuration
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#endif
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#ifdef CONFIG_KSEG_PADDR
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#define XCHAL_KSEG_PADDR __XTENSA_UL_CONST(CONFIG_KSEG_PADDR)
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#else
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#define XCHAL_KSEG_PADDR __XTENSA_UL_CONST(0x00000000)
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#endif
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#if XCHAL_KSEG_PADDR & (XCHAL_KSEG_ALIGNMENT - 1)
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#error XCHAL_KSEG_PADDR is not properly aligned to XCHAL_KSEG_ALIGNMENT
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#endif
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#else
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#define XCHAL_KSEG_CACHED_VADDR __XTENSA_UL_CONST(0xd0000000)
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#define XCHAL_KSEG_BYPASS_VADDR __XTENSA_UL_CONST(0xd8000000)
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#define XCHAL_KSEG_SIZE __XTENSA_UL_CONST(0x08000000)
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#endif
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#endif
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