dbc9f36cf7
Now that the SPDX tag is in all vt6655 files, that identifies the license in a specific and legally-defined manner. So the extra GPL text wording can be removed as it is no longer needed at all. This is done on a quest to remove the 700+ different ways that files in the kernel describe the GPL license text. And there's unneeded stuff like the address (sometimes incorrect) for the FSF which is never needed. No copyright headers or other non-license-description text was removed. Cc: Forest Bond <forest@alittletooquiet.net> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
871 lines
19 KiB
C
871 lines
19 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
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* All rights reserved.
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*
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* File: mac.c
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*
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* Purpose: MAC routines
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*
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* Author: Tevin Chen
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*
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* Date: May 21, 1996
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*
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* Functions:
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* MACbIsRegBitsOn - Test if All test Bits On
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* MACbIsRegBitsOff - Test if All test Bits Off
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* MACbIsIntDisable - Test if MAC interrupt disable
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* MACvSetShortRetryLimit - Set 802.11 Short Retry limit
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* MACvSetLongRetryLimit - Set 802.11 Long Retry limit
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* MACvSetLoopbackMode - Set MAC Loopback Mode
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* MACvSaveContext - Save Context of MAC Registers
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* MACvRestoreContext - Restore Context of MAC Registers
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* MACbSoftwareReset - Software Reset MAC
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* MACbSafeRxOff - Turn Off MAC Rx
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* MACbSafeTxOff - Turn Off MAC Tx
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* MACbSafeStop - Stop MAC function
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* MACbShutdown - Shut down MAC
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* MACvInitialize - Initialize MAC
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* MACvSetCurrRxDescAddr - Set Rx Descriptors Address
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* MACvSetCurrTx0DescAddr - Set Tx0 Descriptors Address
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* MACvSetCurrTx1DescAddr - Set Tx1 Descriptors Address
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* MACvTimer0MicroSDelay - Micro Second Delay Loop by MAC
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*
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* Revision History:
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* 08-22-2003 Kyle Hsu : Porting MAC functions from sim53
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* 09-03-2003 Bryan YC Fan : Add MACvClearBusSusInd()&
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* MACvEnableBusSusEn()
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* 09-18-2003 Jerry Chen : Add MACvSetKeyEntry & MACvDisableKeyEntry
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*
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*/
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#include "tmacro.h"
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#include "mac.h"
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/*
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* Description:
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* Test if all test bits on
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*
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* Parameters:
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* In:
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* io_base - Base Address for MAC
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* byRegOfs - Offset of MAC Register
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* byTestBits - Test bits
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* Out:
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* none
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*
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* Return Value: true if all test bits On; otherwise false
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*
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*/
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bool MACbIsRegBitsOn(struct vnt_private *priv, unsigned char byRegOfs,
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unsigned char byTestBits)
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{
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void __iomem *io_base = priv->PortOffset;
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return (ioread8(io_base + byRegOfs) & byTestBits) == byTestBits;
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}
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/*
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* Description:
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* Test if all test bits off
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*
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* Parameters:
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* In:
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* io_base - Base Address for MAC
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* byRegOfs - Offset of MAC Register
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* byTestBits - Test bits
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* Out:
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* none
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*
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* Return Value: true if all test bits Off; otherwise false
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*
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*/
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bool MACbIsRegBitsOff(struct vnt_private *priv, unsigned char byRegOfs,
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unsigned char byTestBits)
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{
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void __iomem *io_base = priv->PortOffset;
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return !(ioread8(io_base + byRegOfs) & byTestBits);
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}
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/*
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* Description:
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* Test if MAC interrupt disable
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*
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* Parameters:
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* In:
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* io_base - Base Address for MAC
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* Out:
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* none
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*
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* Return Value: true if interrupt is disable; otherwise false
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*
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*/
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bool MACbIsIntDisable(struct vnt_private *priv)
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{
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void __iomem *io_base = priv->PortOffset;
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if (ioread32(io_base + MAC_REG_IMR))
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return false;
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return true;
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}
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/*
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* Description:
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* Set 802.11 Short Retry Limit
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*
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* Parameters:
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* In:
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* io_base - Base Address for MAC
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* byRetryLimit- Retry Limit
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* Out:
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* none
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*
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* Return Value: none
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*
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*/
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void MACvSetShortRetryLimit(struct vnt_private *priv,
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unsigned char byRetryLimit)
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{
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void __iomem *io_base = priv->PortOffset;
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/* set SRT */
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iowrite8(byRetryLimit, io_base + MAC_REG_SRT);
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}
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/*
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* Description:
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* Set 802.11 Long Retry Limit
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*
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* Parameters:
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* In:
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* io_base - Base Address for MAC
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* byRetryLimit- Retry Limit
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* Out:
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* none
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*
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* Return Value: none
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*
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*/
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void MACvSetLongRetryLimit(struct vnt_private *priv,
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unsigned char byRetryLimit)
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{
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void __iomem *io_base = priv->PortOffset;
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/* set LRT */
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iowrite8(byRetryLimit, io_base + MAC_REG_LRT);
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}
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/*
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* Description:
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* Set MAC Loopback mode
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*
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* Parameters:
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* In:
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* io_base - Base Address for MAC
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* byLoopbackMode - Loopback Mode
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* Out:
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* none
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*
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* Return Value: none
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*
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*/
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void MACvSetLoopbackMode(struct vnt_private *priv, unsigned char byLoopbackMode)
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{
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void __iomem *io_base = priv->PortOffset;
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byLoopbackMode <<= 6;
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/* set TCR */
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iowrite8((ioread8(io_base + MAC_REG_TEST) & 0x3f) | byLoopbackMode,
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io_base + MAC_REG_TEST);
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}
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/*
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* Description:
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* Save MAC registers to context buffer
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*
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* Parameters:
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* In:
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* io_base - Base Address for MAC
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* Out:
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* cxt_buf - Context buffer
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*
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* Return Value: none
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*
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*/
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void MACvSaveContext(struct vnt_private *priv, unsigned char *cxt_buf)
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{
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void __iomem *io_base = priv->PortOffset;
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/* read page0 register */
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memcpy_fromio(cxt_buf, io_base, MAC_MAX_CONTEXT_SIZE_PAGE0);
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MACvSelectPage1(io_base);
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/* read page1 register */
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memcpy_fromio(cxt_buf + MAC_MAX_CONTEXT_SIZE_PAGE0, io_base,
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MAC_MAX_CONTEXT_SIZE_PAGE1);
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MACvSelectPage0(io_base);
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}
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/*
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* Description:
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* Restore MAC registers from context buffer
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*
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* Parameters:
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* In:
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* io_base - Base Address for MAC
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* cxt_buf - Context buffer
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* Out:
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* none
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*
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* Return Value: none
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*
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*/
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void MACvRestoreContext(struct vnt_private *priv, unsigned char *cxt_buf)
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{
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void __iomem *io_base = priv->PortOffset;
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MACvSelectPage1(io_base);
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/* restore page1 */
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memcpy_toio(io_base, cxt_buf + MAC_MAX_CONTEXT_SIZE_PAGE0,
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MAC_MAX_CONTEXT_SIZE_PAGE1);
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MACvSelectPage0(io_base);
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/* restore RCR,TCR,IMR... */
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memcpy_toio(io_base + MAC_REG_RCR, cxt_buf + MAC_REG_RCR,
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MAC_REG_ISR - MAC_REG_RCR);
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/* restore MAC Config. */
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memcpy_toio(io_base + MAC_REG_LRT, cxt_buf + MAC_REG_LRT,
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MAC_REG_PAGE1SEL - MAC_REG_LRT);
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iowrite8(*(cxt_buf + MAC_REG_CFG), io_base + MAC_REG_CFG);
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/* restore PS Config. */
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memcpy_toio(io_base + MAC_REG_PSCFG, cxt_buf + MAC_REG_PSCFG,
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MAC_REG_BBREGCTL - MAC_REG_PSCFG);
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/* restore CURR_RX_DESC_ADDR, CURR_TX_DESC_ADDR */
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iowrite32(*(u32 *)(cxt_buf + MAC_REG_TXDMAPTR0),
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io_base + MAC_REG_TXDMAPTR0);
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iowrite32(*(u32 *)(cxt_buf + MAC_REG_AC0DMAPTR),
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io_base + MAC_REG_AC0DMAPTR);
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iowrite32(*(u32 *)(cxt_buf + MAC_REG_BCNDMAPTR),
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io_base + MAC_REG_BCNDMAPTR);
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iowrite32(*(u32 *)(cxt_buf + MAC_REG_RXDMAPTR0),
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io_base + MAC_REG_RXDMAPTR0);
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iowrite32(*(u32 *)(cxt_buf + MAC_REG_RXDMAPTR1),
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io_base + MAC_REG_RXDMAPTR1);
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}
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/*
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* Description:
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* Software Reset MAC
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*
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* Parameters:
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* In:
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* io_base - Base Address for MAC
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* Out:
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* none
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*
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* Return Value: true if Reset Success; otherwise false
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*
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*/
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bool MACbSoftwareReset(struct vnt_private *priv)
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{
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void __iomem *io_base = priv->PortOffset;
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unsigned short ww;
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/* turn on HOSTCR_SOFTRST, just write 0x01 to reset */
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iowrite8(0x01, io_base + MAC_REG_HOSTCR);
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for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
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if (!(ioread8(io_base + MAC_REG_HOSTCR) & HOSTCR_SOFTRST))
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break;
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}
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if (ww == W_MAX_TIMEOUT)
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return false;
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return true;
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}
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/*
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* Description:
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* save some important register's value, then do reset, then restore
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* register's value
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*
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* Parameters:
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* In:
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* io_base - Base Address for MAC
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* Out:
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* none
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*
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* Return Value: true if success; otherwise false
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*
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*/
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bool MACbSafeSoftwareReset(struct vnt_private *priv)
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{
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unsigned char abyTmpRegData[MAC_MAX_CONTEXT_SIZE_PAGE0 + MAC_MAX_CONTEXT_SIZE_PAGE1];
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bool bRetVal;
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/* PATCH....
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* save some important register's value, then do
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* reset, then restore register's value
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*/
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/* save MAC context */
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MACvSaveContext(priv, abyTmpRegData);
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/* do reset */
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bRetVal = MACbSoftwareReset(priv);
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/* restore MAC context, except CR0 */
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MACvRestoreContext(priv, abyTmpRegData);
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return bRetVal;
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}
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/*
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* Description:
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* Turn Off MAC Rx
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*
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* Parameters:
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* In:
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* io_base - Base Address for MAC
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* Out:
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* none
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*
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* Return Value: true if success; otherwise false
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*
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*/
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bool MACbSafeRxOff(struct vnt_private *priv)
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{
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void __iomem *io_base = priv->PortOffset;
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unsigned short ww;
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/* turn off wow temp for turn off Rx safely */
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/* Clear RX DMA0,1 */
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iowrite32(DMACTL_CLRRUN, io_base + MAC_REG_RXDMACTL0);
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iowrite32(DMACTL_CLRRUN, io_base + MAC_REG_RXDMACTL1);
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for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
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if (!(ioread32(io_base + MAC_REG_RXDMACTL0) & DMACTL_RUN))
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break;
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}
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if (ww == W_MAX_TIMEOUT) {
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pr_debug(" DBG_PORT80(0x10)\n");
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return false;
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}
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for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
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if (!(ioread32(io_base + MAC_REG_RXDMACTL1) & DMACTL_RUN))
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break;
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}
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if (ww == W_MAX_TIMEOUT) {
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pr_debug(" DBG_PORT80(0x11)\n");
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return false;
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}
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/* try to safe shutdown RX */
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MACvRegBitsOff(io_base, MAC_REG_HOSTCR, HOSTCR_RXON);
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/* W_MAX_TIMEOUT is the timeout period */
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for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
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if (!(ioread8(io_base + MAC_REG_HOSTCR) & HOSTCR_RXONST))
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break;
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}
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if (ww == W_MAX_TIMEOUT) {
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pr_debug(" DBG_PORT80(0x12)\n");
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return false;
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}
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return true;
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}
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/*
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* Description:
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* Turn Off MAC Tx
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*
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* Parameters:
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* In:
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* io_base - Base Address for MAC
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* Out:
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* none
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*
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* Return Value: true if success; otherwise false
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*
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*/
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bool MACbSafeTxOff(struct vnt_private *priv)
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{
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void __iomem *io_base = priv->PortOffset;
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unsigned short ww;
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/* Clear TX DMA */
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/* Tx0 */
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iowrite32(DMACTL_CLRRUN, io_base + MAC_REG_TXDMACTL0);
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/* AC0 */
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iowrite32(DMACTL_CLRRUN, io_base + MAC_REG_AC0DMACTL);
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for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
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if (!(ioread32(io_base + MAC_REG_TXDMACTL0) & DMACTL_RUN))
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break;
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}
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if (ww == W_MAX_TIMEOUT) {
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pr_debug(" DBG_PORT80(0x20)\n");
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return false;
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}
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for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
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if (!(ioread32(io_base + MAC_REG_AC0DMACTL) & DMACTL_RUN))
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break;
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}
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if (ww == W_MAX_TIMEOUT) {
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pr_debug(" DBG_PORT80(0x21)\n");
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return false;
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}
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/* try to safe shutdown TX */
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MACvRegBitsOff(io_base, MAC_REG_HOSTCR, HOSTCR_TXON);
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/* W_MAX_TIMEOUT is the timeout period */
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for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
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if (!(ioread8(io_base + MAC_REG_HOSTCR) & HOSTCR_TXONST))
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break;
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}
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if (ww == W_MAX_TIMEOUT) {
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pr_debug(" DBG_PORT80(0x24)\n");
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return false;
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}
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return true;
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}
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/*
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* Description:
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* Stop MAC function
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*
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* Parameters:
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* In:
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* io_base - Base Address for MAC
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* Out:
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* none
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*
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* Return Value: true if success; otherwise false
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*
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*/
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bool MACbSafeStop(struct vnt_private *priv)
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{
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void __iomem *io_base = priv->PortOffset;
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MACvRegBitsOff(io_base, MAC_REG_TCR, TCR_AUTOBCNTX);
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if (!MACbSafeRxOff(priv)) {
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pr_debug(" MACbSafeRxOff == false)\n");
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MACbSafeSoftwareReset(priv);
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return false;
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}
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if (!MACbSafeTxOff(priv)) {
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pr_debug(" MACbSafeTxOff == false)\n");
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MACbSafeSoftwareReset(priv);
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return false;
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}
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MACvRegBitsOff(io_base, MAC_REG_HOSTCR, HOSTCR_MACEN);
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return true;
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}
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/*
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* Description:
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* Shut Down MAC
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*
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* Parameters:
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* In:
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* io_base - Base Address for MAC
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* Out:
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* none
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*
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* Return Value: true if success; otherwise false
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*
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*/
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bool MACbShutdown(struct vnt_private *priv)
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{
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void __iomem *io_base = priv->PortOffset;
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/* disable MAC IMR */
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MACvIntDisable(io_base);
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MACvSetLoopbackMode(priv, MAC_LB_INTERNAL);
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/* stop the adapter */
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if (!MACbSafeStop(priv)) {
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MACvSetLoopbackMode(priv, MAC_LB_NONE);
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return false;
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}
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MACvSetLoopbackMode(priv, MAC_LB_NONE);
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return true;
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}
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/*
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* Description:
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* Initialize MAC
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*
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* Parameters:
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* In:
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* io_base - Base Address for MAC
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* Out:
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* none
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*
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* Return Value: none
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*
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*/
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void MACvInitialize(struct vnt_private *priv)
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{
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void __iomem *io_base = priv->PortOffset;
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/* clear sticky bits */
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MACvClearStckDS(io_base);
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/* disable force PME-enable */
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iowrite8(PME_OVR, io_base + MAC_REG_PMC1);
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/* only 3253 A */
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/* do reset */
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MACbSoftwareReset(priv);
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/* reset TSF counter */
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iowrite8(TFTCTL_TSFCNTRST, io_base + MAC_REG_TFTCTL);
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/* enable TSF counter */
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iowrite8(TFTCTL_TSFCNTREN, io_base + MAC_REG_TFTCTL);
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}
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/*
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* Description:
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* Set the chip with current rx descriptor address
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*
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* Parameters:
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* In:
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* io_base - Base Address for MAC
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* curr_desc_addr - Descriptor Address
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* Out:
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* none
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*
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* Return Value: none
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*
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*/
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void MACvSetCurrRx0DescAddr(struct vnt_private *priv, u32 curr_desc_addr)
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{
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void __iomem *io_base = priv->PortOffset;
|
|
unsigned short ww;
|
|
unsigned char org_dma_ctl;
|
|
|
|
org_dma_ctl = ioread8(io_base + MAC_REG_RXDMACTL0);
|
|
if (org_dma_ctl & DMACTL_RUN)
|
|
iowrite8(DMACTL_RUN, io_base + MAC_REG_RXDMACTL0 + 2);
|
|
|
|
for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
|
|
if (!(ioread8(io_base + MAC_REG_RXDMACTL0) & DMACTL_RUN))
|
|
break;
|
|
}
|
|
|
|
iowrite32(curr_desc_addr, io_base + MAC_REG_RXDMAPTR0);
|
|
if (org_dma_ctl & DMACTL_RUN)
|
|
iowrite8(DMACTL_RUN, io_base + MAC_REG_RXDMACTL0);
|
|
}
|
|
|
|
/*
|
|
* Description:
|
|
* Set the chip with current rx descriptor address
|
|
*
|
|
* Parameters:
|
|
* In:
|
|
* io_base - Base Address for MAC
|
|
* curr_desc_addr - Descriptor Address
|
|
* Out:
|
|
* none
|
|
*
|
|
* Return Value: none
|
|
*
|
|
*/
|
|
void MACvSetCurrRx1DescAddr(struct vnt_private *priv, u32 curr_desc_addr)
|
|
{
|
|
void __iomem *io_base = priv->PortOffset;
|
|
unsigned short ww;
|
|
unsigned char org_dma_ctl;
|
|
|
|
org_dma_ctl = ioread8(io_base + MAC_REG_RXDMACTL1);
|
|
if (org_dma_ctl & DMACTL_RUN)
|
|
iowrite8(DMACTL_RUN, io_base + MAC_REG_RXDMACTL1 + 2);
|
|
|
|
for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
|
|
if (!(ioread8(io_base + MAC_REG_RXDMACTL1) & DMACTL_RUN))
|
|
break;
|
|
}
|
|
|
|
iowrite32(curr_desc_addr, io_base + MAC_REG_RXDMAPTR1);
|
|
if (org_dma_ctl & DMACTL_RUN)
|
|
iowrite8(DMACTL_RUN, io_base + MAC_REG_RXDMACTL1);
|
|
|
|
}
|
|
|
|
/*
|
|
* Description:
|
|
* Set the chip with current tx0 descriptor address
|
|
*
|
|
* Parameters:
|
|
* In:
|
|
* io_base - Base Address for MAC
|
|
* curr_desc_addr - Descriptor Address
|
|
* Out:
|
|
* none
|
|
*
|
|
* Return Value: none
|
|
*
|
|
*/
|
|
void MACvSetCurrTx0DescAddrEx(struct vnt_private *priv,
|
|
u32 curr_desc_addr)
|
|
{
|
|
void __iomem *io_base = priv->PortOffset;
|
|
unsigned short ww;
|
|
unsigned char org_dma_ctl;
|
|
|
|
org_dma_ctl = ioread8(io_base + MAC_REG_TXDMACTL0);
|
|
if (org_dma_ctl & DMACTL_RUN)
|
|
iowrite8(DMACTL_RUN, io_base + MAC_REG_TXDMACTL0 + 2);
|
|
|
|
for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
|
|
if (!(ioread8(io_base + MAC_REG_TXDMACTL0) & DMACTL_RUN))
|
|
break;
|
|
}
|
|
|
|
iowrite32(curr_desc_addr, io_base + MAC_REG_TXDMAPTR0);
|
|
if (org_dma_ctl & DMACTL_RUN)
|
|
iowrite8(DMACTL_RUN, io_base + MAC_REG_TXDMACTL0);
|
|
}
|
|
|
|
/*
|
|
* Description:
|
|
* Set the chip with current AC0 descriptor address
|
|
*
|
|
* Parameters:
|
|
* In:
|
|
* io_base - Base Address for MAC
|
|
* curr_desc_addr - Descriptor Address
|
|
* Out:
|
|
* none
|
|
*
|
|
* Return Value: none
|
|
*
|
|
*/
|
|
/* TxDMA1 = AC0DMA */
|
|
void MACvSetCurrAC0DescAddrEx(struct vnt_private *priv,
|
|
u32 curr_desc_addr)
|
|
{
|
|
void __iomem *io_base = priv->PortOffset;
|
|
unsigned short ww;
|
|
unsigned char org_dma_ctl;
|
|
|
|
org_dma_ctl = ioread8(io_base + MAC_REG_AC0DMACTL);
|
|
if (org_dma_ctl & DMACTL_RUN)
|
|
iowrite8(DMACTL_RUN, io_base + MAC_REG_AC0DMACTL + 2);
|
|
|
|
for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
|
|
if (!(ioread8(io_base + MAC_REG_AC0DMACTL) & DMACTL_RUN))
|
|
break;
|
|
}
|
|
if (ww == W_MAX_TIMEOUT)
|
|
pr_debug(" DBG_PORT80(0x26)\n");
|
|
iowrite32(curr_desc_addr, io_base + MAC_REG_AC0DMAPTR);
|
|
if (org_dma_ctl & DMACTL_RUN)
|
|
iowrite8(DMACTL_RUN, io_base + MAC_REG_AC0DMACTL);
|
|
}
|
|
|
|
void MACvSetCurrTXDescAddr(int iTxType, struct vnt_private *priv,
|
|
u32 curr_desc_addr)
|
|
{
|
|
if (iTxType == TYPE_AC0DMA)
|
|
MACvSetCurrAC0DescAddrEx(priv, curr_desc_addr);
|
|
else if (iTxType == TYPE_TXDMA0)
|
|
MACvSetCurrTx0DescAddrEx(priv, curr_desc_addr);
|
|
}
|
|
|
|
/*
|
|
* Description:
|
|
* Micro Second Delay via MAC
|
|
*
|
|
* Parameters:
|
|
* In:
|
|
* io_base - Base Address for MAC
|
|
* uDelay - Delay time (timer resolution is 4 us)
|
|
* Out:
|
|
* none
|
|
*
|
|
* Return Value: none
|
|
*
|
|
*/
|
|
void MACvTimer0MicroSDelay(struct vnt_private *priv, unsigned int uDelay)
|
|
{
|
|
void __iomem *io_base = priv->PortOffset;
|
|
unsigned char byValue;
|
|
unsigned int uu, ii;
|
|
|
|
iowrite8(0, io_base + MAC_REG_TMCTL0);
|
|
iowrite32(uDelay, io_base + MAC_REG_TMDATA0);
|
|
iowrite8((TMCTL_TMD | TMCTL_TE), io_base + MAC_REG_TMCTL0);
|
|
for (ii = 0; ii < 66; ii++) { /* assume max PCI clock is 66Mhz */
|
|
for (uu = 0; uu < uDelay; uu++) {
|
|
byValue = ioread8(io_base + MAC_REG_TMCTL0);
|
|
if ((byValue == 0) ||
|
|
(byValue & TMCTL_TSUSP)) {
|
|
iowrite8(0, io_base + MAC_REG_TMCTL0);
|
|
return;
|
|
}
|
|
}
|
|
}
|
|
iowrite8(0, io_base + MAC_REG_TMCTL0);
|
|
}
|
|
|
|
/*
|
|
* Description:
|
|
* Micro Second One shot timer via MAC
|
|
*
|
|
* Parameters:
|
|
* In:
|
|
* io_base - Base Address for MAC
|
|
* uDelay - Delay time
|
|
* Out:
|
|
* none
|
|
*
|
|
* Return Value: none
|
|
*
|
|
*/
|
|
void MACvOneShotTimer1MicroSec(struct vnt_private *priv,
|
|
unsigned int uDelayTime)
|
|
{
|
|
void __iomem *io_base = priv->PortOffset;
|
|
|
|
iowrite8(0, io_base + MAC_REG_TMCTL1);
|
|
iowrite32(uDelayTime, io_base + MAC_REG_TMDATA1);
|
|
iowrite8((TMCTL_TMD | TMCTL_TE), io_base + MAC_REG_TMCTL1);
|
|
}
|
|
|
|
void MACvSetMISCFifo(struct vnt_private *priv, unsigned short offset,
|
|
u32 data)
|
|
{
|
|
void __iomem *io_base = priv->PortOffset;
|
|
|
|
if (offset > 273)
|
|
return;
|
|
iowrite16(offset, io_base + MAC_REG_MISCFFNDEX);
|
|
iowrite32(data, io_base + MAC_REG_MISCFFDATA);
|
|
iowrite16(MISCFFCTL_WRITE, io_base + MAC_REG_MISCFFCTL);
|
|
}
|
|
|
|
bool MACbPSWakeup(struct vnt_private *priv)
|
|
{
|
|
void __iomem *io_base = priv->PortOffset;
|
|
unsigned int ww;
|
|
/* Read PSCTL */
|
|
if (MACbIsRegBitsOff(priv, MAC_REG_PSCTL, PSCTL_PS))
|
|
return true;
|
|
|
|
/* Disable PS */
|
|
MACvRegBitsOff(io_base, MAC_REG_PSCTL, PSCTL_PSEN);
|
|
|
|
/* Check if SyncFlushOK */
|
|
for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
|
|
if (ioread8(io_base + MAC_REG_PSCTL) & PSCTL_WAKEDONE)
|
|
break;
|
|
}
|
|
if (ww == W_MAX_TIMEOUT) {
|
|
pr_debug(" DBG_PORT80(0x33)\n");
|
|
return false;
|
|
}
|
|
return true;
|
|
}
|
|
|
|
/*
|
|
* Description:
|
|
* Set the Key by MISCFIFO
|
|
*
|
|
* Parameters:
|
|
* In:
|
|
* io_base - Base Address for MAC
|
|
*
|
|
* Out:
|
|
* none
|
|
*
|
|
* Return Value: none
|
|
*
|
|
*/
|
|
|
|
void MACvSetKeyEntry(struct vnt_private *priv, unsigned short wKeyCtl,
|
|
unsigned int uEntryIdx, unsigned int uKeyIdx,
|
|
unsigned char *pbyAddr, u32 *pdwKey,
|
|
unsigned char byLocalID)
|
|
{
|
|
void __iomem *io_base = priv->PortOffset;
|
|
unsigned short offset;
|
|
u32 data;
|
|
int ii;
|
|
|
|
if (byLocalID <= 1)
|
|
return;
|
|
|
|
pr_debug("%s\n", __func__);
|
|
offset = MISCFIFO_KEYETRY0;
|
|
offset += (uEntryIdx * MISCFIFO_KEYENTRYSIZE);
|
|
|
|
data = 0;
|
|
data |= wKeyCtl;
|
|
data <<= 16;
|
|
data |= MAKEWORD(*(pbyAddr + 4), *(pbyAddr + 5));
|
|
pr_debug("1. offset: %d, Data: %X, KeyCtl:%X\n",
|
|
offset, data, wKeyCtl);
|
|
|
|
iowrite16(offset, io_base + MAC_REG_MISCFFNDEX);
|
|
iowrite32(data, io_base + MAC_REG_MISCFFDATA);
|
|
iowrite16(MISCFFCTL_WRITE, io_base + MAC_REG_MISCFFCTL);
|
|
offset++;
|
|
|
|
data = 0;
|
|
data |= *(pbyAddr + 3);
|
|
data <<= 8;
|
|
data |= *(pbyAddr + 2);
|
|
data <<= 8;
|
|
data |= *(pbyAddr + 1);
|
|
data <<= 8;
|
|
data |= *pbyAddr;
|
|
pr_debug("2. offset: %d, Data: %X\n", offset, data);
|
|
|
|
iowrite16(offset, io_base + MAC_REG_MISCFFNDEX);
|
|
iowrite32(data, io_base + MAC_REG_MISCFFDATA);
|
|
iowrite16(MISCFFCTL_WRITE, io_base + MAC_REG_MISCFFCTL);
|
|
offset++;
|
|
|
|
offset += (uKeyIdx * 4);
|
|
for (ii = 0; ii < 4; ii++) {
|
|
/* always push 128 bits */
|
|
pr_debug("3.(%d) offset: %d, Data: %X\n",
|
|
ii, offset + ii, *pdwKey);
|
|
iowrite16(offset + ii, io_base + MAC_REG_MISCFFNDEX);
|
|
iowrite32(*pdwKey++, io_base + MAC_REG_MISCFFDATA);
|
|
iowrite16(MISCFFCTL_WRITE, io_base + MAC_REG_MISCFFCTL);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Description:
|
|
* Disable the Key Entry by MISCFIFO
|
|
*
|
|
* Parameters:
|
|
* In:
|
|
* io_base - Base Address for MAC
|
|
*
|
|
* Out:
|
|
* none
|
|
*
|
|
* Return Value: none
|
|
*
|
|
*/
|
|
void MACvDisableKeyEntry(struct vnt_private *priv, unsigned int uEntryIdx)
|
|
{
|
|
void __iomem *io_base = priv->PortOffset;
|
|
unsigned short offset;
|
|
|
|
offset = MISCFIFO_KEYETRY0;
|
|
offset += (uEntryIdx * MISCFIFO_KEYENTRYSIZE);
|
|
|
|
iowrite16(offset, io_base + MAC_REG_MISCFFNDEX);
|
|
iowrite32(0, io_base + MAC_REG_MISCFFDATA);
|
|
iowrite16(MISCFFCTL_WRITE, io_base + MAC_REG_MISCFFCTL);
|
|
}
|