18a4df7051
Initial support for Tegra 114 SoC. This is expected to be included in the board DTS files, Tegra 114 SoC based evaluation board family. Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
115 lines
2.2 KiB
Plaintext
115 lines
2.2 KiB
Plaintext
/include/ "skeleton.dtsi"
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/ {
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compatible = "nvidia,tegra114";
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interrupt-parent = <&gic>;
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gic: interrupt-controller {
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compatible = "arm,cortex-a15-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x50041000 0x1000>,
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<0x50042000 0x1000>,
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<0x50044000 0x2000>,
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<0x50046000 0x2000>;
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interrupts = <1 9 0xf04>;
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};
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timer@60005000 {
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compatible = "nvidia,tegra114-timer", "nvidia,tegra20-timer";
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reg = <0x60005000 0x400>;
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interrupts = <0 0 0x04
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0 1 0x04
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0 41 0x04
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0 42 0x04
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0 121 0x04
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0 122 0x04>;
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};
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tegra_car: clock {
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compatible = "nvidia,tegra114-car, nvidia,tegra30-car";
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reg = <0x60006000 0x1000>;
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#clock-cells = <1>;
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};
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serial@70006000 {
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compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
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reg = <0x70006000 0x40>;
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reg-shift = <2>;
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interrupts = <0 36 0x04>;
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status = "disabled";
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};
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serial@70006040 {
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compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
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reg = <0x70006040 0x40>;
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reg-shift = <2>;
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interrupts = <0 37 0x04>;
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status = "disabled";
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};
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serial@70006200 {
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compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
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reg = <0x70006200 0x100>;
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reg-shift = <2>;
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interrupts = <0 46 0x04>;
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status = "disabled";
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};
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serial@70006300 {
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compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
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reg = <0x70006300 0x100>;
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reg-shift = <2>;
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interrupts = <0 90 0x04>;
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status = "disabled";
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};
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rtc {
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compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
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reg = <0x7000e000 0x100>;
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interrupts = <0 2 0x04>;
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};
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pmc {
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compatible = "nvidia,tegra114-pmc", "nvidia,tegra30-pmc";
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reg = <0x7000e400 0x400>;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <1>;
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};
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cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <2>;
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};
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cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <3>;
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};
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <1 13 0xf08>,
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<1 14 0xf08>,
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<1 11 0xf08>,
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<1 10 0xf08>;
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};
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};
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