![Chris Wilson](/assets/img/avatar_default.png)
Miles Lane reported the following error: 2 locks held by cat/4179: #0: (&p->lock){+.+.+.}, at: [<c10a3884>] seq_read+0x25/0x315 #1: (&dev_priv->mm.active_list_lock){+.+...}, at: [<c119a854>] i915_batchbuffer_info+0x2b/0x124 Pid: 4179, comm: cat Not tainted 2.6.32-rc5-git1 #2 Call Trace: [<c104874f>] ? __debug_show_held_locks+0x1e/0x20 [<c1023fb0>] __might_sleep+0xf0/0xf7 [<c101c393>] kmap+0x17/0x58 [<c119a8d6>] i915_batchbuffer_info+0xad/0x124 [<c10a39bf>] seq_read+0x160/0x315 [<c108fb8c>] ? rw_verify_area+0x98/0xbb [<c10a385f>] ? seq_read+0x0/0x315 [<c1090331>] vfs_read+0x75/0xa9 [<c10903f9>] sys_read+0x3b/0x5d [<c1002a8f>] sysenter_do_call+0x12/0x36 The fix is relatively simple, use the atomic variants of kmap() that avoid the potential sleep. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Miles Lane <miles.lane@gmail.com> Signed-off-by: Eric Anholt <eric@anholt.net>
448 lines
14 KiB
C
448 lines
14 KiB
C
/*
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* Copyright © 2008 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* Authors:
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* Eric Anholt <eric@anholt.net>
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* Keith Packard <keithp@keithp.com>
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*
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*/
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#include <linux/seq_file.h>
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#include "drmP.h"
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#include "drm.h"
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#include "i915_drm.h"
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#include "i915_drv.h"
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#define DRM_I915_RING_DEBUG 1
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#if defined(CONFIG_DEBUG_FS)
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#define ACTIVE_LIST 1
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#define FLUSHING_LIST 2
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#define INACTIVE_LIST 3
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static const char *get_pin_flag(struct drm_i915_gem_object *obj_priv)
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{
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if (obj_priv->user_pin_count > 0)
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return "P";
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else if (obj_priv->pin_count > 0)
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return "p";
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else
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return " ";
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}
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static const char *get_tiling_flag(struct drm_i915_gem_object *obj_priv)
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{
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switch (obj_priv->tiling_mode) {
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default:
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case I915_TILING_NONE: return " ";
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case I915_TILING_X: return "X";
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case I915_TILING_Y: return "Y";
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}
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}
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static int i915_gem_object_list_info(struct seq_file *m, void *data)
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{
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struct drm_info_node *node = (struct drm_info_node *) m->private;
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uintptr_t list = (uintptr_t) node->info_ent->data;
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struct list_head *head;
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struct drm_device *dev = node->minor->dev;
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drm_i915_private_t *dev_priv = dev->dev_private;
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struct drm_i915_gem_object *obj_priv;
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spinlock_t *lock = NULL;
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switch (list) {
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case ACTIVE_LIST:
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seq_printf(m, "Active:\n");
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lock = &dev_priv->mm.active_list_lock;
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head = &dev_priv->mm.active_list;
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break;
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case INACTIVE_LIST:
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seq_printf(m, "Inactive:\n");
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head = &dev_priv->mm.inactive_list;
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break;
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case FLUSHING_LIST:
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seq_printf(m, "Flushing:\n");
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head = &dev_priv->mm.flushing_list;
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break;
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default:
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DRM_INFO("Ooops, unexpected list\n");
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return 0;
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}
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if (lock)
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spin_lock(lock);
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list_for_each_entry(obj_priv, head, list)
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{
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struct drm_gem_object *obj = obj_priv->obj;
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seq_printf(m, " %p: %s %8zd %08x %08x %d %s",
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obj,
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get_pin_flag(obj_priv),
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obj->size,
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obj->read_domains, obj->write_domain,
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obj_priv->last_rendering_seqno,
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obj_priv->dirty ? "dirty" : "");
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if (obj->name)
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seq_printf(m, " (name: %d)", obj->name);
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if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
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seq_printf(m, " (fence: %d)", obj_priv->fence_reg);
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if (obj_priv->gtt_space != NULL)
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seq_printf(m, " (gtt_offset: %08x)", obj_priv->gtt_offset);
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seq_printf(m, "\n");
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}
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if (lock)
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spin_unlock(lock);
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return 0;
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}
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static int i915_gem_request_info(struct seq_file *m, void *data)
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{
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struct drm_info_node *node = (struct drm_info_node *) m->private;
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struct drm_device *dev = node->minor->dev;
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drm_i915_private_t *dev_priv = dev->dev_private;
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struct drm_i915_gem_request *gem_request;
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seq_printf(m, "Request:\n");
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list_for_each_entry(gem_request, &dev_priv->mm.request_list, list) {
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seq_printf(m, " %d @ %d\n",
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gem_request->seqno,
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(int) (jiffies - gem_request->emitted_jiffies));
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}
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return 0;
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}
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static int i915_gem_seqno_info(struct seq_file *m, void *data)
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{
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struct drm_info_node *node = (struct drm_info_node *) m->private;
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struct drm_device *dev = node->minor->dev;
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drm_i915_private_t *dev_priv = dev->dev_private;
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if (dev_priv->hw_status_page != NULL) {
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seq_printf(m, "Current sequence: %d\n",
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i915_get_gem_seqno(dev));
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} else {
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seq_printf(m, "Current sequence: hws uninitialized\n");
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}
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seq_printf(m, "Waiter sequence: %d\n",
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dev_priv->mm.waiting_gem_seqno);
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seq_printf(m, "IRQ sequence: %d\n", dev_priv->mm.irq_gem_seqno);
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return 0;
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}
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static int i915_interrupt_info(struct seq_file *m, void *data)
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{
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struct drm_info_node *node = (struct drm_info_node *) m->private;
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struct drm_device *dev = node->minor->dev;
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drm_i915_private_t *dev_priv = dev->dev_private;
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if (!IS_IGDNG(dev)) {
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seq_printf(m, "Interrupt enable: %08x\n",
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I915_READ(IER));
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seq_printf(m, "Interrupt identity: %08x\n",
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I915_READ(IIR));
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seq_printf(m, "Interrupt mask: %08x\n",
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I915_READ(IMR));
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seq_printf(m, "Pipe A stat: %08x\n",
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I915_READ(PIPEASTAT));
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seq_printf(m, "Pipe B stat: %08x\n",
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I915_READ(PIPEBSTAT));
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} else {
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seq_printf(m, "North Display Interrupt enable: %08x\n",
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I915_READ(DEIER));
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seq_printf(m, "North Display Interrupt identity: %08x\n",
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I915_READ(DEIIR));
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seq_printf(m, "North Display Interrupt mask: %08x\n",
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I915_READ(DEIMR));
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seq_printf(m, "South Display Interrupt enable: %08x\n",
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I915_READ(SDEIER));
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seq_printf(m, "South Display Interrupt identity: %08x\n",
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I915_READ(SDEIIR));
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seq_printf(m, "South Display Interrupt mask: %08x\n",
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I915_READ(SDEIMR));
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seq_printf(m, "Graphics Interrupt enable: %08x\n",
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I915_READ(GTIER));
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seq_printf(m, "Graphics Interrupt identity: %08x\n",
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I915_READ(GTIIR));
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seq_printf(m, "Graphics Interrupt mask: %08x\n",
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I915_READ(GTIMR));
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}
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seq_printf(m, "Interrupts received: %d\n",
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atomic_read(&dev_priv->irq_received));
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if (dev_priv->hw_status_page != NULL) {
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seq_printf(m, "Current sequence: %d\n",
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i915_get_gem_seqno(dev));
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} else {
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seq_printf(m, "Current sequence: hws uninitialized\n");
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}
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seq_printf(m, "Waiter sequence: %d\n",
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dev_priv->mm.waiting_gem_seqno);
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seq_printf(m, "IRQ sequence: %d\n",
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dev_priv->mm.irq_gem_seqno);
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return 0;
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}
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static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
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{
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struct drm_info_node *node = (struct drm_info_node *) m->private;
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struct drm_device *dev = node->minor->dev;
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drm_i915_private_t *dev_priv = dev->dev_private;
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int i;
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seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
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seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
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for (i = 0; i < dev_priv->num_fence_regs; i++) {
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struct drm_gem_object *obj = dev_priv->fence_regs[i].obj;
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if (obj == NULL) {
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seq_printf(m, "Fenced object[%2d] = unused\n", i);
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} else {
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struct drm_i915_gem_object *obj_priv;
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obj_priv = obj->driver_private;
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seq_printf(m, "Fenced object[%2d] = %p: %s "
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"%08x %08zx %08x %s %08x %08x %d",
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i, obj, get_pin_flag(obj_priv),
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obj_priv->gtt_offset,
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obj->size, obj_priv->stride,
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get_tiling_flag(obj_priv),
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obj->read_domains, obj->write_domain,
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obj_priv->last_rendering_seqno);
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if (obj->name)
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seq_printf(m, " (name: %d)", obj->name);
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seq_printf(m, "\n");
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}
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}
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return 0;
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}
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static int i915_hws_info(struct seq_file *m, void *data)
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{
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struct drm_info_node *node = (struct drm_info_node *) m->private;
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struct drm_device *dev = node->minor->dev;
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drm_i915_private_t *dev_priv = dev->dev_private;
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int i;
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volatile u32 *hws;
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hws = (volatile u32 *)dev_priv->hw_status_page;
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if (hws == NULL)
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return 0;
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for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
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seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
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i * 4,
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hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
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}
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return 0;
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}
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static void i915_dump_pages(struct seq_file *m, struct page **pages, int page_count)
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{
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int page, i;
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uint32_t *mem;
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for (page = 0; page < page_count; page++) {
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mem = kmap_atomic(pages[page], KM_USER0);
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for (i = 0; i < PAGE_SIZE; i += 4)
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seq_printf(m, "%08x : %08x\n", i, mem[i / 4]);
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kunmap_atomic(pages[page], KM_USER0);
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}
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}
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static int i915_batchbuffer_info(struct seq_file *m, void *data)
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{
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struct drm_info_node *node = (struct drm_info_node *) m->private;
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struct drm_device *dev = node->minor->dev;
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drm_i915_private_t *dev_priv = dev->dev_private;
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struct drm_gem_object *obj;
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struct drm_i915_gem_object *obj_priv;
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int ret;
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spin_lock(&dev_priv->mm.active_list_lock);
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list_for_each_entry(obj_priv, &dev_priv->mm.active_list, list) {
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obj = obj_priv->obj;
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if (obj->read_domains & I915_GEM_DOMAIN_COMMAND) {
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ret = i915_gem_object_get_pages(obj);
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if (ret) {
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DRM_ERROR("Failed to get pages: %d\n", ret);
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spin_unlock(&dev_priv->mm.active_list_lock);
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return ret;
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}
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seq_printf(m, "--- gtt_offset = 0x%08x\n", obj_priv->gtt_offset);
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i915_dump_pages(m, obj_priv->pages, obj->size / PAGE_SIZE);
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i915_gem_object_put_pages(obj);
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}
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}
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spin_unlock(&dev_priv->mm.active_list_lock);
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return 0;
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}
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static int i915_ringbuffer_data(struct seq_file *m, void *data)
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{
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struct drm_info_node *node = (struct drm_info_node *) m->private;
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struct drm_device *dev = node->minor->dev;
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drm_i915_private_t *dev_priv = dev->dev_private;
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u8 *virt;
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uint32_t *ptr, off;
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if (!dev_priv->ring.ring_obj) {
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seq_printf(m, "No ringbuffer setup\n");
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return 0;
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}
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virt = dev_priv->ring.virtual_start;
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for (off = 0; off < dev_priv->ring.Size; off += 4) {
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ptr = (uint32_t *)(virt + off);
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seq_printf(m, "%08x : %08x\n", off, *ptr);
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}
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return 0;
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}
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static int i915_ringbuffer_info(struct seq_file *m, void *data)
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{
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struct drm_info_node *node = (struct drm_info_node *) m->private;
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struct drm_device *dev = node->minor->dev;
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drm_i915_private_t *dev_priv = dev->dev_private;
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unsigned int head, tail;
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head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
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tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
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seq_printf(m, "RingHead : %08x\n", head);
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seq_printf(m, "RingTail : %08x\n", tail);
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seq_printf(m, "RingSize : %08lx\n", dev_priv->ring.Size);
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seq_printf(m, "Acthd : %08x\n", I915_READ(IS_I965G(dev) ? ACTHD_I965 : ACTHD));
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return 0;
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}
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static int i915_error_state(struct seq_file *m, void *unused)
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{
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struct drm_info_node *node = (struct drm_info_node *) m->private;
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struct drm_device *dev = node->minor->dev;
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drm_i915_private_t *dev_priv = dev->dev_private;
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struct drm_i915_error_state *error;
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unsigned long flags;
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spin_lock_irqsave(&dev_priv->error_lock, flags);
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if (!dev_priv->first_error) {
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seq_printf(m, "no error state collected\n");
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goto out;
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}
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error = dev_priv->first_error;
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seq_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec,
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error->time.tv_usec);
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seq_printf(m, "EIR: 0x%08x\n", error->eir);
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seq_printf(m, " PGTBL_ER: 0x%08x\n", error->pgtbl_er);
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seq_printf(m, " INSTPM: 0x%08x\n", error->instpm);
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seq_printf(m, " IPEIR: 0x%08x\n", error->ipeir);
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seq_printf(m, " IPEHR: 0x%08x\n", error->ipehr);
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seq_printf(m, " INSTDONE: 0x%08x\n", error->instdone);
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seq_printf(m, " ACTHD: 0x%08x\n", error->acthd);
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if (IS_I965G(dev)) {
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seq_printf(m, " INSTPS: 0x%08x\n", error->instps);
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seq_printf(m, " INSTDONE1: 0x%08x\n", error->instdone1);
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}
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out:
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spin_unlock_irqrestore(&dev_priv->error_lock, flags);
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return 0;
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}
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static int i915_registers_info(struct seq_file *m, void *data) {
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struct drm_info_node *node = (struct drm_info_node *) m->private;
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struct drm_device *dev = node->minor->dev;
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drm_i915_private_t *dev_priv = dev->dev_private;
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uint32_t reg;
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#define DUMP_RANGE(start, end) \
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for (reg=start; reg < end; reg += 4) \
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seq_printf(m, "%08x\t%08x\n", reg, I915_READ(reg));
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DUMP_RANGE(0x00000, 0x00fff); /* VGA registers */
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DUMP_RANGE(0x02000, 0x02fff); /* instruction, memory, interrupt control registers */
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DUMP_RANGE(0x03000, 0x031ff); /* FENCE and PPGTT control registers */
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DUMP_RANGE(0x03200, 0x03fff); /* frame buffer compression registers */
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DUMP_RANGE(0x05000, 0x05fff); /* I/O control registers */
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DUMP_RANGE(0x06000, 0x06fff); /* clock control registers */
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DUMP_RANGE(0x07000, 0x07fff); /* 3D internal debug registers */
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DUMP_RANGE(0x07400, 0x088ff); /* GPE debug registers */
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DUMP_RANGE(0x0a000, 0x0afff); /* display palette registers */
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DUMP_RANGE(0x10000, 0x13fff); /* MMIO MCHBAR */
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DUMP_RANGE(0x30000, 0x3ffff); /* overlay registers */
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DUMP_RANGE(0x60000, 0x6ffff); /* display engine pipeline registers */
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DUMP_RANGE(0x70000, 0x72fff); /* display and cursor registers */
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DUMP_RANGE(0x73000, 0x73fff); /* performance counters */
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return 0;
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}
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static struct drm_info_list i915_debugfs_list[] = {
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{"i915_regs", i915_registers_info, 0},
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{"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
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{"i915_gem_flushing", i915_gem_object_list_info, 0, (void *) FLUSHING_LIST},
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{"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
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{"i915_gem_request", i915_gem_request_info, 0},
|
|
{"i915_gem_seqno", i915_gem_seqno_info, 0},
|
|
{"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
|
|
{"i915_gem_interrupt", i915_interrupt_info, 0},
|
|
{"i915_gem_hws", i915_hws_info, 0},
|
|
{"i915_ringbuffer_data", i915_ringbuffer_data, 0},
|
|
{"i915_ringbuffer_info", i915_ringbuffer_info, 0},
|
|
{"i915_batchbuffers", i915_batchbuffer_info, 0},
|
|
{"i915_error_state", i915_error_state, 0},
|
|
};
|
|
#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
|
|
|
|
int i915_debugfs_init(struct drm_minor *minor)
|
|
{
|
|
return drm_debugfs_create_files(i915_debugfs_list,
|
|
I915_DEBUGFS_ENTRIES,
|
|
minor->debugfs_root, minor);
|
|
}
|
|
|
|
void i915_debugfs_cleanup(struct drm_minor *minor)
|
|
{
|
|
drm_debugfs_remove_files(i915_debugfs_list,
|
|
I915_DEBUGFS_ENTRIES, minor);
|
|
}
|
|
|
|
#endif /* CONFIG_DEBUG_FS */
|
|
|