![Gong Tao](/assets/img/avatar_default.png)
or1k_pic_mask_ack was failing to actually mask the IRQ. Signed-off-by: Gong Tao <gongtao0607@gmail.com> Signed-off-by: Jonas Bonn <jonas@southpole.se>
187 lines
4.7 KiB
C
187 lines
4.7 KiB
C
/*
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* OpenRISC irq.c
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*
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* Linux architectural port borrowing liberally from similar works of
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* others. All original copyrights apply as per the original source
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* declaration.
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*
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* Modifications for the OpenRISC architecture:
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* Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/interrupt.h>
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#include <linux/init.h>
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#include <linux/of.h>
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#include <linux/ftrace.h>
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#include <linux/irq.h>
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#include <linux/export.h>
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#include <linux/irqdomain.h>
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#include <linux/irqflags.h>
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/* read interrupt enabled status */
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unsigned long arch_local_save_flags(void)
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{
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return mfspr(SPR_SR) & (SPR_SR_IEE|SPR_SR_TEE);
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}
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EXPORT_SYMBOL(arch_local_save_flags);
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/* set interrupt enabled status */
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void arch_local_irq_restore(unsigned long flags)
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{
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mtspr(SPR_SR, ((mfspr(SPR_SR) & ~(SPR_SR_IEE|SPR_SR_TEE)) | flags));
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}
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EXPORT_SYMBOL(arch_local_irq_restore);
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/* OR1K PIC implementation */
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/* We're a couple of cycles faster than the generic implementations with
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* these 'fast' versions.
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*/
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static void or1k_pic_mask(struct irq_data *data)
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{
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mtspr(SPR_PICMR, mfspr(SPR_PICMR) & ~(1UL << data->hwirq));
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}
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static void or1k_pic_unmask(struct irq_data *data)
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{
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mtspr(SPR_PICMR, mfspr(SPR_PICMR) | (1UL << data->hwirq));
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}
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static void or1k_pic_ack(struct irq_data *data)
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{
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/* EDGE-triggered interrupts need to be ack'ed in order to clear
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* the latch.
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* LEVEL-triggered interrupts do not need to be ack'ed; however,
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* ack'ing the interrupt has no ill-effect and is quicker than
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* trying to figure out what type it is...
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*/
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/* The OpenRISC 1000 spec says to write a 1 to the bit to ack the
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* interrupt, but the OR1200 does this backwards and requires a 0
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* to be written...
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*/
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#ifdef CONFIG_OR1K_1200
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/* There are two oddities with the OR1200 PIC implementation:
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* i) LEVEL-triggered interrupts are latched and need to be cleared
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* ii) the interrupt latch is cleared by writing a 0 to the bit,
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* as opposed to a 1 as mandated by the spec
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*/
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mtspr(SPR_PICSR, mfspr(SPR_PICSR) & ~(1UL << data->hwirq));
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#else
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WARN(1, "Interrupt handling possibly broken\n");
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mtspr(SPR_PICSR, (1UL << data->hwirq));
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#endif
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}
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static void or1k_pic_mask_ack(struct irq_data *data)
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{
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/* Comments for pic_ack apply here, too */
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#ifdef CONFIG_OR1K_1200
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mtspr(SPR_PICMR, mfspr(SPR_PICMR) & ~(1UL << data->hwirq));
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mtspr(SPR_PICSR, mfspr(SPR_PICSR) & ~(1UL << data->hwirq));
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#else
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WARN(1, "Interrupt handling possibly broken\n");
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mtspr(SPR_PICMR, (1UL << data->hwirq));
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mtspr(SPR_PICSR, (1UL << data->hwirq));
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#endif
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}
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#if 0
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static int or1k_pic_set_type(struct irq_data *data, unsigned int flow_type)
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{
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/* There's nothing to do in the PIC configuration when changing
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* flow type. Level and edge-triggered interrupts are both
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* supported, but it's PIC-implementation specific which type
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* is handled. */
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return irq_setup_alt_chip(data, flow_type);
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}
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#endif
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static struct irq_chip or1k_dev = {
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.name = "or1k-PIC",
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.irq_unmask = or1k_pic_unmask,
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.irq_mask = or1k_pic_mask,
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.irq_ack = or1k_pic_ack,
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.irq_mask_ack = or1k_pic_mask_ack,
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};
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static struct irq_domain *root_domain;
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static inline int pic_get_irq(int first)
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{
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int hwirq;
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hwirq = ffs(mfspr(SPR_PICSR) >> first);
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if (!hwirq)
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return NO_IRQ;
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else
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hwirq = hwirq + first -1;
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return irq_find_mapping(root_domain, hwirq);
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}
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static int or1k_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
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{
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irq_set_chip_and_handler_name(irq, &or1k_dev,
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handle_level_irq, "level");
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irq_set_status_flags(irq, IRQ_LEVEL | IRQ_NOPROBE);
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return 0;
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}
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static const struct irq_domain_ops or1k_irq_domain_ops = {
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.xlate = irq_domain_xlate_onecell,
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.map = or1k_map,
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};
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/*
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* This sets up the IRQ domain for the PIC built in to the OpenRISC
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* 1000 CPU. This is the "root" domain as these are the interrupts
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* that directly trigger an exception in the CPU.
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*/
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static void __init or1k_irq_init(void)
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{
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struct device_node *intc = NULL;
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/* The interrupt controller device node is mandatory */
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intc = of_find_compatible_node(NULL, NULL, "opencores,or1k-pic");
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BUG_ON(!intc);
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/* Disable all interrupts until explicitly requested */
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mtspr(SPR_PICMR, (0UL));
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root_domain = irq_domain_add_linear(intc, 32,
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&or1k_irq_domain_ops, NULL);
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}
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void __init init_IRQ(void)
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{
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or1k_irq_init();
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}
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void __irq_entry do_IRQ(struct pt_regs *regs)
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{
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int irq = -1;
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struct pt_regs *old_regs = set_irq_regs(regs);
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irq_enter();
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while ((irq = pic_get_irq(irq + 1)) != NO_IRQ)
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generic_handle_irq(irq);
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irq_exit();
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set_irq_regs(old_regs);
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}
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