![Kyle Moffett](/assets/img/avatar_default.png)
There are two separate flags controlling whether or not the MPIC is reset during initialization, which is completely unnecessary, and only one of them can be specified in the device tree. Also, most platforms in-tree right now do actually want to reset the MPIC during initialization anyways, which means lots of duplicate code passing the MPIC_WANTS_RESET flag. Fix all of the callers which currently do not pass the MPIC_WANTS_RESET flag to pass the MPIC_NO_RESET flag, then remove the MPIC_WANTS_RESET flag and make the code reset the MPIC by default. Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
608 lines
14 KiB
C
608 lines
14 KiB
C
/*
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* Copyright (C) 1995 Linus Torvalds
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* Adapted from 'alpha' version by Gary Thomas
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* Modified by Cort Dougan (cort@cs.nmt.edu)
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*/
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/*
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* bootup setup stuff..
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*/
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#include <linux/errno.h>
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#include <linux/sched.h>
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/stddef.h>
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#include <linux/unistd.h>
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#include <linux/ptrace.h>
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#include <linux/user.h>
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#include <linux/tty.h>
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#include <linux/major.h>
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#include <linux/interrupt.h>
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#include <linux/reboot.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <generated/utsrelease.h>
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#include <linux/adb.h>
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#include <linux/module.h>
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#include <linux/delay.h>
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#include <linux/console.h>
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#include <linux/seq_file.h>
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#include <linux/root_dev.h>
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#include <linux/initrd.h>
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#include <linux/timer.h>
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#include <asm/io.h>
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#include <asm/pgtable.h>
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#include <asm/prom.h>
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#include <asm/pci-bridge.h>
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#include <asm/dma.h>
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#include <asm/machdep.h>
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#include <asm/irq.h>
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#include <asm/hydra.h>
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#include <asm/sections.h>
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#include <asm/time.h>
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#include <asm/i8259.h>
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#include <asm/mpic.h>
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#include <asm/rtas.h>
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#include <asm/xmon.h>
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#include "chrp.h"
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#include "gg2.h"
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void rtas_indicator_progress(char *, unsigned short);
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int _chrp_type;
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EXPORT_SYMBOL(_chrp_type);
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static struct mpic *chrp_mpic;
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/* Used for doing CHRP event-scans */
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DEFINE_PER_CPU(struct timer_list, heartbeat_timer);
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unsigned long event_scan_interval;
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extern unsigned long loops_per_jiffy;
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/* To be replaced by RTAS when available */
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static unsigned int __iomem *briq_SPOR;
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#ifdef CONFIG_SMP
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extern struct smp_ops_t chrp_smp_ops;
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#endif
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static const char *gg2_memtypes[4] = {
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"FPM", "SDRAM", "EDO", "BEDO"
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};
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static const char *gg2_cachesizes[4] = {
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"256 KB", "512 KB", "1 MB", "Reserved"
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};
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static const char *gg2_cachetypes[4] = {
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"Asynchronous", "Reserved", "Flow-Through Synchronous",
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"Pipelined Synchronous"
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};
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static const char *gg2_cachemodes[4] = {
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"Disabled", "Write-Through", "Copy-Back", "Transparent Mode"
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};
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static const char *chrp_names[] = {
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"Unknown",
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"","","",
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"Motorola",
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"IBM or Longtrail",
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"Genesi Pegasos",
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"Total Impact Briq"
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};
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void chrp_show_cpuinfo(struct seq_file *m)
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{
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int i, sdramen;
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unsigned int t;
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struct device_node *root;
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const char *model = "";
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root = of_find_node_by_path("/");
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if (root)
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model = of_get_property(root, "model", NULL);
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seq_printf(m, "machine\t\t: CHRP %s\n", model);
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/* longtrail (goldengate) stuff */
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if (model && !strncmp(model, "IBM,LongTrail", 13)) {
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/* VLSI VAS96011/12 `Golden Gate 2' */
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/* Memory banks */
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sdramen = (in_le32(gg2_pci_config_base + GG2_PCI_DRAM_CTRL)
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>>31) & 1;
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for (i = 0; i < (sdramen ? 4 : 6); i++) {
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t = in_le32(gg2_pci_config_base+
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GG2_PCI_DRAM_BANK0+
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i*4);
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if (!(t & 1))
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continue;
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switch ((t>>8) & 0x1f) {
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case 0x1f:
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model = "4 MB";
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break;
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case 0x1e:
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model = "8 MB";
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break;
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case 0x1c:
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model = "16 MB";
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break;
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case 0x18:
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model = "32 MB";
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break;
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case 0x10:
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model = "64 MB";
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break;
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case 0x00:
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model = "128 MB";
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break;
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default:
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model = "Reserved";
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break;
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}
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seq_printf(m, "memory bank %d\t: %s %s\n", i, model,
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gg2_memtypes[sdramen ? 1 : ((t>>1) & 3)]);
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}
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/* L2 cache */
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t = in_le32(gg2_pci_config_base+GG2_PCI_CC_CTRL);
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seq_printf(m, "board l2\t: %s %s (%s)\n",
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gg2_cachesizes[(t>>7) & 3],
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gg2_cachetypes[(t>>2) & 3],
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gg2_cachemodes[t & 3]);
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}
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of_node_put(root);
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}
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/*
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* Fixes for the National Semiconductor PC78308VUL SuperI/O
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*
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* Some versions of Open Firmware incorrectly initialize the IRQ settings
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* for keyboard and mouse
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*/
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static inline void __init sio_write(u8 val, u8 index)
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{
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outb(index, 0x15c);
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outb(val, 0x15d);
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}
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static inline u8 __init sio_read(u8 index)
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{
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outb(index, 0x15c);
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return inb(0x15d);
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}
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static void __init sio_fixup_irq(const char *name, u8 device, u8 level,
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u8 type)
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{
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u8 level0, type0, active;
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/* select logical device */
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sio_write(device, 0x07);
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active = sio_read(0x30);
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level0 = sio_read(0x70);
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type0 = sio_read(0x71);
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if (level0 != level || type0 != type || !active) {
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printk(KERN_WARNING "sio: %s irq level %d, type %d, %sactive: "
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"remapping to level %d, type %d, active\n",
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name, level0, type0, !active ? "in" : "", level, type);
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sio_write(0x01, 0x30);
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sio_write(level, 0x70);
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sio_write(type, 0x71);
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}
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}
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static void __init sio_init(void)
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{
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struct device_node *root;
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const char *model;
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root = of_find_node_by_path("/");
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if (!root)
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return;
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model = of_get_property(root, "model", NULL);
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if (model && !strncmp(model, "IBM,LongTrail", 13)) {
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/* logical device 0 (KBC/Keyboard) */
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sio_fixup_irq("keyboard", 0, 1, 2);
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/* select logical device 1 (KBC/Mouse) */
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sio_fixup_irq("mouse", 1, 12, 2);
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}
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of_node_put(root);
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}
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static void __init pegasos_set_l2cr(void)
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{
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struct device_node *np;
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/* On Pegasos, enable the l2 cache if needed, as the OF forgets it */
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if (_chrp_type != _CHRP_Pegasos)
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return;
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/* Enable L2 cache if needed */
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np = of_find_node_by_type(NULL, "cpu");
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if (np != NULL) {
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const unsigned int *l2cr = of_get_property(np, "l2cr", NULL);
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if (l2cr == NULL) {
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printk ("Pegasos l2cr : no cpu l2cr property found\n");
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goto out;
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}
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if (!((*l2cr) & 0x80000000)) {
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printk ("Pegasos l2cr : L2 cache was not active, "
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"activating\n");
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_set_L2CR(0);
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_set_L2CR((*l2cr) | 0x80000000);
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}
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}
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out:
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of_node_put(np);
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}
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static void briq_restart(char *cmd)
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{
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local_irq_disable();
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if (briq_SPOR)
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out_be32(briq_SPOR, 0);
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for(;;);
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}
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/*
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* Per default, input/output-device points to the keyboard/screen
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* If no card is installed, the built-in serial port is used as a fallback.
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* But unfortunately, the firmware does not connect /chosen/{stdin,stdout}
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* the the built-in serial node. Instead, a /failsafe node is created.
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*/
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static void chrp_init_early(void)
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{
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struct device_node *node;
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const char *property;
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if (strstr(cmd_line, "console="))
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return;
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/* find the boot console from /chosen/stdout */
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if (!of_chosen)
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return;
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node = of_find_node_by_path("/");
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if (!node)
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return;
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property = of_get_property(node, "model", NULL);
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if (!property)
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goto out_put;
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if (strcmp(property, "Pegasos2"))
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goto out_put;
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/* this is a Pegasos2 */
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property = of_get_property(of_chosen, "linux,stdout-path", NULL);
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if (!property)
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goto out_put;
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of_node_put(node);
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node = of_find_node_by_path(property);
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if (!node)
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return;
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property = of_get_property(node, "device_type", NULL);
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if (!property)
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goto out_put;
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if (strcmp(property, "serial"))
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goto out_put;
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/*
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* The 9pin connector is either /failsafe
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* or /pci@80000000/isa@C/serial@i2F8
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* The optional graphics card has also type 'serial' in VGA mode.
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*/
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property = of_get_property(node, "name", NULL);
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if (!property)
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goto out_put;
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if (!strcmp(property, "failsafe") || !strcmp(property, "serial"))
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add_preferred_console("ttyS", 0, NULL);
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out_put:
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of_node_put(node);
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}
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void __init chrp_setup_arch(void)
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{
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struct device_node *root = of_find_node_by_path("/");
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const char *machine = NULL;
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/* init to some ~sane value until calibrate_delay() runs */
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loops_per_jiffy = 50000000/HZ;
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if (root)
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machine = of_get_property(root, "model", NULL);
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if (machine && strncmp(machine, "Pegasos", 7) == 0) {
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_chrp_type = _CHRP_Pegasos;
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} else if (machine && strncmp(machine, "IBM", 3) == 0) {
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_chrp_type = _CHRP_IBM;
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} else if (machine && strncmp(machine, "MOT", 3) == 0) {
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_chrp_type = _CHRP_Motorola;
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} else if (machine && strncmp(machine, "TotalImpact,BRIQ-1", 18) == 0) {
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_chrp_type = _CHRP_briq;
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/* Map the SPOR register on briq and change the restart hook */
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briq_SPOR = ioremap(0xff0000e8, 4);
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ppc_md.restart = briq_restart;
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} else {
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/* Let's assume it is an IBM chrp if all else fails */
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_chrp_type = _CHRP_IBM;
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}
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of_node_put(root);
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printk("chrp type = %x [%s]\n", _chrp_type, chrp_names[_chrp_type]);
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rtas_initialize();
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if (rtas_token("display-character") >= 0)
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ppc_md.progress = rtas_progress;
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/* use RTAS time-of-day routines if available */
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if (rtas_token("get-time-of-day") != RTAS_UNKNOWN_SERVICE) {
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ppc_md.get_boot_time = rtas_get_boot_time;
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ppc_md.get_rtc_time = rtas_get_rtc_time;
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ppc_md.set_rtc_time = rtas_set_rtc_time;
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}
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/* On pegasos, enable the L2 cache if not already done by OF */
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pegasos_set_l2cr();
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/* Lookup PCI host bridges */
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chrp_find_bridges();
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/*
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* Temporary fixes for PCI devices.
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* -- Geert
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*/
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hydra_init(); /* Mac I/O */
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/*
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* Fix the Super I/O configuration
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*/
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sio_init();
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pci_create_OF_bus_map();
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/*
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* Print the banner, then scroll down so boot progress
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* can be printed. -- Cort
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*/
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if (ppc_md.progress) ppc_md.progress("Linux/PPC "UTS_RELEASE"\n", 0x0);
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}
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static void chrp_8259_cascade(unsigned int irq, struct irq_desc *desc)
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{
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struct irq_chip *chip = irq_desc_get_chip(desc);
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unsigned int cascade_irq = i8259_irq();
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if (cascade_irq != NO_IRQ)
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generic_handle_irq(cascade_irq);
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chip->irq_eoi(&desc->irq_data);
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}
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/*
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* Finds the open-pic node and sets up the mpic driver.
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*/
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static void __init chrp_find_openpic(void)
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{
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struct device_node *np, *root;
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int len, i, j;
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int isu_size, idu_size;
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const unsigned int *iranges, *opprop = NULL;
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int oplen = 0;
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unsigned long opaddr;
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int na = 1;
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np = of_find_node_by_type(NULL, "open-pic");
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if (np == NULL)
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return;
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root = of_find_node_by_path("/");
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if (root) {
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opprop = of_get_property(root, "platform-open-pic", &oplen);
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na = of_n_addr_cells(root);
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}
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if (opprop && oplen >= na * sizeof(unsigned int)) {
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opaddr = opprop[na-1]; /* assume 32-bit */
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oplen /= na * sizeof(unsigned int);
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} else {
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struct resource r;
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if (of_address_to_resource(np, 0, &r)) {
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goto bail;
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}
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opaddr = r.start;
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oplen = 0;
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}
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printk(KERN_INFO "OpenPIC at %lx\n", opaddr);
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iranges = of_get_property(np, "interrupt-ranges", &len);
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if (iranges == NULL)
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len = 0; /* non-distributed mpic */
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else
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len /= 2 * sizeof(unsigned int);
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/*
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* The first pair of cells in interrupt-ranges refers to the
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* IDU; subsequent pairs refer to the ISUs.
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*/
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if (oplen < len) {
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printk(KERN_ERR "Insufficient addresses for distributed"
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" OpenPIC (%d < %d)\n", oplen, len);
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len = oplen;
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}
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isu_size = 0;
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idu_size = 0;
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if (len > 0 && iranges[1] != 0) {
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printk(KERN_INFO "OpenPIC irqs %d..%d in IDU\n",
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iranges[0], iranges[0] + iranges[1] - 1);
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idu_size = iranges[1];
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}
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if (len > 1)
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isu_size = iranges[3];
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chrp_mpic = mpic_alloc(np, opaddr, MPIC_NO_RESET,
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isu_size, 0, " MPIC ");
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if (chrp_mpic == NULL) {
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printk(KERN_ERR "Failed to allocate MPIC structure\n");
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goto bail;
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}
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j = na - 1;
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for (i = 1; i < len; ++i) {
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iranges += 2;
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j += na;
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printk(KERN_INFO "OpenPIC irqs %d..%d in ISU at %x\n",
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iranges[0], iranges[0] + iranges[1] - 1,
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opprop[j]);
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mpic_assign_isu(chrp_mpic, i - 1, opprop[j]);
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}
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mpic_init(chrp_mpic);
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ppc_md.get_irq = mpic_get_irq;
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bail:
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of_node_put(root);
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of_node_put(np);
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}
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#if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(CONFIG_XMON)
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static struct irqaction xmon_irqaction = {
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.handler = xmon_irq,
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.name = "XMON break",
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};
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#endif
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static void __init chrp_find_8259(void)
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{
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struct device_node *np, *pic = NULL;
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unsigned long chrp_int_ack = 0;
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unsigned int cascade_irq;
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/* Look for cascade */
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for_each_node_by_type(np, "interrupt-controller")
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if (of_device_is_compatible(np, "chrp,iic")) {
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pic = np;
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break;
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}
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/* Ok, 8259 wasn't found. We need to handle the case where
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* we have a pegasos that claims to be chrp but doesn't have
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* a proper interrupt tree
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*/
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if (pic == NULL && chrp_mpic != NULL) {
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printk(KERN_ERR "i8259: Not found in device-tree"
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" assuming no legacy interrupts\n");
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return;
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}
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/* Look for intack. In a perfect world, we would look for it on
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* the ISA bus that holds the 8259 but heh... Works that way. If
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* we ever see a problem, we can try to re-use the pSeries code here.
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* Also, Pegasos-type platforms don't have a proper node to start
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* from anyway
|
|
*/
|
|
for_each_node_by_name(np, "pci") {
|
|
const unsigned int *addrp = of_get_property(np,
|
|
"8259-interrupt-acknowledge", NULL);
|
|
|
|
if (addrp == NULL)
|
|
continue;
|
|
chrp_int_ack = addrp[of_n_addr_cells(np)-1];
|
|
break;
|
|
}
|
|
of_node_put(np);
|
|
if (np == NULL)
|
|
printk(KERN_WARNING "Cannot find PCI interrupt acknowledge"
|
|
" address, polling\n");
|
|
|
|
i8259_init(pic, chrp_int_ack);
|
|
if (ppc_md.get_irq == NULL) {
|
|
ppc_md.get_irq = i8259_irq;
|
|
irq_set_default_host(i8259_get_host());
|
|
}
|
|
if (chrp_mpic != NULL) {
|
|
cascade_irq = irq_of_parse_and_map(pic, 0);
|
|
if (cascade_irq == NO_IRQ)
|
|
printk(KERN_ERR "i8259: failed to map cascade irq\n");
|
|
else
|
|
irq_set_chained_handler(cascade_irq,
|
|
chrp_8259_cascade);
|
|
}
|
|
}
|
|
|
|
void __init chrp_init_IRQ(void)
|
|
{
|
|
#if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(CONFIG_XMON)
|
|
struct device_node *kbd;
|
|
#endif
|
|
chrp_find_openpic();
|
|
chrp_find_8259();
|
|
|
|
#ifdef CONFIG_SMP
|
|
/* Pegasos has no MPIC, those ops would make it crash. It might be an
|
|
* option to move setting them to after we probe the PIC though
|
|
*/
|
|
if (chrp_mpic != NULL)
|
|
smp_ops = &chrp_smp_ops;
|
|
#endif /* CONFIG_SMP */
|
|
|
|
if (_chrp_type == _CHRP_Pegasos)
|
|
ppc_md.get_irq = i8259_irq;
|
|
|
|
#if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(CONFIG_XMON)
|
|
/* see if there is a keyboard in the device tree
|
|
with a parent of type "adb" */
|
|
for_each_node_by_name(kbd, "keyboard")
|
|
if (kbd->parent && kbd->parent->type
|
|
&& strcmp(kbd->parent->type, "adb") == 0)
|
|
break;
|
|
of_node_put(kbd);
|
|
if (kbd)
|
|
setup_irq(HYDRA_INT_ADB_NMI, &xmon_irqaction);
|
|
#endif
|
|
}
|
|
|
|
void __init
|
|
chrp_init2(void)
|
|
{
|
|
#ifdef CONFIG_NVRAM
|
|
chrp_nvram_init();
|
|
#endif
|
|
|
|
request_region(0x20,0x20,"pic1");
|
|
request_region(0xa0,0x20,"pic2");
|
|
request_region(0x00,0x20,"dma1");
|
|
request_region(0x40,0x20,"timer");
|
|
request_region(0x80,0x10,"dma page reg");
|
|
request_region(0xc0,0x20,"dma2");
|
|
|
|
if (ppc_md.progress)
|
|
ppc_md.progress(" Have fun! ", 0x7777);
|
|
}
|
|
|
|
static int __init chrp_probe(void)
|
|
{
|
|
char *dtype = of_get_flat_dt_prop(of_get_flat_dt_root(),
|
|
"device_type", NULL);
|
|
if (dtype == NULL)
|
|
return 0;
|
|
if (strcmp(dtype, "chrp"))
|
|
return 0;
|
|
|
|
ISA_DMA_THRESHOLD = ~0L;
|
|
DMA_MODE_READ = 0x44;
|
|
DMA_MODE_WRITE = 0x48;
|
|
|
|
return 1;
|
|
}
|
|
|
|
define_machine(chrp) {
|
|
.name = "CHRP",
|
|
.probe = chrp_probe,
|
|
.setup_arch = chrp_setup_arch,
|
|
.init = chrp_init2,
|
|
.init_early = chrp_init_early,
|
|
.show_cpuinfo = chrp_show_cpuinfo,
|
|
.init_IRQ = chrp_init_IRQ,
|
|
.restart = rtas_restart,
|
|
.power_off = rtas_power_off,
|
|
.halt = rtas_halt,
|
|
.time_init = chrp_time_init,
|
|
.set_rtc_time = chrp_set_rtc_time,
|
|
.get_rtc_time = chrp_get_rtc_time,
|
|
.calibrate_decr = generic_calibrate_decr,
|
|
.phys_mem_access_prot = pci_phys_mem_access_prot,
|
|
};
|