35033d8cb7
This commit adds support for MOTU 8pre FireWire, which was shipped 2007
and nowadays already discontinued. Userspace applications can transmit
and receive PCM frames and MIDI messages for this model via ALSA PCM
interface and RawMidi/Sequencer interfaces.
Like the other models of MOTU FireWire series, this model has many
quirks in its CIP.
At first, data channels for two pairs of optical interfaces. At lower
sampling transmission frequency, i.e. 44.1 and 48.0 kHz, one pair is
available for ADAT data, thus 8 data chunks are transferred by CIP.
At middle sampling transmission frequency, i.e. 88.2 and 96.0 kHz,
two pairs are available to keep 8 chunks for ADAT data, thus CIP
still includes 8 data chunks.
Apart from data chunks for optical interface, CIP includes fixed number
of data chunks. In tx stream, two chunks for status message, eight
chunks for samples from analog 1-8 input, two chunks for mix-return.
In rx stream, two chunks for control message, two chunks for main 1-2
output, two chunks for phone 1-2 output, two chunks for dummy 1-2.
CIP header in tx stream includes quirks for its dbs and dbc fields.
The value of dbs field is fixed to 0x13, against its actual size.
The value of dbc field is firstly updated to 0x07 from zero, then
it's incremented continuously according to actual number of data h
blocks.
Finally, the model has own bits to disable frame fetch.
This commit uses several options to absorb the above quirks.
$ python2 crpp < /sys/bus/firewire/devices/fw1/config_rom
ROM header and bus information block
-----------------------------------------------------------------
400 0410b57d bus_info_length 4, crc_length 16, crc 46461
404 31333934 bus_name "1394"
408 20001000 irmc 0, cmc 0, isc 1, bmc 0, cyc_clk_acc 0, max_rec 1 (4)
40c 0001f200 company_id 0001f2 |
410 00083dfb device_id 0000083dfb | EUI-64 0001f20000083dfb
root directory
-----------------------------------------------------------------
414 0004c65c directory_length 4, crc 50780
418 030001f2 vendor
41c 0c0083c0 node capabilities per IEEE 1394
420 8d000006 --> eui-64 leaf at 438
424 d1000001 --> unit directory at 428
unit directory at 428
-----------------------------------------------------------------
428 0003991c directory_length 3, crc 39196
42c 120001f2 specifier id
430 1300000f version
434 17103800 model
eui-64 leaf at 438
-----------------------------------------------------------------
438 00022681 leaf_length 2, crc 9857
43c 0001f200 company_id 0001f2 |
440 00083dfb device_id 0000083dfb | EUI-64 0001f20000083dfb
Signed-off-by: Takashi Sakamoto <o-takashi@sakamocchi.jp>
Signed-off-by: Takashi Iwai <tiwai@suse.de>
288 lines
7.2 KiB
C
288 lines
7.2 KiB
C
/*
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* motu-protocol-v2.c - a part of driver for MOTU FireWire series
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*
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* Copyright (c) 2015-2017 Takashi Sakamoto <o-takashi@sakamocchi.jp>
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*
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* Licensed under the terms of the GNU General Public License, version 2.
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*/
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#include "motu.h"
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#define V2_CLOCK_STATUS_OFFSET 0x0b14
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#define V2_CLOCK_RATE_MASK 0x00000038
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#define V2_CLOCK_RATE_SHIFT 3
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#define V2_CLOCK_SRC_MASK 0x00000007
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#define V2_CLOCK_SRC_SHIFT 0
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#define V2_CLOCK_TRAVELER_FETCH_DISABLE 0x04000000
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#define V2_CLOCK_TRAVELER_FETCH_ENABLE 0x03000000
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#define V2_CLOCK_8PRE_FETCH_DISABLE 0x02000000
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#define V2_CLOCK_8PRE_FETCH_ENABLE 0x00000000
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#define V2_IN_OUT_CONF_OFFSET 0x0c04
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#define V2_OPT_OUT_IFACE_MASK 0x00000c00
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#define V2_OPT_OUT_IFACE_SHIFT 10
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#define V2_OPT_IN_IFACE_MASK 0x00000300
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#define V2_OPT_IN_IFACE_SHIFT 8
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#define V2_OPT_IFACE_MODE_NONE 0
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#define V2_OPT_IFACE_MODE_ADAT 1
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#define V2_OPT_IFACE_MODE_SPDIF 2
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static int v2_get_clock_rate(struct snd_motu *motu, unsigned int *rate)
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{
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__be32 reg;
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unsigned int index;
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int err;
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err = snd_motu_transaction_read(motu, V2_CLOCK_STATUS_OFFSET, ®,
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sizeof(reg));
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if (err < 0)
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return err;
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index = (be32_to_cpu(reg) & V2_CLOCK_RATE_MASK) >> V2_CLOCK_RATE_SHIFT;
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if (index >= ARRAY_SIZE(snd_motu_clock_rates))
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return -EIO;
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*rate = snd_motu_clock_rates[index];
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return 0;
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}
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static int v2_set_clock_rate(struct snd_motu *motu, unsigned int rate)
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{
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__be32 reg;
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u32 data;
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int i;
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int err;
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for (i = 0; i < ARRAY_SIZE(snd_motu_clock_rates); ++i) {
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if (snd_motu_clock_rates[i] == rate)
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break;
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}
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if (i == ARRAY_SIZE(snd_motu_clock_rates))
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return -EINVAL;
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err = snd_motu_transaction_read(motu, V2_CLOCK_STATUS_OFFSET, ®,
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sizeof(reg));
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if (err < 0)
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return err;
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data = be32_to_cpu(reg);
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data &= ~V2_CLOCK_RATE_MASK;
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data |= i << V2_CLOCK_RATE_SHIFT;
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if (motu->spec == &snd_motu_spec_traveler) {
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data &= ~V2_CLOCK_TRAVELER_FETCH_ENABLE;
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data |= V2_CLOCK_TRAVELER_FETCH_DISABLE;
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}
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reg = cpu_to_be32(data);
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return snd_motu_transaction_write(motu, V2_CLOCK_STATUS_OFFSET, ®,
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sizeof(reg));
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}
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static int v2_get_clock_source(struct snd_motu *motu,
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enum snd_motu_clock_source *src)
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{
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__be32 reg;
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unsigned int index;
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int err;
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err = snd_motu_transaction_read(motu, V2_CLOCK_STATUS_OFFSET, ®,
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sizeof(reg));
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if (err < 0)
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return err;
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index = be32_to_cpu(reg) & V2_CLOCK_SRC_MASK;
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if (index > 5)
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return -EIO;
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/* To check the configuration of optical interface. */
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err = snd_motu_transaction_read(motu, V2_IN_OUT_CONF_OFFSET, ®,
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sizeof(reg));
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if (err < 0)
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return err;
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switch (index) {
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case 0:
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*src = SND_MOTU_CLOCK_SOURCE_INTERNAL;
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break;
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case 1:
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if (be32_to_cpu(reg) & 0x00000200)
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*src = SND_MOTU_CLOCK_SOURCE_SPDIF_ON_OPT;
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else
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*src = SND_MOTU_CLOCK_SOURCE_ADAT_ON_OPT;
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break;
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case 2:
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*src = SND_MOTU_CLOCK_SOURCE_SPDIF_ON_COAX;
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break;
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case 4:
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*src = SND_MOTU_CLOCK_SOURCE_WORD_ON_BNC;
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break;
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case 5:
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*src = SND_MOTU_CLOCK_SOURCE_ADAT_ON_DSUB;
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break;
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default:
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return -EIO;
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}
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return 0;
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}
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static int v2_switch_fetching_mode(struct snd_motu *motu, bool enable)
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{
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__be32 reg;
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u32 data;
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int err = 0;
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if (motu->spec == &snd_motu_spec_traveler ||
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motu->spec == &snd_motu_spec_8pre) {
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err = snd_motu_transaction_read(motu, V2_CLOCK_STATUS_OFFSET,
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®, sizeof(reg));
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if (err < 0)
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return err;
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data = be32_to_cpu(reg);
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if (motu->spec == &snd_motu_spec_traveler) {
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data &= ~(V2_CLOCK_TRAVELER_FETCH_DISABLE |
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V2_CLOCK_TRAVELER_FETCH_ENABLE);
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if (enable)
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data |= V2_CLOCK_TRAVELER_FETCH_ENABLE;
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else
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data |= V2_CLOCK_TRAVELER_FETCH_DISABLE;
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} else if (motu->spec == &snd_motu_spec_8pre) {
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data &= ~(V2_CLOCK_8PRE_FETCH_DISABLE |
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V2_CLOCK_8PRE_FETCH_ENABLE);
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if (enable)
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data |= V2_CLOCK_8PRE_FETCH_DISABLE;
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else
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data |= V2_CLOCK_8PRE_FETCH_ENABLE;
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}
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reg = cpu_to_be32(data);
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err = snd_motu_transaction_write(motu, V2_CLOCK_STATUS_OFFSET,
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®, sizeof(reg));
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}
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return err;
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}
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static void calculate_fixed_part(struct snd_motu_packet_format *formats,
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enum amdtp_stream_direction dir,
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enum snd_motu_spec_flags flags,
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unsigned char analog_ports)
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{
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unsigned char pcm_chunks[3] = {0, 0, 0};
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formats->msg_chunks = 2;
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pcm_chunks[0] = analog_ports;
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pcm_chunks[1] = analog_ports;
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if (flags & SND_MOTU_SPEC_SUPPORT_CLOCK_X4)
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pcm_chunks[2] = analog_ports;
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if (dir == AMDTP_IN_STREAM) {
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if (flags & SND_MOTU_SPEC_TX_MICINST_CHUNK) {
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pcm_chunks[0] += 2;
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pcm_chunks[1] += 2;
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}
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if (flags & SND_MOTU_SPEC_TX_RETURN_CHUNK) {
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pcm_chunks[0] += 2;
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pcm_chunks[1] += 2;
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}
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} else {
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if (flags & SND_MOTU_SPEC_RX_SEPARETED_MAIN) {
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pcm_chunks[0] += 2;
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pcm_chunks[1] += 2;
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}
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// Packets to v2 units include 2 chunks for phone 1/2, except
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// for 176.4/192.0 kHz.
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pcm_chunks[0] += 2;
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pcm_chunks[1] += 2;
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}
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if (flags & SND_MOTU_SPEC_HAS_AESEBU_IFACE) {
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pcm_chunks[0] += 2;
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pcm_chunks[1] += 2;
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}
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/*
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* All of v2 models have a pair of coaxial interfaces for digital in/out
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* port. At 44.1/48.0/88.2/96.0 kHz, packets includes PCM from these
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* ports.
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*/
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pcm_chunks[0] += 2;
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pcm_chunks[1] += 2;
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formats->fixed_part_pcm_chunks[0] = pcm_chunks[0];
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formats->fixed_part_pcm_chunks[1] = pcm_chunks[1];
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formats->fixed_part_pcm_chunks[2] = pcm_chunks[2];
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}
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static void calculate_differed_part(struct snd_motu_packet_format *formats,
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enum snd_motu_spec_flags flags,
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u32 data, u32 mask, u32 shift)
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{
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unsigned char pcm_chunks[2] = {0, 0};
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/*
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* When optical interfaces are configured for S/PDIF (TOSLINK),
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* the above PCM frames come from them, instead of coaxial
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* interfaces.
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*/
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data = (data & mask) >> shift;
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if (data == V2_OPT_IFACE_MODE_ADAT) {
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if (flags & SND_MOTU_SPEC_HAS_OPT_IFACE_A) {
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pcm_chunks[0] += 8;
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pcm_chunks[1] += 4;
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}
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// 8pre has two sets of optical interface and doesn't reduce
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// chunks for ADAT signals.
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if (flags & SND_MOTU_SPEC_HAS_OPT_IFACE_B) {
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pcm_chunks[1] += 4;
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}
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}
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/* At mode x4, no data chunks are supported in this part. */
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formats->differed_part_pcm_chunks[0] = pcm_chunks[0];
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formats->differed_part_pcm_chunks[1] = pcm_chunks[1];
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}
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static int v2_cache_packet_formats(struct snd_motu *motu)
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{
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__be32 reg;
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u32 data;
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int err;
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err = snd_motu_transaction_read(motu, V2_IN_OUT_CONF_OFFSET, ®,
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sizeof(reg));
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if (err < 0)
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return err;
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data = be32_to_cpu(reg);
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calculate_fixed_part(&motu->tx_packet_formats, AMDTP_IN_STREAM,
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motu->spec->flags, motu->spec->analog_in_ports);
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calculate_differed_part(&motu->tx_packet_formats, motu->spec->flags,
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data, V2_OPT_IN_IFACE_MASK, V2_OPT_IN_IFACE_SHIFT);
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calculate_fixed_part(&motu->rx_packet_formats, AMDTP_OUT_STREAM,
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motu->spec->flags, motu->spec->analog_out_ports);
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calculate_differed_part(&motu->rx_packet_formats, motu->spec->flags,
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data, V2_OPT_OUT_IFACE_MASK, V2_OPT_OUT_IFACE_SHIFT);
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motu->tx_packet_formats.pcm_byte_offset = 10;
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motu->rx_packet_formats.pcm_byte_offset = 10;
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return 0;
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}
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const struct snd_motu_protocol snd_motu_protocol_v2 = {
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.get_clock_rate = v2_get_clock_rate,
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.set_clock_rate = v2_set_clock_rate,
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.get_clock_source = v2_get_clock_source,
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.switch_fetching_mode = v2_switch_fetching_mode,
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.cache_packet_formats = v2_cache_packet_formats,
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};
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