6efa20e49b
This is based on a patch that Zhenzhong Duan had sent - which
was missing some of the remaining pieces. The kernel has the
logic to handle Xen-type-exceptions using the paravirt interface
in the assembler code (see PARAVIRT_ADJUST_EXCEPTION_FRAME -
pv_irq_ops.adjust_exception_frame and and INTERRUPT_RETURN -
pv_cpu_ops.iret).
That means the nmi handler (and other exception handlers) use
the hypervisor iret.
The other changes that would be neccessary for this would
be to translate the NMI_VECTOR to one of the entries on the
ipi_vector and make xen_send_IPI_mask_allbutself use different
events.
Fortunately for us commit 1db01b4903
(xen: Clean up apic ipi interface) implemented this and we piggyback
on the cleanup such that the apic IPI interface will pass the right
vector value for NMI.
With this patch we can trigger NMIs within a PV guest (only tested
x86_64).
For this to work with normal PV guests (not initial domain)
we need the domain to be able to use the APIC ops - they are
already implemented to use the Xen event channels. For that
to be turned on in a PV domU we need to remove the masking
of X86_FEATURE_APIC.
Incidentally that means kgdb will also now work within
a PV guest without using the 'nokgdbroundup' workaround.
Note that the 32-bit version is different and this patch
does not enable that.
CC: Lisa Nguyen <lisa@xenapiadmin.com>
CC: Ben Guthro <benjamin.guthro@citrix.com>
CC: Zhenzhong Duan <zhenzhong.duan@oracle.com>
Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
[v1: Fixed up per David Vrabel comments]
Reviewed-by: Ben Guthro <benjamin.guthro@citrix.com>
Reviewed-by: David Vrabel <david.vrabel@citrix.com>
24 lines
501 B
C
24 lines
501 B
C
#ifndef _ASM_X86_XEN_EVENTS_H
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#define _ASM_X86_XEN_EVENTS_H
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enum ipi_vector {
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XEN_RESCHEDULE_VECTOR,
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XEN_CALL_FUNCTION_VECTOR,
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XEN_CALL_FUNCTION_SINGLE_VECTOR,
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XEN_SPIN_UNLOCK_VECTOR,
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XEN_IRQ_WORK_VECTOR,
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XEN_NMI_VECTOR,
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XEN_NR_IPIS,
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};
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static inline int xen_irqs_disabled(struct pt_regs *regs)
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{
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return raw_irqs_disabled_flags(regs->flags);
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}
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/* No need for a barrier -- XCHG is a barrier on x86. */
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#define xchg_xen_ulong(ptr, val) xchg((ptr), (val))
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#endif /* _ASM_X86_XEN_EVENTS_H */
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