a9ee6bd44c
The sysfs and debugfs entries for pin control drivers work better when the individual pins are given real names, even if they are all just "gpio0", "gpio1", etc. Signed-off-by: Timur Tabi <timur@codeaurora.org> Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
141 lines
4.1 KiB
C
141 lines
4.1 KiB
C
/*
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* Copyright (c) 2015, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* GPIO and pin control functions on this SOC are handled by the "TLMM"
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* device. The driver which controls this device is pinctrl-msm.c. Each
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* SOC with a TLMM is expected to create a client driver that registers
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* with pinctrl-msm.c. This means that all TLMM drivers are pin control
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* drivers.
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*
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* This pin control driver is intended to be used only an ACPI-enabled
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* system. As such, UEFI will handle all pin control configuration, so
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* this driver does not provide pin control functions. It is effectively
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* a GPIO-only driver. The alternative is to duplicate the GPIO code of
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* pinctrl-msm.c into another driver.
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*/
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/pinctrl/pinctrl.h>
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#include <linux/acpi.h>
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#include "pinctrl-msm.h"
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static struct msm_pinctrl_soc_data qdf2xxx_pinctrl;
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/* A reasonable limit to the number of GPIOS */
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#define MAX_GPIOS 256
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/* maximum size of each gpio name (enough room for "gpioXXX" + null) */
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#define NAME_SIZE 8
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static int qdf2xxx_pinctrl_probe(struct platform_device *pdev)
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{
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struct pinctrl_pin_desc *pins;
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struct msm_pingroup *groups;
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char (*names)[NAME_SIZE];
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unsigned int i;
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u32 num_gpios;
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int ret;
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/* Query the number of GPIOs from ACPI */
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ret = device_property_read_u32(&pdev->dev, "num-gpios", &num_gpios);
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if (ret < 0) {
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dev_warn(&pdev->dev, "missing num-gpios property\n");
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return ret;
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}
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if (!num_gpios || num_gpios > MAX_GPIOS) {
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dev_warn(&pdev->dev, "invalid num-gpios property\n");
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return -ENODEV;
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}
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pins = devm_kcalloc(&pdev->dev, num_gpios,
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sizeof(struct pinctrl_pin_desc), GFP_KERNEL);
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groups = devm_kcalloc(&pdev->dev, num_gpios,
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sizeof(struct msm_pingroup), GFP_KERNEL);
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names = devm_kcalloc(&pdev->dev, num_gpios, NAME_SIZE, GFP_KERNEL);
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if (!pins || !groups || !names)
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return -ENOMEM;
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for (i = 0; i < num_gpios; i++) {
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snprintf(names[i], NAME_SIZE, "gpio%u", i);
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pins[i].number = i;
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pins[i].name = names[i];
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groups[i].npins = 1;
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groups[i].name = names[i];
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groups[i].pins = &pins[i].number;
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groups[i].ctl_reg = 0x10000 * i;
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groups[i].io_reg = 0x04 + 0x10000 * i;
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groups[i].intr_cfg_reg = 0x08 + 0x10000 * i;
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groups[i].intr_status_reg = 0x0c + 0x10000 * i;
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groups[i].intr_target_reg = 0x08 + 0x10000 * i;
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groups[i].mux_bit = 2;
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groups[i].pull_bit = 0;
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groups[i].drv_bit = 6;
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groups[i].oe_bit = 9;
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groups[i].in_bit = 0;
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groups[i].out_bit = 1;
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groups[i].intr_enable_bit = 0;
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groups[i].intr_status_bit = 0;
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groups[i].intr_target_bit = 5;
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groups[i].intr_target_kpss_val = 1;
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groups[i].intr_raw_status_bit = 4;
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groups[i].intr_polarity_bit = 1;
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groups[i].intr_detection_bit = 2;
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groups[i].intr_detection_width = 2;
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}
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qdf2xxx_pinctrl.pins = pins;
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qdf2xxx_pinctrl.groups = groups;
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qdf2xxx_pinctrl.npins = num_gpios;
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qdf2xxx_pinctrl.ngroups = num_gpios;
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qdf2xxx_pinctrl.ngpios = num_gpios;
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return msm_pinctrl_probe(pdev, &qdf2xxx_pinctrl);
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}
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static const struct acpi_device_id qdf2xxx_acpi_ids[] = {
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{"QCOM8001"},
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{},
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};
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MODULE_DEVICE_TABLE(acpi, qdf2xxx_acpi_ids);
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static struct platform_driver qdf2xxx_pinctrl_driver = {
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.driver = {
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.name = "qdf2xxx-pinctrl",
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.acpi_match_table = ACPI_PTR(qdf2xxx_acpi_ids),
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},
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.probe = qdf2xxx_pinctrl_probe,
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.remove = msm_pinctrl_remove,
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};
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static int __init qdf2xxx_pinctrl_init(void)
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{
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return platform_driver_register(&qdf2xxx_pinctrl_driver);
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}
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arch_initcall(qdf2xxx_pinctrl_init);
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static void __exit qdf2xxx_pinctrl_exit(void)
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{
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platform_driver_unregister(&qdf2xxx_pinctrl_driver);
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}
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module_exit(qdf2xxx_pinctrl_exit);
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MODULE_DESCRIPTION("Qualcomm Technologies QDF2xxx pin control driver");
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MODULE_LICENSE("GPL v2");
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