694 lines
15 KiB
C
694 lines
15 KiB
C
/*
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* Marvell 88E6xxx Switch Port Registers support
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*
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* Copyright (c) 2008 Marvell Semiconductor
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*
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* Copyright (c) 2016 Vivien Didelot <vivien.didelot@savoirfairelinux.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include "mv88e6xxx.h"
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#include "port.h"
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int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port, int reg,
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u16 *val)
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{
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int addr = chip->info->port_base_addr + port;
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return mv88e6xxx_read(chip, addr, reg, val);
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}
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int mv88e6xxx_port_write(struct mv88e6xxx_chip *chip, int port, int reg,
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u16 val)
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{
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int addr = chip->info->port_base_addr + port;
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return mv88e6xxx_write(chip, addr, reg, val);
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}
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/* Offset 0x01: MAC (or PCS or Physical) Control Register
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*
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* Link, Duplex and Flow Control have one force bit, one value bit.
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*
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* For port's MAC speed, ForceSpd (or SpdValue) bits 1:0 program the value.
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* Alternative values require the 200BASE (or AltSpeed) bit 12 set.
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* Newer chips need a ForcedSpd bit 13 set to consider the value.
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*/
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static int mv88e6xxx_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
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phy_interface_t mode)
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{
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u16 reg;
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int err;
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err = mv88e6xxx_port_read(chip, port, PORT_PCS_CTRL, ®);
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if (err)
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return err;
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reg &= ~(PORT_PCS_CTRL_RGMII_DELAY_RXCLK |
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PORT_PCS_CTRL_RGMII_DELAY_TXCLK);
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switch (mode) {
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case PHY_INTERFACE_MODE_RGMII_RXID:
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reg |= PORT_PCS_CTRL_RGMII_DELAY_RXCLK;
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break;
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case PHY_INTERFACE_MODE_RGMII_TXID:
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reg |= PORT_PCS_CTRL_RGMII_DELAY_TXCLK;
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break;
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case PHY_INTERFACE_MODE_RGMII_ID:
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reg |= PORT_PCS_CTRL_RGMII_DELAY_RXCLK |
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PORT_PCS_CTRL_RGMII_DELAY_TXCLK;
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break;
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case PHY_INTERFACE_MODE_RGMII:
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break;
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default:
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return 0;
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}
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err = mv88e6xxx_port_write(chip, port, PORT_PCS_CTRL, reg);
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if (err)
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return err;
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netdev_dbg(chip->ds->ports[port].netdev, "delay RXCLK %s, TXCLK %s\n",
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reg & PORT_PCS_CTRL_RGMII_DELAY_RXCLK ? "yes" : "no",
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reg & PORT_PCS_CTRL_RGMII_DELAY_TXCLK ? "yes" : "no");
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return 0;
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}
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int mv88e6352_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
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phy_interface_t mode)
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{
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if (port < 5)
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return -EOPNOTSUPP;
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return mv88e6xxx_port_set_rgmii_delay(chip, port, mode);
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}
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int mv88e6390_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
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phy_interface_t mode)
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{
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if (port != 0)
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return -EOPNOTSUPP;
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return mv88e6xxx_port_set_rgmii_delay(chip, port, mode);
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}
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int mv88e6xxx_port_set_link(struct mv88e6xxx_chip *chip, int port, int link)
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{
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u16 reg;
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int err;
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err = mv88e6xxx_port_read(chip, port, PORT_PCS_CTRL, ®);
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if (err)
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return err;
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reg &= ~(PORT_PCS_CTRL_FORCE_LINK | PORT_PCS_CTRL_LINK_UP);
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switch (link) {
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case LINK_FORCED_DOWN:
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reg |= PORT_PCS_CTRL_FORCE_LINK;
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break;
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case LINK_FORCED_UP:
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reg |= PORT_PCS_CTRL_FORCE_LINK | PORT_PCS_CTRL_LINK_UP;
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break;
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case LINK_UNFORCED:
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/* normal link detection */
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break;
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default:
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return -EINVAL;
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}
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err = mv88e6xxx_port_write(chip, port, PORT_PCS_CTRL, reg);
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if (err)
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return err;
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netdev_dbg(chip->ds->ports[port].netdev, "%s link %s\n",
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reg & PORT_PCS_CTRL_FORCE_LINK ? "Force" : "Unforce",
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reg & PORT_PCS_CTRL_LINK_UP ? "up" : "down");
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return 0;
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}
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int mv88e6xxx_port_set_duplex(struct mv88e6xxx_chip *chip, int port, int dup)
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{
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u16 reg;
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int err;
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err = mv88e6xxx_port_read(chip, port, PORT_PCS_CTRL, ®);
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if (err)
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return err;
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reg &= ~(PORT_PCS_CTRL_FORCE_DUPLEX | PORT_PCS_CTRL_DUPLEX_FULL);
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switch (dup) {
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case DUPLEX_HALF:
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reg |= PORT_PCS_CTRL_FORCE_DUPLEX;
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break;
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case DUPLEX_FULL:
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reg |= PORT_PCS_CTRL_FORCE_DUPLEX | PORT_PCS_CTRL_DUPLEX_FULL;
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break;
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case DUPLEX_UNFORCED:
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/* normal duplex detection */
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break;
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default:
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return -EINVAL;
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}
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err = mv88e6xxx_port_write(chip, port, PORT_PCS_CTRL, reg);
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if (err)
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return err;
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netdev_dbg(chip->ds->ports[port].netdev, "%s %s duplex\n",
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reg & PORT_PCS_CTRL_FORCE_DUPLEX ? "Force" : "Unforce",
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reg & PORT_PCS_CTRL_DUPLEX_FULL ? "full" : "half");
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return 0;
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}
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static int mv88e6xxx_port_set_speed(struct mv88e6xxx_chip *chip, int port,
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int speed, bool alt_bit, bool force_bit)
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{
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u16 reg, ctrl;
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int err;
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switch (speed) {
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case 10:
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ctrl = PORT_PCS_CTRL_SPEED_10;
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break;
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case 100:
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ctrl = PORT_PCS_CTRL_SPEED_100;
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break;
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case 200:
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if (alt_bit)
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ctrl = PORT_PCS_CTRL_SPEED_100 | PORT_PCS_CTRL_ALTSPEED;
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else
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ctrl = PORT_PCS_CTRL_SPEED_200;
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break;
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case 1000:
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ctrl = PORT_PCS_CTRL_SPEED_1000;
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break;
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case 2500:
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ctrl = PORT_PCS_CTRL_SPEED_1000 | PORT_PCS_CTRL_ALTSPEED;
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break;
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case 10000:
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/* all bits set, fall through... */
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case SPEED_UNFORCED:
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ctrl = PORT_PCS_CTRL_SPEED_UNFORCED;
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break;
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default:
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return -EOPNOTSUPP;
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}
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err = mv88e6xxx_port_read(chip, port, PORT_PCS_CTRL, ®);
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if (err)
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return err;
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reg &= ~PORT_PCS_CTRL_SPEED_MASK;
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if (alt_bit)
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reg &= ~PORT_PCS_CTRL_ALTSPEED;
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if (force_bit) {
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reg &= ~PORT_PCS_CTRL_FORCE_SPEED;
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if (speed != SPEED_UNFORCED)
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ctrl |= PORT_PCS_CTRL_FORCE_SPEED;
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}
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reg |= ctrl;
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err = mv88e6xxx_port_write(chip, port, PORT_PCS_CTRL, reg);
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if (err)
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return err;
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if (speed)
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netdev_dbg(chip->ds->ports[port].netdev,
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"Speed set to %d Mbps\n", speed);
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else
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netdev_dbg(chip->ds->ports[port].netdev, "Speed unforced\n");
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return 0;
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}
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/* Support 10, 100, 200 Mbps (e.g. 88E6065 family) */
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int mv88e6065_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed)
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{
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if (speed == SPEED_MAX)
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speed = 200;
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if (speed > 200)
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return -EOPNOTSUPP;
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/* Setting 200 Mbps on port 0 to 3 selects 100 Mbps */
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return mv88e6xxx_port_set_speed(chip, port, speed, false, false);
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}
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/* Support 10, 100, 1000 Mbps (e.g. 88E6185 family) */
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int mv88e6185_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed)
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{
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if (speed == SPEED_MAX)
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speed = 1000;
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if (speed == 200 || speed > 1000)
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return -EOPNOTSUPP;
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return mv88e6xxx_port_set_speed(chip, port, speed, false, false);
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}
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/* Support 10, 100, 200, 1000 Mbps (e.g. 88E6352 family) */
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int mv88e6352_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed)
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{
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if (speed == SPEED_MAX)
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speed = 1000;
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if (speed > 1000)
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return -EOPNOTSUPP;
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if (speed == 200 && port < 5)
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return -EOPNOTSUPP;
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return mv88e6xxx_port_set_speed(chip, port, speed, true, false);
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}
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/* Support 10, 100, 200, 1000, 2500 Mbps (e.g. 88E6390) */
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int mv88e6390_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed)
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{
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if (speed == SPEED_MAX)
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speed = port < 9 ? 1000 : 2500;
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if (speed > 2500)
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return -EOPNOTSUPP;
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if (speed == 200 && port != 0)
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return -EOPNOTSUPP;
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if (speed == 2500 && port < 9)
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return -EOPNOTSUPP;
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return mv88e6xxx_port_set_speed(chip, port, speed, true, true);
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}
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/* Support 10, 100, 200, 1000, 2500, 10000 Mbps (e.g. 88E6190X) */
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int mv88e6390x_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed)
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{
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if (speed == SPEED_MAX)
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speed = port < 9 ? 1000 : 10000;
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if (speed == 200 && port != 0)
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return -EOPNOTSUPP;
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if (speed >= 2500 && port < 9)
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return -EOPNOTSUPP;
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return mv88e6xxx_port_set_speed(chip, port, speed, true, true);
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}
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/* Offset 0x04: Port Control Register */
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static const char * const mv88e6xxx_port_state_names[] = {
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[PORT_CONTROL_STATE_DISABLED] = "Disabled",
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[PORT_CONTROL_STATE_BLOCKING] = "Blocking/Listening",
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[PORT_CONTROL_STATE_LEARNING] = "Learning",
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[PORT_CONTROL_STATE_FORWARDING] = "Forwarding",
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};
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int mv88e6xxx_port_set_state(struct mv88e6xxx_chip *chip, int port, u8 state)
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{
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u16 reg;
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int err;
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err = mv88e6xxx_port_read(chip, port, PORT_CONTROL, ®);
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if (err)
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return err;
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reg &= ~PORT_CONTROL_STATE_MASK;
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reg |= state;
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err = mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg);
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if (err)
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return err;
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netdev_dbg(chip->ds->ports[port].netdev, "PortState set to %s\n",
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mv88e6xxx_port_state_names[state]);
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return 0;
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}
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int mv88e6xxx_port_set_egress_mode(struct mv88e6xxx_chip *chip, int port,
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u16 mode)
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{
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int err;
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u16 reg;
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err = mv88e6xxx_port_read(chip, port, PORT_CONTROL, ®);
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if (err)
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return err;
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reg &= ~PORT_CONTROL_EGRESS_MASK;
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reg |= mode;
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return mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg);
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}
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int mv88e6085_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port,
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enum mv88e6xxx_frame_mode mode)
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{
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int err;
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u16 reg;
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err = mv88e6xxx_port_read(chip, port, PORT_CONTROL, ®);
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if (err)
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return err;
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reg &= ~PORT_CONTROL_FRAME_MODE_DSA;
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switch (mode) {
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case MV88E6XXX_FRAME_MODE_NORMAL:
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reg |= PORT_CONTROL_FRAME_MODE_NORMAL;
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break;
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case MV88E6XXX_FRAME_MODE_DSA:
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reg |= PORT_CONTROL_FRAME_MODE_DSA;
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break;
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default:
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return -EINVAL;
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}
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return mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg);
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}
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int mv88e6351_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port,
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enum mv88e6xxx_frame_mode mode)
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{
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int err;
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u16 reg;
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err = mv88e6xxx_port_read(chip, port, PORT_CONTROL, ®);
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if (err)
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return err;
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reg &= ~PORT_CONTROL_FRAME_MASK;
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switch (mode) {
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case MV88E6XXX_FRAME_MODE_NORMAL:
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reg |= PORT_CONTROL_FRAME_MODE_NORMAL;
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break;
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case MV88E6XXX_FRAME_MODE_DSA:
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reg |= PORT_CONTROL_FRAME_MODE_DSA;
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break;
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case MV88E6XXX_FRAME_MODE_PROVIDER:
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reg |= PORT_CONTROL_FRAME_MODE_PROVIDER;
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break;
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case MV88E6XXX_FRAME_MODE_ETHERTYPE:
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reg |= PORT_CONTROL_FRAME_ETHER_TYPE_DSA;
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break;
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default:
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return -EINVAL;
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}
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return mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg);
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}
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int mv88e6085_port_set_egress_unknowns(struct mv88e6xxx_chip *chip, int port,
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bool on)
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{
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int err;
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u16 reg;
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err = mv88e6xxx_port_read(chip, port, PORT_CONTROL, ®);
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if (err)
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return err;
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if (on)
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reg |= PORT_CONTROL_FORWARD_UNKNOWN;
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else
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reg &= ~PORT_CONTROL_FORWARD_UNKNOWN;
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return mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg);
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}
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int mv88e6351_port_set_egress_unknowns(struct mv88e6xxx_chip *chip, int port,
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bool on)
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{
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int err;
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u16 reg;
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err = mv88e6xxx_port_read(chip, port, PORT_CONTROL, ®);
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if (err)
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return err;
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if (on)
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reg |= PORT_CONTROL_EGRESS_ALL_UNKNOWN_DA;
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else
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reg &= ~PORT_CONTROL_EGRESS_ALL_UNKNOWN_DA;
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return mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg);
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}
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/* Offset 0x05: Port Control 1 */
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/* Offset 0x06: Port Based VLAN Map */
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int mv88e6xxx_port_set_vlan_map(struct mv88e6xxx_chip *chip, int port, u16 map)
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{
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const u16 mask = GENMASK(mv88e6xxx_num_ports(chip) - 1, 0);
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u16 reg;
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int err;
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err = mv88e6xxx_port_read(chip, port, PORT_BASE_VLAN, ®);
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if (err)
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return err;
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reg &= ~mask;
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reg |= map & mask;
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err = mv88e6xxx_port_write(chip, port, PORT_BASE_VLAN, reg);
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if (err)
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return err;
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netdev_dbg(chip->ds->ports[port].netdev, "VLANTable set to %.3x\n",
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map);
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return 0;
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}
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int mv88e6xxx_port_get_fid(struct mv88e6xxx_chip *chip, int port, u16 *fid)
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{
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const u16 upper_mask = (mv88e6xxx_num_databases(chip) - 1) >> 4;
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u16 reg;
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int err;
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/* Port's default FID lower 4 bits are located in reg 0x06, offset 12 */
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err = mv88e6xxx_port_read(chip, port, PORT_BASE_VLAN, ®);
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if (err)
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return err;
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*fid = (reg & 0xf000) >> 12;
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/* Port's default FID upper bits are located in reg 0x05, offset 0 */
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if (upper_mask) {
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err = mv88e6xxx_port_read(chip, port, PORT_CONTROL_1, ®);
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if (err)
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return err;
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*fid |= (reg & upper_mask) << 4;
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}
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return 0;
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}
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int mv88e6xxx_port_set_fid(struct mv88e6xxx_chip *chip, int port, u16 fid)
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{
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const u16 upper_mask = (mv88e6xxx_num_databases(chip) - 1) >> 4;
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u16 reg;
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int err;
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if (fid >= mv88e6xxx_num_databases(chip))
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return -EINVAL;
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/* Port's default FID lower 4 bits are located in reg 0x06, offset 12 */
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err = mv88e6xxx_port_read(chip, port, PORT_BASE_VLAN, ®);
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if (err)
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return err;
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|
reg &= 0x0fff;
|
|
reg |= (fid & 0x000f) << 12;
|
|
|
|
err = mv88e6xxx_port_write(chip, port, PORT_BASE_VLAN, reg);
|
|
if (err)
|
|
return err;
|
|
|
|
/* Port's default FID upper bits are located in reg 0x05, offset 0 */
|
|
if (upper_mask) {
|
|
err = mv88e6xxx_port_read(chip, port, PORT_CONTROL_1, ®);
|
|
if (err)
|
|
return err;
|
|
|
|
reg &= ~upper_mask;
|
|
reg |= (fid >> 4) & upper_mask;
|
|
|
|
err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_1, reg);
|
|
if (err)
|
|
return err;
|
|
}
|
|
|
|
netdev_dbg(chip->ds->ports[port].netdev, "FID set to %u\n", fid);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* Offset 0x07: Default Port VLAN ID & Priority */
|
|
|
|
int mv88e6xxx_port_get_pvid(struct mv88e6xxx_chip *chip, int port, u16 *pvid)
|
|
{
|
|
u16 reg;
|
|
int err;
|
|
|
|
err = mv88e6xxx_port_read(chip, port, PORT_DEFAULT_VLAN, ®);
|
|
if (err)
|
|
return err;
|
|
|
|
*pvid = reg & PORT_DEFAULT_VLAN_MASK;
|
|
|
|
return 0;
|
|
}
|
|
|
|
int mv88e6xxx_port_set_pvid(struct mv88e6xxx_chip *chip, int port, u16 pvid)
|
|
{
|
|
u16 reg;
|
|
int err;
|
|
|
|
err = mv88e6xxx_port_read(chip, port, PORT_DEFAULT_VLAN, ®);
|
|
if (err)
|
|
return err;
|
|
|
|
reg &= ~PORT_DEFAULT_VLAN_MASK;
|
|
reg |= pvid & PORT_DEFAULT_VLAN_MASK;
|
|
|
|
err = mv88e6xxx_port_write(chip, port, PORT_DEFAULT_VLAN, reg);
|
|
if (err)
|
|
return err;
|
|
|
|
netdev_dbg(chip->ds->ports[port].netdev, "DefaultVID set to %u\n",
|
|
pvid);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* Offset 0x08: Port Control 2 Register */
|
|
|
|
static const char * const mv88e6xxx_port_8021q_mode_names[] = {
|
|
[PORT_CONTROL_2_8021Q_DISABLED] = "Disabled",
|
|
[PORT_CONTROL_2_8021Q_FALLBACK] = "Fallback",
|
|
[PORT_CONTROL_2_8021Q_CHECK] = "Check",
|
|
[PORT_CONTROL_2_8021Q_SECURE] = "Secure",
|
|
};
|
|
|
|
int mv88e6xxx_port_set_8021q_mode(struct mv88e6xxx_chip *chip, int port,
|
|
u16 mode)
|
|
{
|
|
u16 reg;
|
|
int err;
|
|
|
|
err = mv88e6xxx_port_read(chip, port, PORT_CONTROL_2, ®);
|
|
if (err)
|
|
return err;
|
|
|
|
reg &= ~PORT_CONTROL_2_8021Q_MASK;
|
|
reg |= mode & PORT_CONTROL_2_8021Q_MASK;
|
|
|
|
err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_2, reg);
|
|
if (err)
|
|
return err;
|
|
|
|
netdev_dbg(chip->ds->ports[port].netdev, "802.1QMode set to %s\n",
|
|
mv88e6xxx_port_8021q_mode_names[mode]);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int mv88e6165_port_jumbo_config(struct mv88e6xxx_chip *chip, int port)
|
|
{
|
|
u16 reg;
|
|
int err;
|
|
|
|
err = mv88e6xxx_port_read(chip, port, PORT_CONTROL_2, ®);
|
|
if (err)
|
|
return err;
|
|
|
|
reg |= PORT_CONTROL_2_JUMBO_10240;
|
|
|
|
return mv88e6xxx_port_write(chip, port, PORT_CONTROL_2, reg);
|
|
}
|
|
|
|
/* Offset 0x0f: Port Ether type */
|
|
|
|
int mv88e6351_port_set_ether_type(struct mv88e6xxx_chip *chip, int port,
|
|
u16 etype)
|
|
{
|
|
return mv88e6xxx_port_write(chip, port, PORT_ETH_TYPE, etype);
|
|
}
|
|
|
|
/* Offset 0x18: Port IEEE Priority Remapping Registers [0-3]
|
|
* Offset 0x19: Port IEEE Priority Remapping Registers [4-7]
|
|
*/
|
|
|
|
int mv88e6095_port_tag_remap(struct mv88e6xxx_chip *chip, int port)
|
|
{
|
|
int err;
|
|
|
|
/* Use a direct priority mapping for all IEEE tagged frames */
|
|
err = mv88e6xxx_port_write(chip, port, PORT_TAG_REGMAP_0123, 0x3210);
|
|
if (err)
|
|
return err;
|
|
|
|
return mv88e6xxx_port_write(chip, port, PORT_TAG_REGMAP_4567, 0x7654);
|
|
}
|
|
|
|
static int mv88e6xxx_port_ieeepmt_write(struct mv88e6xxx_chip *chip,
|
|
int port, u16 table,
|
|
u8 pointer, u16 data)
|
|
{
|
|
u16 reg;
|
|
|
|
reg = PORT_IEEE_PRIO_MAP_TABLE_UPDATE |
|
|
table |
|
|
(pointer << PORT_IEEE_PRIO_MAP_TABLE_POINTER_SHIFT) |
|
|
data;
|
|
|
|
return mv88e6xxx_port_write(chip, port, PORT_IEEE_PRIO_MAP_TABLE, reg);
|
|
}
|
|
|
|
int mv88e6390_port_tag_remap(struct mv88e6xxx_chip *chip, int port)
|
|
{
|
|
int err, i;
|
|
|
|
for (i = 0; i <= 7; i++) {
|
|
err = mv88e6xxx_port_ieeepmt_write(
|
|
chip, port, PORT_IEEE_PRIO_MAP_TABLE_INGRESS_PCP,
|
|
i, (i | i << 4));
|
|
if (err)
|
|
return err;
|
|
|
|
err = mv88e6xxx_port_ieeepmt_write(
|
|
chip, port, PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_PCP,
|
|
i, i);
|
|
if (err)
|
|
return err;
|
|
|
|
err = mv88e6xxx_port_ieeepmt_write(
|
|
chip, port, PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_PCP,
|
|
i, i);
|
|
if (err)
|
|
return err;
|
|
|
|
err = mv88e6xxx_port_ieeepmt_write(
|
|
chip, port, PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_PCP,
|
|
i, i);
|
|
if (err)
|
|
return err;
|
|
}
|
|
|
|
return 0;
|
|
}
|