283 lines
8.4 KiB
C
283 lines
8.4 KiB
C
/*
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* Copyright 2012-15 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#ifndef __DC_LINK_ENCODER__DCE110_H__
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#define __DC_LINK_ENCODER__DCE110_H__
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#include "link_encoder.h"
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#define TO_DCE110_LINK_ENC(link_encoder)\
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container_of(link_encoder, struct dce110_link_encoder, base)
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/* Not found regs in dce120 spec
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* BIOS_SCRATCH_2
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* DP_DPHY_INTERNAL_CTRL
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*/
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#define AUX_REG_LIST(id)\
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SRI(AUX_CONTROL, DP_AUX, id), \
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SRI(AUX_DPHY_RX_CONTROL0, DP_AUX, id)
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#define HPD_REG_LIST(id)\
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SRI(DC_HPD_CONTROL, HPD, id)
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#define LE_COMMON_REG_LIST_BASE(id) \
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SR(LVTMA_PWRSEQ_CNTL), \
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SR(LVTMA_PWRSEQ_STATE), \
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SR(DMCU_RAM_ACCESS_CTRL), \
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SR(DMCU_IRAM_RD_CTRL), \
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SR(DMCU_IRAM_RD_DATA), \
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SR(DMCU_INTERRUPT_TO_UC_EN_MASK), \
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SRI(DIG_BE_CNTL, DIG, id), \
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SRI(DIG_BE_EN_CNTL, DIG, id), \
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SRI(DP_CONFIG, DP, id), \
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SRI(DP_DPHY_CNTL, DP, id), \
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SRI(DP_DPHY_PRBS_CNTL, DP, id), \
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SRI(DP_DPHY_SCRAM_CNTL, DP, id),\
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SRI(DP_DPHY_SYM0, DP, id), \
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SRI(DP_DPHY_SYM1, DP, id), \
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SRI(DP_DPHY_SYM2, DP, id), \
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SRI(DP_DPHY_TRAINING_PATTERN_SEL, DP, id), \
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SRI(DP_LINK_CNTL, DP, id), \
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SRI(DP_LINK_FRAMING_CNTL, DP, id), \
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SRI(DP_MSE_SAT0, DP, id), \
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SRI(DP_MSE_SAT1, DP, id), \
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SRI(DP_MSE_SAT2, DP, id), \
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SRI(DP_MSE_SAT_UPDATE, DP, id), \
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SRI(DP_SEC_CNTL, DP, id), \
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SRI(DP_VID_STREAM_CNTL, DP, id), \
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SRI(DP_DPHY_FAST_TRAINING, DP, id), \
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SRI(DP_SEC_CNTL1, DP, id)
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#define LE_COMMON_REG_LIST(id)\
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LE_COMMON_REG_LIST_BASE(id), \
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SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \
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SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
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SR(DCI_MEM_PWR_STATUS)
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#define LE_DCE80_REG_LIST(id)\
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SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
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LE_COMMON_REG_LIST_BASE(id)
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#define LE_DCE100_REG_LIST(id)\
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LE_COMMON_REG_LIST_BASE(id), \
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SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \
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SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
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SR(DCI_MEM_PWR_STATUS)
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#define LE_DCE110_REG_LIST(id)\
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LE_COMMON_REG_LIST_BASE(id), \
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SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \
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SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
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SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id), \
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SR(DCI_MEM_PWR_STATUS)
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#define LE_DCE120_REG_LIST(id)\
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LE_COMMON_REG_LIST_BASE(id), \
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SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \
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SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id), \
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SR(DCI_MEM_PWR_STATUS)
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#define LE_DCN10_REG_LIST(id)\
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LE_COMMON_REG_LIST_BASE(id), \
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SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \
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SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
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SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id), \
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SR(DMU_MEM_PWR_CNTL)
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struct dce110_link_enc_aux_registers {
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uint32_t AUX_CONTROL;
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uint32_t AUX_DPHY_RX_CONTROL0;
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};
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struct dce110_link_enc_hpd_registers {
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uint32_t DC_HPD_CONTROL;
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};
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struct dce110_link_enc_registers {
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/* Backlight registers */
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uint32_t LVTMA_PWRSEQ_CNTL;
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uint32_t LVTMA_PWRSEQ_STATE;
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/* DMCU registers */
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uint32_t MASTER_COMM_DATA_REG1;
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uint32_t MASTER_COMM_DATA_REG2;
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uint32_t MASTER_COMM_DATA_REG3;
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uint32_t MASTER_COMM_CMD_REG;
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uint32_t MASTER_COMM_CNTL_REG;
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uint32_t DMCU_RAM_ACCESS_CTRL;
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uint32_t DCI_MEM_PWR_STATUS;
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uint32_t DMU_MEM_PWR_CNTL;
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uint32_t DMCU_IRAM_RD_CTRL;
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uint32_t DMCU_IRAM_RD_DATA;
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uint32_t DMCU_INTERRUPT_TO_UC_EN_MASK;
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/* Common DP registers */
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uint32_t DIG_BE_CNTL;
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uint32_t DIG_BE_EN_CNTL;
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uint32_t DP_CONFIG;
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uint32_t DP_DPHY_CNTL;
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uint32_t DP_DPHY_INTERNAL_CTRL;
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uint32_t DP_DPHY_PRBS_CNTL;
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uint32_t DP_DPHY_SCRAM_CNTL;
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uint32_t DP_DPHY_SYM0;
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uint32_t DP_DPHY_SYM1;
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uint32_t DP_DPHY_SYM2;
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uint32_t DP_DPHY_TRAINING_PATTERN_SEL;
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uint32_t DP_LINK_CNTL;
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uint32_t DP_LINK_FRAMING_CNTL;
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uint32_t DP_MSE_SAT0;
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uint32_t DP_MSE_SAT1;
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uint32_t DP_MSE_SAT2;
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uint32_t DP_MSE_SAT_UPDATE;
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uint32_t DP_SEC_CNTL;
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uint32_t DP_VID_STREAM_CNTL;
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uint32_t DP_DPHY_FAST_TRAINING;
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uint32_t DP_DPHY_BS_SR_SWAP_CNTL;
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uint32_t DP_DPHY_HBR2_PATTERN_CONTROL;
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uint32_t DP_SEC_CNTL1;
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};
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struct dce110_link_encoder {
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struct link_encoder base;
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const struct dce110_link_enc_registers *link_regs;
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const struct dce110_link_enc_aux_registers *aux_regs;
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const struct dce110_link_enc_hpd_registers *hpd_regs;
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};
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bool dce110_link_encoder_construct(
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struct dce110_link_encoder *enc110,
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const struct encoder_init_data *init_data,
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const struct encoder_feature_support *enc_features,
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const struct dce110_link_enc_registers *link_regs,
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const struct dce110_link_enc_aux_registers *aux_regs,
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const struct dce110_link_enc_hpd_registers *hpd_regs);
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bool dce110_link_encoder_validate_dvi_output(
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const struct dce110_link_encoder *enc110,
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enum signal_type connector_signal,
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enum signal_type signal,
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const struct dc_crtc_timing *crtc_timing);
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bool dce110_link_encoder_validate_rgb_output(
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const struct dce110_link_encoder *enc110,
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const struct dc_crtc_timing *crtc_timing);
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bool dce110_link_encoder_validate_dp_output(
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const struct dce110_link_encoder *enc110,
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const struct dc_crtc_timing *crtc_timing);
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bool dce110_link_encoder_validate_wireless_output(
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const struct dce110_link_encoder *enc110,
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const struct dc_crtc_timing *crtc_timing);
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bool dce110_link_encoder_validate_output_with_stream(
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struct link_encoder *enc,
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const struct dc_stream_state *stream);
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/****************** HW programming ************************/
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/* initialize HW */ /* why do we initialze aux in here? */
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void dce110_link_encoder_hw_init(struct link_encoder *enc);
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void dce110_link_encoder_destroy(struct link_encoder **enc);
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/* program DIG_MODE in DIG_BE */
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/* TODO can this be combined with enable_output? */
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void dce110_link_encoder_setup(
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struct link_encoder *enc,
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enum signal_type signal);
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/* enables TMDS PHY output */
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/* TODO: still need depth or just pass in adjusted pixel clock? */
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void dce110_link_encoder_enable_tmds_output(
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struct link_encoder *enc,
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enum clock_source_id clock_source,
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enum dc_color_depth color_depth,
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bool hdmi,
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bool dual_link,
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uint32_t pixel_clock);
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/* enables DP PHY output */
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void dce110_link_encoder_enable_dp_output(
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struct link_encoder *enc,
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const struct dc_link_settings *link_settings,
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enum clock_source_id clock_source);
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/* enables DP PHY output in MST mode */
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void dce110_link_encoder_enable_dp_mst_output(
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struct link_encoder *enc,
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const struct dc_link_settings *link_settings,
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enum clock_source_id clock_source);
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/* disable PHY output */
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void dce110_link_encoder_disable_output(
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struct link_encoder *link_enc,
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enum signal_type signal);
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/* set DP lane settings */
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void dce110_link_encoder_dp_set_lane_settings(
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struct link_encoder *enc,
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const struct link_training_settings *link_settings);
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void dce110_link_encoder_dp_set_phy_pattern(
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struct link_encoder *enc,
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const struct encoder_set_dp_phy_pattern_param *param);
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/* programs DP MST VC payload allocation */
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void dce110_link_encoder_update_mst_stream_allocation_table(
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struct link_encoder *enc,
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const struct link_mst_stream_allocation_table *table);
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void dce110_link_encoder_edp_backlight_control(
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struct link_encoder *enc,
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bool enable);
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void dce110_link_encoder_edp_power_control(
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struct link_encoder *enc,
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bool power_up);
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void dce110_link_encoder_connect_dig_be_to_fe(
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struct link_encoder *enc,
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enum engine_id engine,
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bool connect);
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void dce110_link_encoder_set_dp_phy_pattern_training_pattern(
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struct link_encoder *enc,
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uint32_t index);
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void dce110_link_encoder_enable_hpd(struct link_encoder *enc);
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void dce110_link_encoder_disable_hpd(struct link_encoder *enc);
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void dce110_psr_program_dp_dphy_fast_training(struct link_encoder *enc,
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bool exit_link_training_required);
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void dce110_psr_program_secondary_packet(struct link_encoder *enc,
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unsigned int sdp_transmit_line_num_deadline);
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#endif /* __DC_LINK_ENCODER__DCE110_H__ */
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