2c23d9de9f
Correct the clock mode of PCIe PHY. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Fugang Duan <fugang.duan@nxp.com> |
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| .. | ||
| allwinner | ||
| amlogic | ||
| broadcom | ||
| cadence | ||
| freescale | ||
| hisilicon | ||
| lantiq | ||
| marvell | ||
| mediatek | ||
| motorola | ||
| mscc | ||
| qualcomm | ||
| ralink | ||
| renesas | ||
| rockchip | ||
| samsung | ||
| socionext | ||
| st | ||
| tegra | ||
| ti | ||
| Kconfig | ||
| Makefile | ||
| phy-core-mipi-dphy.c | ||
| phy-core.c | ||
| phy-lpc18xx-usb-otg.c | ||
| phy-mixel-lvds-combo.c | ||
| phy-mixel-lvds.c | ||
| phy-pistachio-usb.c | ||
| phy-xgene.c | ||