![Nishanth Aravamudan](/assets/img/avatar_default.png)
Use schedule_timeout_interruptible() instead of set_current_state()/schedule_timeout() to reduce kernel size. Signed-off-by: Nishanth Aravamudan <nacc@us.ibm.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
628 lines
14 KiB
C
628 lines
14 KiB
C
/*
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Hardware driver for the Intel/AMD/VIA Random Number Generators (RNG)
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(c) Copyright 2003 Red Hat Inc <jgarzik@redhat.com>
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derived from
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Hardware driver for the AMD 768 Random Number Generator (RNG)
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(c) Copyright 2001 Red Hat Inc <alan@redhat.com>
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derived from
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Hardware driver for Intel i810 Random Number Generator (RNG)
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Copyright 2000,2001 Jeff Garzik <jgarzik@pobox.com>
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Copyright 2000,2001 Philipp Rumpf <prumpf@mandrakesoft.com>
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Please read Documentation/hw_random.txt for details on use.
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----------------------------------------------------------
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This software may be used and distributed according to the terms
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of the GNU General Public License, incorporated herein by reference.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/fs.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <linux/interrupt.h>
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#include <linux/spinlock.h>
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#include <linux/random.h>
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#include <linux/miscdevice.h>
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#include <linux/smp_lock.h>
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#include <linux/mm.h>
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#include <linux/delay.h>
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#ifdef __i386__
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#include <asm/msr.h>
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#include <asm/cpufeature.h>
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#endif
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#include <asm/io.h>
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#include <asm/uaccess.h>
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/*
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* core module and version information
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*/
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#define RNG_VERSION "1.0.0"
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#define RNG_MODULE_NAME "hw_random"
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#define RNG_DRIVER_NAME RNG_MODULE_NAME " hardware driver " RNG_VERSION
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#define PFX RNG_MODULE_NAME ": "
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/*
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* debugging macros
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*/
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/* pr_debug() collapses to a no-op if DEBUG is not defined */
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#define DPRINTK(fmt, args...) pr_debug(PFX "%s: " fmt, __FUNCTION__ , ## args)
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#undef RNG_NDEBUG /* define to enable lightweight runtime checks */
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#ifdef RNG_NDEBUG
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#define assert(expr) \
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if(!(expr)) { \
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printk(KERN_DEBUG PFX "Assertion failed! %s,%s,%s," \
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"line=%d\n", #expr, __FILE__, __FUNCTION__, __LINE__); \
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}
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#else
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#define assert(expr)
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#endif
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#define RNG_MISCDEV_MINOR 183 /* official */
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static int rng_dev_open (struct inode *inode, struct file *filp);
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static ssize_t rng_dev_read (struct file *filp, char __user *buf, size_t size,
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loff_t * offp);
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static int __init intel_init (struct pci_dev *dev);
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static void intel_cleanup(void);
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static unsigned int intel_data_present (void);
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static u32 intel_data_read (void);
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static int __init amd_init (struct pci_dev *dev);
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static void amd_cleanup(void);
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static unsigned int amd_data_present (void);
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static u32 amd_data_read (void);
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#ifdef __i386__
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static int __init via_init(struct pci_dev *dev);
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static void via_cleanup(void);
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static unsigned int via_data_present (void);
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static u32 via_data_read (void);
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#endif
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struct rng_operations {
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int (*init) (struct pci_dev *dev);
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void (*cleanup) (void);
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unsigned int (*data_present) (void);
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u32 (*data_read) (void);
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unsigned int n_bytes; /* number of bytes per ->data_read */
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};
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static struct rng_operations *rng_ops;
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static struct file_operations rng_chrdev_ops = {
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.owner = THIS_MODULE,
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.open = rng_dev_open,
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.read = rng_dev_read,
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};
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static struct miscdevice rng_miscdev = {
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RNG_MISCDEV_MINOR,
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RNG_MODULE_NAME,
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&rng_chrdev_ops,
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};
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enum {
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rng_hw_none,
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rng_hw_intel,
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rng_hw_amd,
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rng_hw_via,
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};
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static struct rng_operations rng_vendor_ops[] = {
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/* rng_hw_none */
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{ },
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/* rng_hw_intel */
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{ intel_init, intel_cleanup, intel_data_present,
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intel_data_read, 1 },
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/* rng_hw_amd */
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{ amd_init, amd_cleanup, amd_data_present, amd_data_read, 4 },
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#ifdef __i386__
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/* rng_hw_via */
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{ via_init, via_cleanup, via_data_present, via_data_read, 1 },
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#endif
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};
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/*
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* Data for PCI driver interface
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*
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* This data only exists for exporting the supported
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* PCI ids via MODULE_DEVICE_TABLE. We do not actually
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* register a pci_driver, because someone else might one day
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* want to register another driver on the same PCI id.
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*/
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static struct pci_device_id rng_pci_tbl[] = {
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{ 0x1022, 0x7443, PCI_ANY_ID, PCI_ANY_ID, 0, 0, rng_hw_amd },
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{ 0x1022, 0x746b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, rng_hw_amd },
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{ 0x8086, 0x2418, PCI_ANY_ID, PCI_ANY_ID, 0, 0, rng_hw_intel },
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{ 0x8086, 0x2428, PCI_ANY_ID, PCI_ANY_ID, 0, 0, rng_hw_intel },
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{ 0x8086, 0x2448, PCI_ANY_ID, PCI_ANY_ID, 0, 0, rng_hw_intel },
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{ 0x8086, 0x244e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, rng_hw_intel },
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{ 0x8086, 0x245e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, rng_hw_intel },
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{ 0, }, /* terminate list */
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};
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MODULE_DEVICE_TABLE (pci, rng_pci_tbl);
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/***********************************************************************
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*
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* Intel RNG operations
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*
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*/
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/*
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* RNG registers (offsets from rng_mem)
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*/
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#define INTEL_RNG_HW_STATUS 0
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#define INTEL_RNG_PRESENT 0x40
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#define INTEL_RNG_ENABLED 0x01
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#define INTEL_RNG_STATUS 1
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#define INTEL_RNG_DATA_PRESENT 0x01
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#define INTEL_RNG_DATA 2
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/*
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* Magic address at which Intel PCI bridges locate the RNG
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*/
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#define INTEL_RNG_ADDR 0xFFBC015F
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#define INTEL_RNG_ADDR_LEN 3
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/* token to our ioremap'd RNG register area */
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static void __iomem *rng_mem;
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static inline u8 intel_hwstatus (void)
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{
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assert (rng_mem != NULL);
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return readb (rng_mem + INTEL_RNG_HW_STATUS);
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}
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static inline u8 intel_hwstatus_set (u8 hw_status)
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{
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assert (rng_mem != NULL);
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writeb (hw_status, rng_mem + INTEL_RNG_HW_STATUS);
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return intel_hwstatus ();
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}
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static unsigned int intel_data_present(void)
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{
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assert (rng_mem != NULL);
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return (readb (rng_mem + INTEL_RNG_STATUS) & INTEL_RNG_DATA_PRESENT) ?
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1 : 0;
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}
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static u32 intel_data_read(void)
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{
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assert (rng_mem != NULL);
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return readb (rng_mem + INTEL_RNG_DATA);
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}
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static int __init intel_init (struct pci_dev *dev)
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{
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int rc;
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u8 hw_status;
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DPRINTK ("ENTER\n");
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rng_mem = ioremap (INTEL_RNG_ADDR, INTEL_RNG_ADDR_LEN);
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if (rng_mem == NULL) {
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printk (KERN_ERR PFX "cannot ioremap RNG Memory\n");
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rc = -EBUSY;
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goto err_out;
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}
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/* Check for Intel 82802 */
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hw_status = intel_hwstatus ();
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if ((hw_status & INTEL_RNG_PRESENT) == 0) {
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printk (KERN_ERR PFX "RNG not detected\n");
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rc = -ENODEV;
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goto err_out_free_map;
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}
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/* turn RNG h/w on, if it's off */
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if ((hw_status & INTEL_RNG_ENABLED) == 0)
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hw_status = intel_hwstatus_set (hw_status | INTEL_RNG_ENABLED);
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if ((hw_status & INTEL_RNG_ENABLED) == 0) {
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printk (KERN_ERR PFX "cannot enable RNG, aborting\n");
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rc = -EIO;
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goto err_out_free_map;
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}
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DPRINTK ("EXIT, returning 0\n");
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return 0;
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err_out_free_map:
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iounmap (rng_mem);
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rng_mem = NULL;
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err_out:
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DPRINTK ("EXIT, returning %d\n", rc);
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return rc;
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}
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static void intel_cleanup(void)
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{
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u8 hw_status;
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hw_status = intel_hwstatus ();
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if (hw_status & INTEL_RNG_ENABLED)
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intel_hwstatus_set (hw_status & ~INTEL_RNG_ENABLED);
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else
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printk(KERN_WARNING PFX "unusual: RNG already disabled\n");
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iounmap(rng_mem);
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rng_mem = NULL;
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}
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/***********************************************************************
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*
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* AMD RNG operations
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*
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*/
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static u32 pmbase; /* PMxx I/O base */
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static struct pci_dev *amd_dev;
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static unsigned int amd_data_present (void)
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{
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return inl(pmbase + 0xF4) & 1;
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}
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static u32 amd_data_read (void)
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{
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return inl(pmbase + 0xF0);
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}
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static int __init amd_init (struct pci_dev *dev)
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{
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int rc;
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u8 rnen;
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DPRINTK ("ENTER\n");
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pci_read_config_dword(dev, 0x58, &pmbase);
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pmbase &= 0x0000FF00;
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if (pmbase == 0)
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{
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printk (KERN_ERR PFX "power management base not set\n");
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rc = -EIO;
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goto err_out;
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}
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pci_read_config_byte(dev, 0x40, &rnen);
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rnen |= (1 << 7); /* RNG on */
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pci_write_config_byte(dev, 0x40, rnen);
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pci_read_config_byte(dev, 0x41, &rnen);
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rnen |= (1 << 7); /* PMIO enable */
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pci_write_config_byte(dev, 0x41, rnen);
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pr_info( PFX "AMD768 system management I/O registers at 0x%X.\n",
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pmbase);
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amd_dev = dev;
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DPRINTK ("EXIT, returning 0\n");
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return 0;
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err_out:
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DPRINTK ("EXIT, returning %d\n", rc);
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return rc;
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}
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static void amd_cleanup(void)
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{
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u8 rnen;
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pci_read_config_byte(amd_dev, 0x40, &rnen);
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rnen &= ~(1 << 7); /* RNG off */
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pci_write_config_byte(amd_dev, 0x40, rnen);
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/* FIXME: twiddle pmio, also? */
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}
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#ifdef __i386__
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/***********************************************************************
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*
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* VIA RNG operations
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*
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*/
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enum {
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VIA_STRFILT_CNT_SHIFT = 16,
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VIA_STRFILT_FAIL = (1 << 15),
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VIA_STRFILT_ENABLE = (1 << 14),
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VIA_RAWBITS_ENABLE = (1 << 13),
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VIA_RNG_ENABLE = (1 << 6),
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VIA_XSTORE_CNT_MASK = 0x0F,
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VIA_RNG_CHUNK_8 = 0x00, /* 64 rand bits, 64 stored bits */
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VIA_RNG_CHUNK_4 = 0x01, /* 32 rand bits, 32 stored bits */
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VIA_RNG_CHUNK_4_MASK = 0xFFFFFFFF,
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VIA_RNG_CHUNK_2 = 0x02, /* 16 rand bits, 32 stored bits */
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VIA_RNG_CHUNK_2_MASK = 0xFFFF,
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VIA_RNG_CHUNK_1 = 0x03, /* 8 rand bits, 32 stored bits */
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VIA_RNG_CHUNK_1_MASK = 0xFF,
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};
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static u32 via_rng_datum;
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/*
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* Investigate using the 'rep' prefix to obtain 32 bits of random data
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* in one insn. The upside is potentially better performance. The
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* downside is that the instruction becomes no longer atomic. Due to
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* this, just like familiar issues with /dev/random itself, the worst
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* case of a 'rep xstore' could potentially pause a cpu for an
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* unreasonably long time. In practice, this condition would likely
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* only occur when the hardware is failing. (or so we hope :))
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*
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* Another possible performance boost may come from simply buffering
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* until we have 4 bytes, thus returning a u32 at a time,
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* instead of the current u8-at-a-time.
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*/
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static inline u32 xstore(u32 *addr, u32 edx_in)
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{
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u32 eax_out;
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asm(".byte 0x0F,0xA7,0xC0 /* xstore %%edi (addr=%0) */"
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:"=m"(*addr), "=a"(eax_out)
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:"D"(addr), "d"(edx_in));
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return eax_out;
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}
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static unsigned int via_data_present(void)
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{
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u32 bytes_out;
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/* We choose the recommended 1-byte-per-instruction RNG rate,
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* for greater randomness at the expense of speed. Larger
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* values 2, 4, or 8 bytes-per-instruction yield greater
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* speed at lesser randomness.
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*
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* If you change this to another VIA_CHUNK_n, you must also
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* change the ->n_bytes values in rng_vendor_ops[] tables.
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* VIA_CHUNK_8 requires further code changes.
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*
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* A copy of MSR_VIA_RNG is placed in eax_out when xstore
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* completes.
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*/
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via_rng_datum = 0; /* paranoia, not really necessary */
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bytes_out = xstore(&via_rng_datum, VIA_RNG_CHUNK_1) & VIA_XSTORE_CNT_MASK;
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if (bytes_out == 0)
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return 0;
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return 1;
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}
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static u32 via_data_read(void)
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{
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return via_rng_datum;
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}
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static int __init via_init(struct pci_dev *dev)
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{
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u32 lo, hi, old_lo;
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/* Control the RNG via MSR. Tread lightly and pay very close
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* close attention to values written, as the reserved fields
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* are documented to be "undefined and unpredictable"; but it
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* does not say to write them as zero, so I make a guess that
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* we restore the values we find in the register.
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*/
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rdmsr(MSR_VIA_RNG, lo, hi);
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old_lo = lo;
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lo &= ~(0x7f << VIA_STRFILT_CNT_SHIFT);
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lo &= ~VIA_XSTORE_CNT_MASK;
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lo &= ~(VIA_STRFILT_ENABLE | VIA_STRFILT_FAIL | VIA_RAWBITS_ENABLE);
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lo |= VIA_RNG_ENABLE;
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if (lo != old_lo)
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wrmsr(MSR_VIA_RNG, lo, hi);
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/* perhaps-unnecessary sanity check; remove after testing if
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unneeded */
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rdmsr(MSR_VIA_RNG, lo, hi);
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if ((lo & VIA_RNG_ENABLE) == 0) {
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printk(KERN_ERR PFX "cannot enable VIA C3 RNG, aborting\n");
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return -ENODEV;
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}
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return 0;
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}
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static void via_cleanup(void)
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{
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/* do nothing */
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}
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#endif
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/***********************************************************************
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*
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* /dev/hwrandom character device handling (major 10, minor 183)
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*
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*/
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static int rng_dev_open (struct inode *inode, struct file *filp)
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{
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/* enforce read-only access to this chrdev */
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if ((filp->f_mode & FMODE_READ) == 0)
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return -EINVAL;
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if (filp->f_mode & FMODE_WRITE)
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return -EINVAL;
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return 0;
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}
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static ssize_t rng_dev_read (struct file *filp, char __user *buf, size_t size,
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loff_t * offp)
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{
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static DEFINE_SPINLOCK(rng_lock);
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unsigned int have_data;
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u32 data = 0;
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ssize_t ret = 0;
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while (size) {
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spin_lock(&rng_lock);
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have_data = 0;
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if (rng_ops->data_present()) {
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data = rng_ops->data_read();
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have_data = rng_ops->n_bytes;
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}
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spin_unlock (&rng_lock);
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while (have_data && size) {
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if (put_user((u8)data, buf++)) {
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ret = ret ? : -EFAULT;
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break;
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}
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size--;
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ret++;
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have_data--;
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data>>=8;
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}
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if (filp->f_flags & O_NONBLOCK)
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return ret ? : -EAGAIN;
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if(need_resched())
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schedule_timeout_interruptible(1);
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else
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udelay(200); /* FIXME: We could poll for 250uS ?? */
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if (signal_pending (current))
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return ret ? : -ERESTARTSYS;
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}
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return ret;
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|
}
|
|
|
|
|
|
|
|
/*
|
|
* rng_init_one - look for and attempt to init a single RNG
|
|
*/
|
|
static int __init rng_init_one (struct pci_dev *dev)
|
|
{
|
|
int rc;
|
|
|
|
DPRINTK ("ENTER\n");
|
|
|
|
assert(rng_ops != NULL);
|
|
|
|
rc = rng_ops->init(dev);
|
|
if (rc)
|
|
goto err_out;
|
|
|
|
rc = misc_register (&rng_miscdev);
|
|
if (rc) {
|
|
printk (KERN_ERR PFX "misc device register failed\n");
|
|
goto err_out_cleanup_hw;
|
|
}
|
|
|
|
DPRINTK ("EXIT, returning 0\n");
|
|
return 0;
|
|
|
|
err_out_cleanup_hw:
|
|
rng_ops->cleanup();
|
|
err_out:
|
|
DPRINTK ("EXIT, returning %d\n", rc);
|
|
return rc;
|
|
}
|
|
|
|
|
|
|
|
MODULE_AUTHOR("The Linux Kernel team");
|
|
MODULE_DESCRIPTION("H/W Random Number Generator (RNG) driver");
|
|
MODULE_LICENSE("GPL");
|
|
|
|
|
|
/*
|
|
* rng_init - initialize RNG module
|
|
*/
|
|
static int __init rng_init (void)
|
|
{
|
|
int rc;
|
|
struct pci_dev *pdev = NULL;
|
|
const struct pci_device_id *ent;
|
|
|
|
DPRINTK ("ENTER\n");
|
|
|
|
/* Probe for Intel, AMD RNGs */
|
|
for_each_pci_dev(pdev) {
|
|
ent = pci_match_id(rng_pci_tbl, pdev);
|
|
if (ent) {
|
|
rng_ops = &rng_vendor_ops[ent->driver_data];
|
|
goto match;
|
|
}
|
|
}
|
|
|
|
#ifdef __i386__
|
|
/* Probe for VIA RNG */
|
|
if (cpu_has_xstore) {
|
|
rng_ops = &rng_vendor_ops[rng_hw_via];
|
|
pdev = NULL;
|
|
goto match;
|
|
}
|
|
#endif
|
|
|
|
DPRINTK ("EXIT, returning -ENODEV\n");
|
|
return -ENODEV;
|
|
|
|
match:
|
|
rc = rng_init_one (pdev);
|
|
if (rc)
|
|
return rc;
|
|
|
|
pr_info( RNG_DRIVER_NAME " loaded\n");
|
|
|
|
DPRINTK ("EXIT, returning 0\n");
|
|
return 0;
|
|
}
|
|
|
|
|
|
/*
|
|
* rng_init - shutdown RNG module
|
|
*/
|
|
static void __exit rng_cleanup (void)
|
|
{
|
|
DPRINTK ("ENTER\n");
|
|
|
|
misc_deregister (&rng_miscdev);
|
|
|
|
if (rng_ops->cleanup)
|
|
rng_ops->cleanup();
|
|
|
|
DPRINTK ("EXIT\n");
|
|
}
|
|
|
|
|
|
module_init (rng_init);
|
|
module_exit (rng_cleanup);
|