![Peter De Schrijver](/assets/img/avatar_default.png)
Add a table lookup feature to the mux clock. Also allow arbitrary masks instead of the width. This will be used by some clocks on Tegra114. Also adapt the tegra periph clk because it uses struct clk_mux directly. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
156 lines
3.8 KiB
C
156 lines
3.8 KiB
C
/*
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* Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
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* Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org>
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* Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Simple multiplexer clock implementation
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/module.h>
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#include <linux/slab.h>
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#include <linux/io.h>
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#include <linux/err.h>
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/*
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* DOC: basic adjustable multiplexer clock that cannot gate
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*
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* Traits of this clock:
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* prepare - clk_prepare only ensures that parents are prepared
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* enable - clk_enable only ensures that parents are enabled
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* rate - rate is only affected by parent switching. No clk_set_rate support
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* parent - parent is adjustable through clk_set_parent
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*/
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#define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw)
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static u8 clk_mux_get_parent(struct clk_hw *hw)
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{
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struct clk_mux *mux = to_clk_mux(hw);
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int num_parents = __clk_get_num_parents(hw->clk);
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u32 val;
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/*
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* FIXME need a mux-specific flag to determine if val is bitwise or numeric
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* e.g. sys_clkin_ck's clksel field is 3 bits wide, but ranges from 0x1
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* to 0x7 (index starts at one)
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* OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so
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* val = 0x4 really means "bit 2, index starts at bit 0"
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*/
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val = readl(mux->reg) >> mux->shift;
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val &= mux->mask;
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if (mux->table) {
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int i;
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for (i = 0; i < num_parents; i++)
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if (mux->table[i] == val)
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return i;
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return -EINVAL;
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}
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if (val && (mux->flags & CLK_MUX_INDEX_BIT))
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val = ffs(val) - 1;
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if (val && (mux->flags & CLK_MUX_INDEX_ONE))
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val--;
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if (val >= num_parents)
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return -EINVAL;
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return val;
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}
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static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
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{
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struct clk_mux *mux = to_clk_mux(hw);
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u32 val;
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unsigned long flags = 0;
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if (mux->table)
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index = mux->table[index];
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else {
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if (mux->flags & CLK_MUX_INDEX_BIT)
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index = (1 << ffs(index));
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if (mux->flags & CLK_MUX_INDEX_ONE)
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index++;
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}
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if (mux->lock)
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spin_lock_irqsave(mux->lock, flags);
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val = readl(mux->reg);
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val &= ~(mux->mask << mux->shift);
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val |= index << mux->shift;
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writel(val, mux->reg);
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if (mux->lock)
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spin_unlock_irqrestore(mux->lock, flags);
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return 0;
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}
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const struct clk_ops clk_mux_ops = {
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.get_parent = clk_mux_get_parent,
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.set_parent = clk_mux_set_parent,
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};
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EXPORT_SYMBOL_GPL(clk_mux_ops);
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struct clk *clk_register_mux_table(struct device *dev, const char *name,
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const char **parent_names, u8 num_parents, unsigned long flags,
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void __iomem *reg, u8 shift, u32 mask,
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u8 clk_mux_flags, u32 *table, spinlock_t *lock)
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{
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struct clk_mux *mux;
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struct clk *clk;
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struct clk_init_data init;
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/* allocate the mux */
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mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL);
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if (!mux) {
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pr_err("%s: could not allocate mux clk\n", __func__);
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return ERR_PTR(-ENOMEM);
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}
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init.name = name;
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init.ops = &clk_mux_ops;
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init.flags = flags | CLK_IS_BASIC;
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init.parent_names = parent_names;
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init.num_parents = num_parents;
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/* struct clk_mux assignments */
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mux->reg = reg;
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mux->shift = shift;
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mux->mask = mask;
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mux->flags = clk_mux_flags;
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mux->lock = lock;
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mux->table = table;
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mux->hw.init = &init;
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clk = clk_register(dev, &mux->hw);
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if (IS_ERR(clk))
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kfree(mux);
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return clk;
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}
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struct clk *clk_register_mux(struct device *dev, const char *name,
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const char **parent_names, u8 num_parents, unsigned long flags,
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void __iomem *reg, u8 shift, u8 width,
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u8 clk_mux_flags, spinlock_t *lock)
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{
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u32 mask = BIT(width) - 1;
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return clk_register_mux_table(dev, name, parent_names, num_parents,
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flags, reg, shift, mask, clk_mux_flags,
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NULL, lock);
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}
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