02b4e2756e
All ARMv5 and older CPUs invalidate their caches in the early assembly setup function, prior to enabling the MMU. This is because the L1 cache should not contain any data relevant to the execution of the kernel at this point; all data should have been flushed out to memory. This requirement should also be true for ARMv6 and ARMv7 CPUs - indeed, these typically do not search their caches when caching is disabled (as it needs to be when the MMU is disabled) so this change should be safe. ARMv7 allows there to be CPUs which search their caches while caching is disabled, and it's permitted that the cache is uninitialised at boot; for these, the architecture reference manual requires that an implementation specific code sequence is used immediately after reset to ensure that the cache is placed into a sane state. Such functionality is definitely outside the remit of the Linux kernel, and must be done by the SoC's firmware before _any_ CPU gets to the Linux kernel. Changing the data cache clean+invalidate to a mere invalidate allows us to get rid of a lot of platform specific hacks around this issue for their secondary CPU bringup paths - some of which were buggy. Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Tested-by: Florian Fainelli <f.fainelli@gmail.com> Tested-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Shawn Guo <shawn.guo@linaro.org> Tested-by: Thierry Reding <treding@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Tested-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Michal Simek <michal.simek@xilinx.com> Tested-by: Wei Xu <xuwei5@hisilicon.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
92 lines
2 KiB
ArmAsm
92 lines
2 KiB
ArmAsm
/*
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* SMP support for R-Mobile / SH-Mobile
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*
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* Copyright (C) 2010 Magnus Damm
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* Copyright (C) 2010 Takashi Yoshii
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*
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* Based on vexpress, Copyright (c) 2003 ARM Limited, All Rights Reserved
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/linkage.h>
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#include <linux/threads.h>
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#include <asm/assembler.h>
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#include <asm/memory.h>
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/*
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* Reset vector for secondary CPUs.
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* This will be mapped at address 0 by SBAR register.
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* We need _long_ jump to the physical address.
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*/
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.arm
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.align 12
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ENTRY(shmobile_boot_vector)
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ldr r0, 2f
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ldr r1, 1f
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bx r1
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ENDPROC(shmobile_boot_vector)
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.align 2
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.globl shmobile_boot_fn
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shmobile_boot_fn:
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1: .space 4
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.globl shmobile_boot_arg
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shmobile_boot_arg:
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2: .space 4
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.globl shmobile_boot_size
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shmobile_boot_size:
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.long . - shmobile_boot_vector
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/*
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* Per-CPU SMP boot function/argument selection code based on MPIDR
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*/
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ENTRY(shmobile_smp_boot)
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@ r0 = MPIDR_HWID_BITMASK
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mrc p15, 0, r1, c0, c0, 5 @ r1 = MPIDR
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and r0, r1, r0 @ r0 = cpu_logical_map() value
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mov r1, #0 @ r1 = CPU index
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adr r5, 1f @ array of per-cpu mpidr values
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adr r6, 2f @ array of per-cpu functions
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adr r7, 3f @ array of per-cpu arguments
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shmobile_smp_boot_find_mpidr:
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ldr r8, [r5, r1, lsl #2]
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cmp r8, r0
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bne shmobile_smp_boot_next
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ldr r9, [r6, r1, lsl #2]
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cmp r9, #0
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bne shmobile_smp_boot_found
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shmobile_smp_boot_next:
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add r1, r1, #1
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cmp r1, #NR_CPUS
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blo shmobile_smp_boot_find_mpidr
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b shmobile_smp_sleep
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shmobile_smp_boot_found:
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ldr r0, [r7, r1, lsl #2]
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ret r9
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ENDPROC(shmobile_smp_boot)
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ENTRY(shmobile_smp_sleep)
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wfi
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b shmobile_smp_boot
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ENDPROC(shmobile_smp_sleep)
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.globl shmobile_smp_mpidr
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shmobile_smp_mpidr:
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1: .space NR_CPUS * 4
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.globl shmobile_smp_fn
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shmobile_smp_fn:
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2: .space NR_CPUS * 4
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.globl shmobile_smp_arg
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shmobile_smp_arg:
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3: .space NR_CPUS * 4
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