02b4e2756e
All ARMv5 and older CPUs invalidate their caches in the early assembly setup function, prior to enabling the MMU. This is because the L1 cache should not contain any data relevant to the execution of the kernel at this point; all data should have been flushed out to memory. This requirement should also be true for ARMv6 and ARMv7 CPUs - indeed, these typically do not search their caches when caching is disabled (as it needs to be when the MMU is disabled) so this change should be safe. ARMv7 allows there to be CPUs which search their caches while caching is disabled, and it's permitted that the cache is uninitialised at boot; for these, the architecture reference manual requires that an implementation specific code sequence is used immediately after reset to ensure that the cache is placed into a sane state. Such functionality is definitely outside the remit of the Linux kernel, and must be done by the SoC's firmware before _any_ CPU gets to the Linux kernel. Changing the data cache clean+invalidate to a mere invalidate allows us to get rid of a lot of platform specific hacks around this issue for their secondary CPU bringup paths - some of which were buggy. Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Tested-by: Florian Fainelli <f.fainelli@gmail.com> Tested-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Shawn Guo <shawn.guo@linaro.org> Tested-by: Thierry Reding <treding@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Tested-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Michal Simek <michal.simek@xilinx.com> Tested-by: Wei Xu <xuwei5@hisilicon.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
109 lines
2.7 KiB
C
109 lines
2.7 KiB
C
/*
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* arch/arm/mach-tegra/reset.c
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*
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* Copyright (C) 2011,2012 NVIDIA Corporation.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/bitops.h>
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#include <linux/cpumask.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <soc/tegra/fuse.h>
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#include <asm/cacheflush.h>
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#include <asm/firmware.h>
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#include <asm/hardware/cache-l2x0.h>
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#include "iomap.h"
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#include "irammap.h"
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#include "reset.h"
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#include "sleep.h"
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#define TEGRA_IRAM_RESET_BASE (TEGRA_IRAM_BASE + \
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TEGRA_IRAM_RESET_HANDLER_OFFSET)
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static bool is_enabled;
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static void __init tegra_cpu_reset_handler_set(const u32 reset_address)
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{
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void __iomem *evp_cpu_reset =
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IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE + 0x100);
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void __iomem *sb_ctrl = IO_ADDRESS(TEGRA_SB_BASE);
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u32 reg;
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/*
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* NOTE: This must be the one and only write to the EVP CPU reset
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* vector in the entire system.
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*/
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writel(reset_address, evp_cpu_reset);
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wmb();
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reg = readl(evp_cpu_reset);
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/*
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* Prevent further modifications to the physical reset vector.
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* NOTE: Has no effect on chips prior to Tegra30.
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*/
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reg = readl(sb_ctrl);
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reg |= 2;
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writel(reg, sb_ctrl);
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wmb();
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}
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static void __init tegra_cpu_reset_handler_enable(void)
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{
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void __iomem *iram_base = IO_ADDRESS(TEGRA_IRAM_RESET_BASE);
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const u32 reset_address = TEGRA_IRAM_RESET_BASE +
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tegra_cpu_reset_handler_offset;
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int err;
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BUG_ON(is_enabled);
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BUG_ON(tegra_cpu_reset_handler_size > TEGRA_IRAM_RESET_HANDLER_SIZE);
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memcpy(iram_base, (void *)__tegra_cpu_reset_handler_start,
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tegra_cpu_reset_handler_size);
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err = call_firmware_op(set_cpu_boot_addr, 0, reset_address);
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switch (err) {
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case -ENOSYS:
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tegra_cpu_reset_handler_set(reset_address);
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/* pass-through */
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case 0:
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is_enabled = true;
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break;
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default:
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pr_crit("Cannot set CPU reset handler: %d\n", err);
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BUG();
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}
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}
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void __init tegra_cpu_reset_handler_init(void)
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{
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#ifdef CONFIG_SMP
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__tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_PRESENT] =
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*((u32 *)cpu_possible_mask);
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__tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_SECONDARY] =
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virt_to_phys((void *)secondary_startup);
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#endif
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#ifdef CONFIG_PM_SLEEP
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__tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_LP1] =
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TEGRA_IRAM_LPx_RESUME_AREA;
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__tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_LP2] =
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virt_to_phys((void *)tegra_resume);
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#endif
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tegra_cpu_reset_handler_enable();
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}
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