4aa705b18b
Our SoC branch usually contains expanded support for new SoCs and other core platform code. Some highlights from this round: - sunxi: SMP support for A23 SoC - socpga: big-endian support - pxa: conversion to common clock framework - bcm: SMP support for BCM63138 - imx: support new I.MX7D SoC - zte: basic support for ZX296702 SoC Conflicts: arch/arm/mach-socfpga/core.h Trivial remove/remove conflict with our cleanup branch. Resolution: remove both sides -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJVi4RMAAoJEFk3GJrT+8Zl6/kP/1Rv9O++1Kxua6R54Og6AF1J 0miFr2fnUrUWUYg/NVbseRH5bBe6N6ir3SQMfde8W2/QibEjOoEwSwrle+mC/eiq CE0x0gtyRvXMrMU/FWkOvbmmw9uv5oz1z3IHZV6AiecNuSMLUBPfamryikQ8C+d1 O/QZtX543tJQJDOBihO5cuhoVVM37UX0unNmqGsyswlyqTPF8FxcIJAYVNtnxjmj AFaOB0nDJKLKFTiX2Ype2wOxxJX1lrLatNo4W4T+YaaK+i1uCOhgTdSN+n49K7YA KNDFEgZFQqT8VMJyG+eJVeYF+cI7yWQ7lBzIftPUjPk/7+dIHBjWPz2QdjVz3U38 kxncf4S9xGAF5G2rcKe4mFrfT3Y8QLWQpA/jFs06yLwW1O3Hlfq3DzMdGNcF7hth 17LOP8namn9+NepZEp/vAlFzRRypxWWtbkPNBIItkImC6zn0IiGjBy50DE1io27W hmQcnMb7d+0wWl2Y8OmR2lZSB97JiRZkRYMCVHVt+0zGJzp4prLvl9wbjh1VXkPv ERCDJ9nCmZsl7ZVmIXMI7KNXYuPNp7R/QAzCvuSUueswF0qxTAQ0VSSBwRMqvQsQ UUNC6p63VnjUeMUdn2EBsUQZ0Uqw3t2U5TtvooHNt9FkiGsSpwjWrvVD+LItaPoJ GPeeJrJaYQsDvTrO8wjU =ZtPK -----END PGP SIGNATURE----- Merge tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC platform support updates from Kevin Hilman: "Our SoC branch usually contains expanded support for new SoCs and other core platform code. Some highlights from this round: - sunxi: SMP support for A23 SoC - socpga: big-endian support - pxa: conversion to common clock framework - bcm: SMP support for BCM63138 - imx: support new I.MX7D SoC - zte: basic support for ZX296702 SoC" * tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (134 commits) ARM: zx: Add basic defconfig support for ZX296702 ARM: dts: zx: add an initial zx296702 dts and doc clk: zx: add clock support to zx296702 dt-bindings: Add #defines for ZTE ZX296702 clocks ARM: socfpga: fix build error due to secondary_startup MAINTAINERS: ARM64: EXYNOS: Extend entry for ARM64 DTS ARM: ep93xx: simone: support for SPI-based MMC/SD cards MAINTAINERS: update Shawn's email to use kernel.org one ARM: socfpga: support suspend to ram ARM: socfpga: add CPU_METHOD_OF_DECLARE for Arria 10 ARM: socfpga: use CPU_METHOD_OF_DECLARE for socfpga_cyclone5 ARM: EXYNOS: register power domain driver from core_initcall ARM: EXYNOS: use PS_HOLD based poweroff for all supported SoCs ARM: SAMSUNG: Constify platform_device_id ARM: EXYNOS: Constify irq_domain_ops ARM: EXYNOS: add coupled cpuidle support for Exynos3250 ARM: EXYNOS: add exynos_get_boot_addr() helper ARM: EXYNOS: add exynos_set_boot_addr() helper ARM: EXYNOS: make exynos_core_restart() less verbose ARM: EXYNOS: fix exynos_boot_secondary() return value on timeout ...
67 lines
2 KiB
C
67 lines
2 KiB
C
/*
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* arch/arm/mach-tegra/reset.h
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*
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* CPU reset dispatcher.
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*
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* Copyright (c) 2011, NVIDIA Corporation.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef __MACH_TEGRA_RESET_H
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#define __MACH_TEGRA_RESET_H
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#define TEGRA_RESET_MASK_PRESENT 0
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#define TEGRA_RESET_MASK_LP1 1
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#define TEGRA_RESET_MASK_LP2 2
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#define TEGRA_RESET_STARTUP_SECONDARY 3
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#define TEGRA_RESET_STARTUP_LP2 4
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#define TEGRA_RESET_STARTUP_LP1 5
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#define TEGRA_RESET_DATA_SIZE 6
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#ifndef __ASSEMBLY__
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#include "irammap.h"
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extern unsigned long __tegra_cpu_reset_handler_data[TEGRA_RESET_DATA_SIZE];
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void __tegra_cpu_reset_handler_start(void);
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void __tegra_cpu_reset_handler(void);
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void __tegra20_cpu1_resettable_status_offset(void);
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void __tegra_cpu_reset_handler_end(void);
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#ifdef CONFIG_PM_SLEEP
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#define tegra_cpu_lp1_mask \
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(IO_ADDRESS(TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET + \
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((u32)&__tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_LP1] - \
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(u32)__tegra_cpu_reset_handler_start)))
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#define tegra_cpu_lp2_mask \
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(IO_ADDRESS(TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET + \
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((u32)&__tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_LP2] - \
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(u32)__tegra_cpu_reset_handler_start)))
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#define tegra20_cpu1_resettable_status \
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(IO_ADDRESS(TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET + \
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(u32)__tegra20_cpu1_resettable_status_offset))
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#endif
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#define tegra_cpu_reset_handler_offset \
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((u32)__tegra_cpu_reset_handler - \
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(u32)__tegra_cpu_reset_handler_start)
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#define tegra_cpu_reset_handler_size \
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(__tegra_cpu_reset_handler_end - \
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__tegra_cpu_reset_handler_start)
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void __init tegra_cpu_reset_handler_init(void);
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#endif
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#endif
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