602 lines
14 KiB
C
602 lines
14 KiB
C
/**
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* @file bd7181x.h ROHM BD71815GW/BD71817GW header file
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*
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* Copyright 2014 Embest Technology Co. Ltd. Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* @author yanglsh@embest-tech.com
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*/
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#ifndef __LINUX_MFD_BD7181X_H
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#define __LINUX_MFD_BD7181X_H
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#include <linux/regmap.h>
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// LDO5VSEL_EQ_H
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// define to 1 when LDO5VSEL connect to High
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// define to 0 when LDO5VSEL connect to Low
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#define LDO5VSEL_EQ_H 1
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#ifndef LDO5VSEL_EQ_H
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#error define LDO5VSEL_EQ_H to 1 when connect to High, to 0 when connect to Low
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#else
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#if LDO5VSEL_EQ_H == 1
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#define BD7181X_REG_LDO5_VOLT BD7181X_REG_LDO5_VOLT_H
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#elif LDO5VSEL_EQ_H == 0
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#define BD7181X_REG_LDO5_VOLT BD7181X_REG_LDO5_VOLT_L
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#else
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#error Define LDO5VSEL_EQ_H only to 0 or 1
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#endif
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#endif
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enum {
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BD7181X_BUCK1 = 0,
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BD7181X_BUCK2,
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BD7181X_BUCK3,
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BD7181X_BUCK4,
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BD7181X_BUCK5,
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// General Purpose
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BD7181X_LDO1,
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BD7181X_LDO2,
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BD7181X_LDO3,
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// LDOs for SD Card and SD Card Interface
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BD7181X_LDO4,
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BD7181X_LDO5,
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// LDO for DDR Reference Voltage
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BD7181X_LDODVREF,
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// LDO for Secure Non-Volatile Storage
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// BD7181X_LDOSNVS,
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// LDO for Low-Power State Retention
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BD7181X_LDOLPSR,
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BD7181X_WLED,
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BD7181X_REGULATOR_CNT,
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};
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#define BD7181X_SUPPLY_STATE_ENABLED 0x1
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enum {
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BD7181X_REG_DEVICE = 0,
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BD7181X_REG_PWRCTRL,
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BD7181X_REG_BUCK1_MODE,
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BD7181X_REG_BUCK2_MODE,
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BD7181X_REG_BUCK3_MODE,
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BD7181X_REG_BUCK4_MODE,
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BD7181X_REG_BUCK5_MODE,
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BD7181X_REG_BUCK1_VOLT_H,
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// 0x08
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BD7181X_REG_BUCK1_VOLT_L,
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BD7181X_REG_BUCK2_VOLT_H,
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BD7181X_REG_BUCK2_VOLT_L,
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BD7181X_REG_BUCK3_VOLT,
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BD7181X_REG_BUCK4_VOLT,
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BD7181X_REG_BUCK5_VOLT,
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BD7181X_REG_LED_CTRL,
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BD7181X_REG_LED_DIMM,
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// 0x10
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BD7181X_REG_LDO_MODE1,
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BD7181X_REG_LDO_MODE2,
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BD7181X_REG_LDO_MODE3,
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BD7181X_REG_LDO_MODE4,
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BD7181X_REG_LDO1_VOLT,
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BD7181X_REG_LDO2_VOLT,
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BD7181X_REG_LDO3_VOLT,
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BD7181X_REG_LDO4_VOLT,
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// 0x18
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BD7181X_REG_LDO5_VOLT_H,
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BD7181X_REG_LDO5_VOLT_L,
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BD7181X_REG_BUCK_PD_DIS,
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BD7181X_REG_LDO_PD_DIS,
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BD7181X_REG_GPO,
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BD7181X_REG_OUT32K,
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BD7181X_REG_SEC,
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BD7181X_REG_MIN,
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// 0x20
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BD7181X_REG_HOUR,
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BD7181X_REG_WEEK,
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BD7181X_REG_DAY,
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BD7181X_REG_MONTH,
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BD7181X_REG_YEAR,
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BD7181X_REG_ALM0_SEC,
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// 0x2C
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BD7181X_REG_ALM1_SEC = 0x2C,
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// 0x33
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BD7181X_REG_ALM0_MASK = 0x33,
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BD7181X_REG_ALM1_MASK,
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BD7181X_REG_ALM2,
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BD7181X_REG_TRIM,
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BD7181X_REG_CONF,
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// 0x38
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BD7181X_REG_SYS_INIT,
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BD7181X_REG_CHG_STATE,
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BD7181X_REG_CHG_LAST_STATE,
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BD7181X_REG_BAT_STAT,
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BD7181X_REG_DCIN_STAT,
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BD7181X_REG_VSYS_STAT,
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BD7181X_REG_CHG_STAT,
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BD7181X_REG_CHG_WDT_STAT,
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// 0x40
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BD7181X_REG_BAT_TEMP,
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BD7181X_REG_IGNORE_0,
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BD7181X_REG_INHIBIT_0,
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BD7181X_REG_DCIN_CLPS,
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BD7181X_REG_VSYS_REG,
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BD7181X_REG_VSYS_MAX,
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BD7181X_REG_VSYS_MIN,
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BD7181X_REG_CHG_SET1,
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// 0x48
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BD7181X_REG_CHG_SET2,
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BD7181X_REG_CHG_WDT_PRE,
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BD7181X_REG_CHG_WDT_FST,
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BD7181X_REG_CHG_IPRE,
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BD7181X_REG_CHG_IFST,
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BD7181X_REG_CHG_IFST_TERM,
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BD7181X_REG_CHG_VPRE,
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BD7181X_REG_CHG_VBAT_1,
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// 0x50
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BD7181X_REG_CHG_VBAT_2,
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BD7181X_REG_CHG_VBAT_3,
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BD7181X_REG_CHG_LED_1,
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BD7181X_REG_VF_TH,
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BD7181X_REG_BAT_SET_1,
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BD7181X_REG_BAT_SET_2,
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BD7181X_REG_BAT_SET_3,
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BD7181X_REG_ALM_VBAT_TH_U,
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// 0x58
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BD7181X_REG_ALM_VBAT_TH_L,
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BD7181X_REG_ALM_DCIN_TH,
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BD7181X_REG_ALM_VSYS_TH,
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BD7181X_REG_VM_IBAT_U,
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BD7181X_REG_VM_IBAT_L,
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BD7181X_REG_VM_VBAT_U,
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BD7181X_REG_VM_VBAT_L,
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BD7181X_REG_VM_BTMP,
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// 0x60
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BD7181X_REG_VM_VTH,
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BD7181X_REG_VM_DCIN_U,
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BD7181X_REG_VM_DCIN_L,
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BD7181X_REG_VM_VSYS,
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BD7181X_REG_VM_VF,
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BD7181X_REG_VM_OCI_PRE_U,
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BD7181X_REG_VM_OCI_PRE_L,
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BD7181X_REG_VM_OCV_PRE_U,
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// 0x68
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BD7181X_REG_VM_OCV_PRE_L,
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BD7181X_REG_VM_OCI_PST_U,
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BD7181X_REG_VM_OCI_PST_L,
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BD7181X_REG_VM_OCV_PST_U,
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BD7181X_REG_VM_OCV_PST_L,
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BD7181X_REG_VM_SA_VBAT_U,
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BD7181X_REG_VM_SA_VBAT_L,
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BD7181X_REG_VM_SA_IBAT_U,
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// 0x70
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BD7181X_REG_VM_SA_IBAT_L,
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BD7181X_REG_CC_CTRL,
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BD7181X_REG_CC_BATCAP1_TH_U,
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BD7181X_REG_CC_BATCAP1_TH_L,
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BD7181X_REG_CC_BATCAP2_TH_U,
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BD7181X_REG_CC_BATCAP2_TH_L,
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BD7181X_REG_CC_BATCAP3_TH_U,
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BD7181X_REG_CC_BATCAP3_TH_L,
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// 0x78
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BD7181X_REG_CC_STAT,
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BD7181X_REG_CC_CCNTD_3,
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BD7181X_REG_CC_CCNTD_2,
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BD7181X_REG_CC_CCNTD_1,
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BD7181X_REG_CC_CCNTD_0,
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BD7181X_REG_CC_CURCD_U,
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BD7181X_REG_CC_CURCD_L,
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BD7181X_REG_VM_OCUR_THR_1,
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// 0x80
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BD7181X_REG_VM_OCUR_DUR_1,
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BD7181X_REG_VM_OCUR_THR_2,
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BD7181X_REG_VM_OCUR_DUR_2,
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BD7181X_REG_VM_OCUR_THR_3,
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BD7181X_REG_VM_OCUR_DUR_3,
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BD7181X_REG_VM_OCUR_MON,
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BD7181X_REG_VM_BTMP_OV_THR,
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BD7181X_REG_VM_BTMP_OV_DUR,
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// 0x88
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BD7181X_REG_VM_BTMP_LO_THR,
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BD7181X_REG_VM_BTMP_LO_DUR,
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BD7181X_REG_VM_BTMP_MON,
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BD7181X_REG_INT_EN_01,
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// 0x95
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BD7181X_REG_INT_EN_11 = 0x95,
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// 0x96
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BD7181X_REG_INT_EN_12 = 0x96,
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BD7181X_REG_INT_STAT,
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// 0x98
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BD7181X_REG_INT_STAT_01,
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BD7181X_REG_INT_STAT_02,
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BD7181X_REG_INT_STAT_03,
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BD7181X_REG_INT_STAT_04,
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BD7181X_REG_INT_STAT_05,
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BD7181X_REG_INT_STAT_06,
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BD7181X_REG_INT_STAT_07,
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BD7181X_REG_INT_STAT_08,
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// 0xA0
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BD7181X_REG_INT_STAT_09,
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BD7181X_REG_INT_STAT_10,
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BD7181X_REG_INT_STAT_11,
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BD7181X_REG_INT_STAT_12,
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BD7181X_REG_INT_UPDATE,
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// 0xC0
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BD7181X_REG_VM_VSYS_U = 0xC0,
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BD7181X_REG_VM_VSYS_L,
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BD7181X_REG_VM_SA_VSYS_U,
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BD7181X_REG_VM_SA_VSYS_L,
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// 0xD0
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BD7181X_REG_VM_SA_IBAT_MIN_U = 0xD0,
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BD7181X_REG_VM_SA_IBAT_MIN_L,
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BD7181X_REG_VM_SA_IBAT_MAX_U,
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BD7181X_REG_VM_SA_IBAT_MAX_L,
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BD7181X_REG_VM_SA_VBAT_MIN_U,
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BD7181X_REG_VM_SA_VBAT_MIN_L,
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BD7181X_REG_VM_SA_VBAT_MAX_U,
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BD7181X_REG_VM_SA_VBAT_MAX_L,
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BD7181X_REG_VM_SA_VSYS_MIN_U,
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BD7181X_REG_VM_SA_VSYS_MIN_L,
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BD7181X_REG_VM_SA_VSYS_MAX_U,
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BD7181X_REG_VM_SA_VSYS_MAX_L,
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BD7181X_REG_VM_SA_MINMAX_CLR,
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// 0xE0
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BD7181X_REG_REX_CCNTD_3 = 0xE0,
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BD7181X_REG_REX_CCNTD_2,
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BD7181X_REG_REX_CCNTD_1,
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BD7181X_REG_REX_CCNTD_0,
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BD7181X_REG_REX_SA_VBAT_U,
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BD7181X_REG_REX_SA_VBAT_L,
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BD7181X_REG_REX_CTRL_1,
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BD7181X_REG_REX_CTRL_2,
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BD7181X_REG_FULL_CCNTD_3,
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BD7181X_REG_FULL_CCNTD_2,
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BD7181X_REG_FULL_CCNTD_1,
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BD7181X_REG_FULL_CCNTD_0,
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BD7181X_REG_FULL_CTRL,
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// 0xF0
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BD7181X_REG_CCNTD_CHG_3 = 0xF0,
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BD7181X_REG_CCNTD_CHG_2,
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// 0xFE
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BD7181X_REG_TEST_MODE = 0xFE,
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BD7181X_MAX_REGISTER,
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};
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/* BD7181X_REG_BUCK1_MODE bits */
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#define BUCK1_RAMPRATE_MASK 0xC0
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#define BUCK1_RAMPRATE_10P00MV 0x0
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#define BUCK1_RAMPRATE_5P00MV 0x1
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#define BUCK1_RAMPRATE_2P50MV 0x2
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#define BUCK1_RAMPRATE_1P25MV 0x3
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/* BD7181X_REG_BUCK1_VOLT_H bits */
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#define BUCK1_DVSSEL 0x80
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#define BUCK1_STBY_DVS 0x40
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#define BUCK1_H_MASK 0x3F
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#define BUCK1_H_DEFAULT 0x14
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/* BD7181X_REG_BUCK1_VOLT_L bits */
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#define BUCK1_L_MASK 0x3F
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#define BUCK1_L_DEFAULT 0x14
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/* BD7181X_REG_BUCK2_VOLT_H bits */
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#define BUCK2_DVSSEL 0x80
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#define BUCK2_STBY_DVS 0x40
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#define BUCK2_H_MASK 0x3F
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#define BUCK2_H_DEFAULT 0x14
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/* BD7181X_REG_BUCK2_VOLT_L bits */
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#define BUCK2_L_MASK 0x3F
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#define BUCK2_L_DEFAULT 0x14
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/* BD7181X_REG_LDO1_CTRL bits */
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#define LDO1_EN 0x01
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#define LDO2_EN 0x02
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#define LDO3_EN 0x04
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#define DVREF_EN 0x08
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#define VOSNVS_SW_EN 0x10
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#define VOLT_MASK 0x3F
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/* BD7181X_REG_OUT32K bits */
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#define OUT32K_EN 0x01
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#define OUT32K_MODE 0x02
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/* BD7181X_REG_BAT_STAT bits */
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#define BAT_DET 0x20
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#define BAT_DET_OFFSET 5
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#define BAT_DET_DONE 0x10
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#define VBAT_OV 0x08
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#define DBAT_DET 0x01
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/* BD7181X_REG_VBUS_STAT bits */
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#define VBUS_DET 0x01
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#define BUCK1_RAMPRATE_10MV_US 0x0
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#define BUCK1_RAMPRATE_5MV_US 0x1
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#define BUCK1_RAMPRATE_2P5MV_US 0x2
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#define BUCK1_RAMPRATE_1P25MV_US 0x3a
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/* BD7181X_REG_ALM0_MASK bits */
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#define A0_ONESEC 0x80
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/* BD7181X_REG_INT_EN_00 bits */
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#define ALMALE 0x1
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/* BD7181X_REG_INT_STAT_03 bits */
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#define DCIN_MON_DET 0x02
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#define DCIN_MON_RES 0x01
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#define POWERON_LONG 0x04
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#define POWERON_MID 0x08
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#define POWERON_SHORT 0x10
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#define POWERON_PRESS 0x20
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/* BD71805_REG_INT_STAT_08 bits */
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#define VBAT_MON_DET 0x02
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#define VBAT_MON_RES 0x01
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/* BD71805_REG_INT_STAT_11 bits */
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#define INT_STAT_11_VF_DET 0x80
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#define INT_STAT_11_VF_RES 0x40
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#define INT_STAT_11_VF125_DET 0x20
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#define INT_STAT_11_VF125_RES 0x10
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#define INT_STAT_11_OVTMP_DET 0x08
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#define INT_STAT_11_OVTMP_RES 0x04
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#define INT_STAT_11_LOTMP_DET 0x02
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#define INT_STAT_11_LOTMP_RES 0x01
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#define VBAT_MON_DET 0x02
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#define VBAT_MON_RES 0x01
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/* BD7181X_REG_PWRCTRL bits */
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#define RESTARTEN 0x01
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/* BD7181X_REG_GPO bits */
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#define READY_FORCE_LOW 0x04
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/* BD7181X_REG_CHG_SET1 bits */
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#define CHG_EN 0x01
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/* BD7181X interrupt masks */
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enum {
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BD7181X_INT_EN_01_BUCKAST_MASK = 0x0F,
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BD7181X_INT_EN_02_DCINAST_MASK = 0x3E,
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BD7181X_INT_EN_03_DCINAST_MASK = 0x3F,
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BD7181X_INT_EN_04_VSYSAST_MASK = 0xCF,
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BD7181X_INT_EN_05_CHGAST_MASK = 0xFC,
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BD7181X_INT_EN_06_BATAST_MASK = 0xF3,
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BD7181X_INT_EN_07_BMONAST_MASK = 0xFE,
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BD7181X_INT_EN_08_BMONAST_MASK = 0x03,
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BD7181X_INT_EN_09_BMONAST_MASK = 0x07,
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BD7181X_INT_EN_10_BMONAST_MASK = 0x3F,
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BD7181X_INT_EN_11_TMPAST_MASK = 0xFF,
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BD7181X_INT_EN_12_ALMAST_MASK = 0x07,
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};
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/* BD7181X interrupt irqs */
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enum {
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BD7181X_IRQ_BUCK_01 = 0x0,
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BD7181X_IRQ_DCIN_02,
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BD7181X_IRQ_DCIN_03,
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BD7181X_IRQ_VSYS_04,
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BD7181X_IRQ_CHARGE_05,
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BD7181X_IRQ_BAT_06,
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BD7181X_IRQ_BAT_MON_07,
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BD7181X_IRQ_BAT_MON_08,
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BD7181X_IRQ_BAT_MON_09,
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BD7181X_IRQ_BAT_MON_10,
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BD7181X_IRQ_TEMPERATURE_11,
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BD7181X_IRQ_ALARM_12,
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};
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/* BD7181X_REG_INT_EN_12 bits */
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#define ALM0 0x1
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/* BD7181X_REG_HOUR bits */
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#define HOUR_24HOUR 0x80
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/* BD7181X_REG_CC_CTRL bits */
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#define CCNTRST 0x80
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#define CCNTENB 0x40
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#define CCCALIB 0x20
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/* BD7181X_REG_CHG_SET1 bits */
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#define WDT_AUTO 0x40
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/* BD7181X_REG_CC_CURCD */
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#define CURDIR_Discharging 0x8000
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/* BD7181X_REG_VM_SA_IBAT */
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#define IBAT_SA_DIR_Discharging 0x8000
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/* BD7181X_REG_VM_SA_MINMAX_CLR bits */
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#define VSYS_SA_MIN_CLR 0x10
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#define VBAT_SA_MIN_CLR 0x01
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/* BD7181X_REG_REX_CTRL_1 bits */
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#define REX_CLR 0x10
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/* BD7181X_REG_REX_CTRL_1 bits */
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#define REX_PMU_STATE_MASK 0x04
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/* BD7181X_REG_FULL_CTRL bits */
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#define FULL_CLR 0x10
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/* BD7181X_REG_LED_CTRL bits */
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#define CHGDONE_LED_EN 0x10
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/** @brief charge state enumuration */
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enum CHG_STATE {
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CHG_STATE_SUSPEND = 0x0, /**< suspend state */
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CHG_STATE_TRICKLE_CHARGE, /**< trickle charge state */
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CHG_STATE_PRE_CHARGE, /**< precharge state */
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CHG_STATE_FAST_CHARGE, /**< fast charge state */
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CHG_STATE_TOP_OFF, /**< top off state */
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CHG_STATE_DONE, /**< charge complete */
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};
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/** @brief rtc or alarm registers structure */
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struct bd7181x_rtc_alarm {
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u8 sec;
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u8 min;
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u8 hour;
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u8 week;
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u8 day;
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u8 month;
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u8 year;
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};
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struct bd7181x;
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/**
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* @brief Board platform data may be used to initialize regulators.
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*/
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struct bd7181x_board {
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struct regulator_init_data *init_data[BD7181X_REGULATOR_CNT];
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/**< regulator initialize data */
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int gpio_intr; /**< gpio connected to bd7181x INTB */
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int irq_base; /**< bd7181x sub irqs base # */
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};
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/**
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* @brief bd7181x sub-driver chip access routines
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*/
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struct bd7181x {
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struct device *dev;
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struct i2c_client *i2c_client;
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struct regmap *regmap;
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struct mutex io_mutex;
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unsigned int id;
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/* IRQ Handling */
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int chip_irq; /**< bd7181x irq to host cpu */
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struct regmap_irq_chip_data *irq_data;
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/* Client devices */
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struct bd7181x_pmic *pmic; /**< client device regulator */
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struct bd7181x_power *power; /**< client device battery */
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struct bd7181x_board *of_plat_data;
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/**< Device node parsed board data */
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};
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static inline int bd7181x_chip_id(struct bd7181x *bd7181x)
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{
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return bd7181x->id;
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}
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/**
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* @brief bd7181x_reg_read
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* read single register's value of bd7181x
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* @param bd7181x device to read
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* @param reg register address
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* @return register value if success
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* error number if fail
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*/
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static inline int bd7181x_reg_read(struct bd7181x *bd7181x, u8 reg)
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{
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int r, val;
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r = regmap_read(bd7181x->regmap, reg, &val);
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if (r < 0) {
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return r;
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}
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return val;
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}
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/**
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* @brief bd7181x_reg_write
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* write single register of bd7181x
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* @param bd7181x device to write
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* @param reg register address
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* @param val value to write
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* @retval 0 if success
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* @retval negative error number if fail
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*/
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static inline int bd7181x_reg_write(struct bd7181x *bd7181x, u8 reg,
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unsigned int val)
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{
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return regmap_write(bd7181x->regmap, reg, val);
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}
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/**
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* @brief bd7181x_set_bits
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* set bits in one register of bd7181x
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* @param bd7181x device to read
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* @param reg register address
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* @param mask mask bits
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* @retval 0 if success
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* @retval negative error number if fail
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*/
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static inline int bd7181x_set_bits(struct bd7181x *bd7181x, u8 reg,
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u8 mask)
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{
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return regmap_update_bits(bd7181x->regmap, reg, mask, mask);
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}
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/**
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* @brief bd7181x_clear_bits
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* clear bits in one register of bd7181x
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* @param bd7181x device to read
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* @param reg register address
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* @param mask mask bits
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* @retval 0 if success
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* @retval negative error number if fail
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*/
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static inline int bd7181x_clear_bits(struct bd7181x *bd7181x, u8 reg,
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u8 mask)
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{
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return regmap_update_bits(bd7181x->regmap, reg, mask, 0);
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}
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/**
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* @brief bd7181x_update_bits
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* update bits in one register of bd7181x
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* @param bd7181x device to read
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* @param reg register address
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* @param mask mask bits
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* @param val value to update
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* @retval 0 if success
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* @retval negative error number if fail
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*/
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static inline int bd7181x_update_bits(struct bd7181x *bd7181x, u8 reg,
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u8 mask, u8 val)
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{
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return regmap_update_bits(bd7181x->regmap, reg, mask, val);
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}
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|
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/**
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* @brief bd7181x platform data type
|
|
*/
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struct bd7181x_gpo_plat_data {
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u32 mode; ///< gpo output mode
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|
int gpio_base; ///< base gpio number in system
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|
};
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|
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#define BD7181X_DBG0 0x0001
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#define BD7181X_DBG1 0x0002
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#define BD7181X_DBG2 0x0004
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#define BD7181X_DBG3 0x0008
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extern unsigned int bd7181x_debug_mask;
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#define bd7181x_debug(debug, fmt, arg...) do { if(debug & bd7181x_debug_mask) printk("BD7181x:" fmt, ##arg);} while(0)
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#endif /* __LINUX_MFD_BD7181X_H */
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