![Daniel Walker](/assets/img/avatar_default.png)
Fixes the following warning, arch/arm/mach-msm/acpuclock-arm11.c:138: warning: 'freq_table' defined but not used when CONFIG_CPU_FREQ_TABLE is not enabled. Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
527 lines
14 KiB
C
527 lines
14 KiB
C
/* arch/arm/mach-msm/acpuclock.c
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*
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* MSM architecture clock driver
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*
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* Copyright (C) 2007 Google, Inc.
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* Copyright (c) 2007 QUALCOMM Incorporated
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* Author: San Mehat <san@android.com>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/version.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/list.h>
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#include <linux/errno.h>
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#include <linux/string.h>
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#include <linux/delay.h>
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#include <linux/clk.h>
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#include <linux/cpufreq.h>
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#include <linux/mutex.h>
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#include <linux/io.h>
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#include <mach/board.h>
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#include <mach/msm_iomap.h>
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#include "proc_comm.h"
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#include "acpuclock.h"
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#define A11S_CLK_CNTL_ADDR (MSM_CSR_BASE + 0x100)
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#define A11S_CLK_SEL_ADDR (MSM_CSR_BASE + 0x104)
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#define A11S_VDD_SVS_PLEVEL_ADDR (MSM_CSR_BASE + 0x124)
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/*
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* ARM11 clock configuration for specific ACPU speeds
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*/
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#define ACPU_PLL_TCXO -1
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#define ACPU_PLL_0 0
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#define ACPU_PLL_1 1
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#define ACPU_PLL_2 2
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#define ACPU_PLL_3 3
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#define PERF_SWITCH_DEBUG 0
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#define PERF_SWITCH_STEP_DEBUG 0
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struct clock_state
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{
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struct clkctl_acpu_speed *current_speed;
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struct mutex lock;
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uint32_t acpu_switch_time_us;
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uint32_t max_speed_delta_khz;
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uint32_t vdd_switch_time_us;
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unsigned long power_collapse_khz;
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unsigned long wait_for_irq_khz;
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};
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static struct clk *ebi1_clk;
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static struct clock_state drv_state = { 0 };
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static void __init acpuclk_init(void);
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/* MSM7201A Levels 3-6 all correspond to 1.2V, level 7 corresponds to 1.325V. */
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enum {
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VDD_0 = 0,
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VDD_1 = 1,
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VDD_2 = 2,
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VDD_3 = 3,
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VDD_4 = 3,
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VDD_5 = 3,
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VDD_6 = 3,
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VDD_7 = 7,
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VDD_END
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};
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struct clkctl_acpu_speed {
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unsigned int a11clk_khz;
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int pll;
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unsigned int a11clk_src_sel;
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unsigned int a11clk_src_div;
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unsigned int ahbclk_khz;
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unsigned int ahbclk_div;
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int vdd;
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unsigned int axiclk_khz;
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unsigned long lpj; /* loops_per_jiffy */
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/* Index in acpu_freq_tbl[] for steppings. */
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short down;
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short up;
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};
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/*
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* ACPU speed table. Complete table is shown but certain speeds are commented
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* out to optimized speed switching. Initalize loops_per_jiffy to 0.
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*
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* Table stepping up/down is optimized for 256mhz jumps while staying on the
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* same PLL.
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*/
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#if (0)
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static struct clkctl_acpu_speed acpu_freq_tbl[] = {
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{ 19200, ACPU_PLL_TCXO, 0, 0, 19200, 0, VDD_0, 30720, 0, 0, 8 },
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{ 61440, ACPU_PLL_0, 4, 3, 61440, 0, VDD_0, 30720, 0, 0, 8 },
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{ 81920, ACPU_PLL_0, 4, 2, 40960, 1, VDD_0, 61440, 0, 0, 8 },
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{ 96000, ACPU_PLL_1, 1, 7, 48000, 1, VDD_0, 61440, 0, 0, 9 },
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{ 122880, ACPU_PLL_0, 4, 1, 61440, 1, VDD_3, 61440, 0, 0, 8 },
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{ 128000, ACPU_PLL_1, 1, 5, 64000, 1, VDD_3, 61440, 0, 0, 12 },
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{ 176000, ACPU_PLL_2, 2, 5, 88000, 1, VDD_3, 61440, 0, 0, 11 },
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{ 192000, ACPU_PLL_1, 1, 3, 64000, 2, VDD_3, 61440, 0, 0, 12 },
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{ 245760, ACPU_PLL_0, 4, 0, 81920, 2, VDD_4, 61440, 0, 0, 12 },
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{ 256000, ACPU_PLL_1, 1, 2, 128000, 2, VDD_5, 128000, 0, 0, 12 },
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{ 264000, ACPU_PLL_2, 2, 3, 88000, 2, VDD_5, 128000, 0, 6, 13 },
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{ 352000, ACPU_PLL_2, 2, 2, 88000, 3, VDD_5, 128000, 0, 6, 13 },
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{ 384000, ACPU_PLL_1, 1, 1, 128000, 2, VDD_6, 128000, 0, 5, -1 },
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{ 528000, ACPU_PLL_2, 2, 1, 132000, 3, VDD_7, 128000, 0, 11, -1 },
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
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};
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#else /* Table of freq we currently use. */
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static struct clkctl_acpu_speed acpu_freq_tbl[] = {
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{ 19200, ACPU_PLL_TCXO, 0, 0, 19200, 0, VDD_0, 30720, 0, 0, 4 },
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{ 122880, ACPU_PLL_0, 4, 1, 61440, 1, VDD_3, 61440, 0, 0, 4 },
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{ 128000, ACPU_PLL_1, 1, 5, 64000, 1, VDD_3, 61440, 0, 0, 6 },
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{ 176000, ACPU_PLL_2, 2, 5, 88000, 1, VDD_3, 61440, 0, 0, 5 },
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{ 245760, ACPU_PLL_0, 4, 0, 81920, 2, VDD_4, 61440, 0, 0, 5 },
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{ 352000, ACPU_PLL_2, 2, 2, 88000, 3, VDD_5, 128000, 0, 3, 7 },
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{ 384000, ACPU_PLL_1, 1, 1, 128000, 2, VDD_6, 128000, 0, 2, -1 },
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{ 528000, ACPU_PLL_2, 2, 1, 132000, 3, VDD_7, 128000, 0, 5, -1 },
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
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};
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#endif
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#ifdef CONFIG_CPU_FREQ_TABLE
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static struct cpufreq_frequency_table freq_table[] = {
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{ 0, 122880 },
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{ 1, 128000 },
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{ 2, 245760 },
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{ 3, 384000 },
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{ 4, 528000 },
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{ 5, CPUFREQ_TABLE_END },
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};
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#endif
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static int pc_pll_request(unsigned id, unsigned on)
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{
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int res;
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on = !!on;
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#if PERF_SWITCH_DEBUG
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if (on)
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printk(KERN_DEBUG "Enabling PLL %d\n", id);
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else
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printk(KERN_DEBUG "Disabling PLL %d\n", id);
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#endif
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res = msm_proc_comm(PCOM_CLKCTL_RPC_PLL_REQUEST, &id, &on);
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if (res < 0)
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return res;
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#if PERF_SWITCH_DEBUG
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if (on)
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printk(KERN_DEBUG "PLL %d enabled\n", id);
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else
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printk(KERN_DEBUG "PLL %d disabled\n", id);
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#endif
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return res;
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}
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/*----------------------------------------------------------------------------
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* ARM11 'owned' clock control
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*---------------------------------------------------------------------------*/
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unsigned long acpuclk_power_collapse(void) {
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int ret = acpuclk_get_rate();
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ret *= 1000;
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if (ret > drv_state.power_collapse_khz)
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acpuclk_set_rate(drv_state.power_collapse_khz, 1);
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return ret;
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}
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unsigned long acpuclk_get_wfi_rate(void)
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{
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return drv_state.wait_for_irq_khz;
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}
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unsigned long acpuclk_wait_for_irq(void) {
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int ret = acpuclk_get_rate();
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ret *= 1000;
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if (ret > drv_state.wait_for_irq_khz)
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acpuclk_set_rate(drv_state.wait_for_irq_khz, 1);
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return ret;
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}
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static int acpuclk_set_vdd_level(int vdd)
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{
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uint32_t current_vdd;
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current_vdd = readl(A11S_VDD_SVS_PLEVEL_ADDR) & 0x07;
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#if PERF_SWITCH_DEBUG
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printk(KERN_DEBUG "acpuclock: Switching VDD from %u -> %d\n",
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current_vdd, vdd);
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#endif
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writel((1 << 7) | (vdd << 3), A11S_VDD_SVS_PLEVEL_ADDR);
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udelay(drv_state.vdd_switch_time_us);
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if ((readl(A11S_VDD_SVS_PLEVEL_ADDR) & 0x7) != vdd) {
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#if PERF_SWITCH_DEBUG
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printk(KERN_ERR "acpuclock: VDD set failed\n");
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#endif
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return -EIO;
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}
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#if PERF_SWITCH_DEBUG
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printk(KERN_DEBUG "acpuclock: VDD switched\n");
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#endif
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return 0;
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}
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/* Set proper dividers for the given clock speed. */
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static void acpuclk_set_div(const struct clkctl_acpu_speed *hunt_s) {
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uint32_t reg_clkctl, reg_clksel, clk_div;
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/* AHB_CLK_DIV */
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clk_div = (readl(A11S_CLK_SEL_ADDR) >> 1) & 0x03;
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/*
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* If the new clock divider is higher than the previous, then
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* program the divider before switching the clock
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*/
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if (hunt_s->ahbclk_div > clk_div) {
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reg_clksel = readl(A11S_CLK_SEL_ADDR);
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reg_clksel &= ~(0x3 << 1);
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reg_clksel |= (hunt_s->ahbclk_div << 1);
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writel(reg_clksel, A11S_CLK_SEL_ADDR);
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}
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if ((readl(A11S_CLK_SEL_ADDR) & 0x01) == 0) {
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/* SRC0 */
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/* Program clock source */
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reg_clkctl = readl(A11S_CLK_CNTL_ADDR);
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reg_clkctl &= ~(0x07 << 4);
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reg_clkctl |= (hunt_s->a11clk_src_sel << 4);
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writel(reg_clkctl, A11S_CLK_CNTL_ADDR);
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/* Program clock divider */
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reg_clkctl = readl(A11S_CLK_CNTL_ADDR);
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reg_clkctl &= ~0xf;
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reg_clkctl |= hunt_s->a11clk_src_div;
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writel(reg_clkctl, A11S_CLK_CNTL_ADDR);
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/* Program clock source selection */
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reg_clksel = readl(A11S_CLK_SEL_ADDR);
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reg_clksel |= 1; /* CLK_SEL_SRC1NO == SRC1 */
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writel(reg_clksel, A11S_CLK_SEL_ADDR);
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} else {
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/* SRC1 */
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/* Program clock source */
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reg_clkctl = readl(A11S_CLK_CNTL_ADDR);
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reg_clkctl &= ~(0x07 << 12);
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reg_clkctl |= (hunt_s->a11clk_src_sel << 12);
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writel(reg_clkctl, A11S_CLK_CNTL_ADDR);
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/* Program clock divider */
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reg_clkctl = readl(A11S_CLK_CNTL_ADDR);
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reg_clkctl &= ~(0xf << 8);
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reg_clkctl |= (hunt_s->a11clk_src_div << 8);
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writel(reg_clkctl, A11S_CLK_CNTL_ADDR);
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/* Program clock source selection */
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reg_clksel = readl(A11S_CLK_SEL_ADDR);
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reg_clksel &= ~1; /* CLK_SEL_SRC1NO == SRC0 */
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writel(reg_clksel, A11S_CLK_SEL_ADDR);
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}
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/*
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* If the new clock divider is lower than the previous, then
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* program the divider after switching the clock
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*/
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if (hunt_s->ahbclk_div < clk_div) {
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reg_clksel = readl(A11S_CLK_SEL_ADDR);
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reg_clksel &= ~(0x3 << 1);
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reg_clksel |= (hunt_s->ahbclk_div << 1);
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writel(reg_clksel, A11S_CLK_SEL_ADDR);
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}
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}
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int acpuclk_set_rate(unsigned long rate, int for_power_collapse)
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{
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uint32_t reg_clkctl;
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struct clkctl_acpu_speed *cur_s, *tgt_s, *strt_s;
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int rc = 0;
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unsigned int plls_enabled = 0, pll;
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strt_s = cur_s = drv_state.current_speed;
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WARN_ONCE(cur_s == NULL, "acpuclk_set_rate: not initialized\n");
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if (cur_s == NULL)
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return -ENOENT;
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if (rate == (cur_s->a11clk_khz * 1000))
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return 0;
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for (tgt_s = acpu_freq_tbl; tgt_s->a11clk_khz != 0; tgt_s++) {
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if (tgt_s->a11clk_khz == (rate / 1000))
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break;
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}
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if (tgt_s->a11clk_khz == 0)
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return -EINVAL;
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/* Choose the highest speed speed at or below 'rate' with same PLL. */
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if (for_power_collapse && tgt_s->a11clk_khz < cur_s->a11clk_khz) {
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while (tgt_s->pll != ACPU_PLL_TCXO && tgt_s->pll != cur_s->pll)
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tgt_s--;
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}
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if (strt_s->pll != ACPU_PLL_TCXO)
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plls_enabled |= 1 << strt_s->pll;
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if (!for_power_collapse) {
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mutex_lock(&drv_state.lock);
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if (strt_s->pll != tgt_s->pll && tgt_s->pll != ACPU_PLL_TCXO) {
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rc = pc_pll_request(tgt_s->pll, 1);
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if (rc < 0) {
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pr_err("PLL%d enable failed (%d)\n",
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tgt_s->pll, rc);
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goto out;
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}
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plls_enabled |= 1 << tgt_s->pll;
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}
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/* Increase VDD if needed. */
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if (tgt_s->vdd > cur_s->vdd) {
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if ((rc = acpuclk_set_vdd_level(tgt_s->vdd)) < 0) {
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printk(KERN_ERR "Unable to switch ACPU vdd\n");
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goto out;
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}
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}
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}
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/* Set wait states for CPU inbetween frequency changes */
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reg_clkctl = readl(A11S_CLK_CNTL_ADDR);
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reg_clkctl |= (100 << 16); /* set WT_ST_CNT */
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writel(reg_clkctl, A11S_CLK_CNTL_ADDR);
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#if PERF_SWITCH_DEBUG
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printk(KERN_INFO "acpuclock: Switching from ACPU rate %u -> %u\n",
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strt_s->a11clk_khz * 1000, tgt_s->a11clk_khz * 1000);
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#endif
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while (cur_s != tgt_s) {
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/*
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* Always jump to target freq if within 256mhz, regulardless of
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* PLL. If differnece is greater, use the predefinied
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* steppings in the table.
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*/
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int d = abs((int)(cur_s->a11clk_khz - tgt_s->a11clk_khz));
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if (d > drv_state.max_speed_delta_khz) {
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/* Step up or down depending on target vs current. */
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int clk_index = tgt_s->a11clk_khz > cur_s->a11clk_khz ?
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cur_s->up : cur_s->down;
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if (clk_index < 0) { /* This should not happen. */
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printk(KERN_ERR "cur:%u target: %u\n",
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cur_s->a11clk_khz, tgt_s->a11clk_khz);
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rc = -EINVAL;
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goto out;
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}
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cur_s = &acpu_freq_tbl[clk_index];
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} else {
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cur_s = tgt_s;
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}
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#if PERF_SWITCH_STEP_DEBUG
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printk(KERN_DEBUG "%s: STEP khz = %u, pll = %d\n",
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__FUNCTION__, cur_s->a11clk_khz, cur_s->pll);
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#endif
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if (!for_power_collapse&& cur_s->pll != ACPU_PLL_TCXO
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&& !(plls_enabled & (1 << cur_s->pll))) {
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rc = pc_pll_request(cur_s->pll, 1);
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if (rc < 0) {
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pr_err("PLL%d enable failed (%d)\n",
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cur_s->pll, rc);
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goto out;
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}
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plls_enabled |= 1 << cur_s->pll;
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}
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acpuclk_set_div(cur_s);
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drv_state.current_speed = cur_s;
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/* Re-adjust lpj for the new clock speed. */
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loops_per_jiffy = cur_s->lpj;
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udelay(drv_state.acpu_switch_time_us);
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}
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/* Nothing else to do for power collapse. */
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if (for_power_collapse)
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return 0;
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/* Disable PLLs we are not using anymore. */
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plls_enabled &= ~(1 << tgt_s->pll);
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for (pll = ACPU_PLL_0; pll <= ACPU_PLL_2; pll++)
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if (plls_enabled & (1 << pll)) {
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rc = pc_pll_request(pll, 0);
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if (rc < 0) {
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pr_err("PLL%d disable failed (%d)\n", pll, rc);
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goto out;
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}
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}
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/* Change the AXI bus frequency if we can. */
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if (strt_s->axiclk_khz != tgt_s->axiclk_khz) {
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rc = clk_set_rate(ebi1_clk, tgt_s->axiclk_khz * 1000);
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if (rc < 0)
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pr_err("Setting AXI min rate failed!\n");
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}
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/* Drop VDD level if we can. */
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if (tgt_s->vdd < strt_s->vdd) {
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if (acpuclk_set_vdd_level(tgt_s->vdd) < 0)
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printk(KERN_ERR "acpuclock: Unable to drop ACPU vdd\n");
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}
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#if PERF_SWITCH_DEBUG
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printk(KERN_DEBUG "%s: ACPU speed change complete\n", __FUNCTION__);
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#endif
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out:
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if (!for_power_collapse)
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mutex_unlock(&drv_state.lock);
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return rc;
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}
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static void __init acpuclk_init(void)
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{
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struct clkctl_acpu_speed *speed;
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uint32_t div, sel;
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int rc;
|
|
|
|
/*
|
|
* Determine the rate of ACPU clock
|
|
*/
|
|
|
|
if (!(readl(A11S_CLK_SEL_ADDR) & 0x01)) { /* CLK_SEL_SRC1N0 */
|
|
/* CLK_SRC0_SEL */
|
|
sel = (readl(A11S_CLK_CNTL_ADDR) >> 12) & 0x7;
|
|
/* CLK_SRC0_DIV */
|
|
div = (readl(A11S_CLK_CNTL_ADDR) >> 8) & 0x0f;
|
|
} else {
|
|
/* CLK_SRC1_SEL */
|
|
sel = (readl(A11S_CLK_CNTL_ADDR) >> 4) & 0x07;
|
|
/* CLK_SRC1_DIV */
|
|
div = readl(A11S_CLK_CNTL_ADDR) & 0x0f;
|
|
}
|
|
|
|
for (speed = acpu_freq_tbl; speed->a11clk_khz != 0; speed++) {
|
|
if (speed->a11clk_src_sel == sel
|
|
&& (speed->a11clk_src_div == div))
|
|
break;
|
|
}
|
|
if (speed->a11clk_khz == 0) {
|
|
printk(KERN_WARNING "Warning - ACPU clock reports invalid speed\n");
|
|
return;
|
|
}
|
|
|
|
drv_state.current_speed = speed;
|
|
|
|
rc = clk_set_rate(ebi1_clk, speed->axiclk_khz * 1000);
|
|
if (rc < 0)
|
|
pr_err("Setting AXI min rate failed!\n");
|
|
|
|
printk(KERN_INFO "ACPU running at %d KHz\n", speed->a11clk_khz);
|
|
}
|
|
|
|
unsigned long acpuclk_get_rate(void)
|
|
{
|
|
WARN_ONCE(drv_state.current_speed == NULL,
|
|
"acpuclk_get_rate: not initialized\n");
|
|
if (drv_state.current_speed)
|
|
return drv_state.current_speed->a11clk_khz;
|
|
else
|
|
return 0;
|
|
}
|
|
|
|
uint32_t acpuclk_get_switch_time(void)
|
|
{
|
|
return drv_state.acpu_switch_time_us;
|
|
}
|
|
|
|
/*----------------------------------------------------------------------------
|
|
* Clock driver initialization
|
|
*---------------------------------------------------------------------------*/
|
|
|
|
/* Initalize the lpj field in the acpu_freq_tbl. */
|
|
static void __init lpj_init(void)
|
|
{
|
|
int i;
|
|
const struct clkctl_acpu_speed *base_clk = drv_state.current_speed;
|
|
for (i = 0; acpu_freq_tbl[i].a11clk_khz; i++) {
|
|
acpu_freq_tbl[i].lpj = cpufreq_scale(loops_per_jiffy,
|
|
base_clk->a11clk_khz,
|
|
acpu_freq_tbl[i].a11clk_khz);
|
|
}
|
|
}
|
|
|
|
void __init msm_acpu_clock_init(struct msm_acpu_clock_platform_data *clkdata)
|
|
{
|
|
pr_info("acpu_clock_init()\n");
|
|
|
|
ebi1_clk = clk_get(NULL, "ebi1_clk");
|
|
|
|
mutex_init(&drv_state.lock);
|
|
drv_state.acpu_switch_time_us = clkdata->acpu_switch_time_us;
|
|
drv_state.max_speed_delta_khz = clkdata->max_speed_delta_khz;
|
|
drv_state.vdd_switch_time_us = clkdata->vdd_switch_time_us;
|
|
drv_state.power_collapse_khz = clkdata->power_collapse_khz;
|
|
drv_state.wait_for_irq_khz = clkdata->wait_for_irq_khz;
|
|
acpuclk_init();
|
|
lpj_init();
|
|
#ifdef CONFIG_CPU_FREQ_TABLE
|
|
cpufreq_frequency_table_get_attr(freq_table, smp_processor_id());
|
|
#endif
|
|
}
|