![Uwe Kleine-König](/assets/img/avatar_default.png)
As a consequence registers are now accessed with __raw_{read,write}[bl]. Signed-off-by: Uwe Kleine-König <ukleinek@informatik.uni-freiburg.de> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
185 lines
4.7 KiB
C
185 lines
4.7 KiB
C
/*
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* arch/arm/mach-ns9xxx/time.c
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*
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* Copyright (C) 2006 by Digi International Inc.
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* All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*/
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#include <linux/jiffies.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/stringify.h>
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#include <linux/clocksource.h>
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#include <linux/clockchips.h>
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#include <asm/arch-ns9xxx/regs-sys.h>
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#include <asm/arch-ns9xxx/clock.h>
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#include <asm/arch-ns9xxx/irqs.h>
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#include <asm/arch/system.h>
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#include "generic.h"
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#define TIMER_CLOCKSOURCE 0
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#define TIMER_CLOCKEVENT 1
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static u32 latch;
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static cycle_t ns9xxx_clocksource_read(void)
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{
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return __raw_readl(SYS_TR(TIMER_CLOCKSOURCE));
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}
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static struct clocksource ns9xxx_clocksource = {
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.name = "ns9xxx-timer" __stringify(TIMER_CLOCKSOURCE),
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.rating = 300,
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.read = ns9xxx_clocksource_read,
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.mask = CLOCKSOURCE_MASK(32),
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.shift = 20,
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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static void ns9xxx_clockevent_setmode(enum clock_event_mode mode,
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struct clock_event_device *clk)
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{
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u32 tc = __raw_readl(SYS_TC(TIMER_CLOCKEVENT));
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switch(mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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__raw_writel(latch, SYS_TRC(TIMER_CLOCKEVENT));
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REGSET(tc, SYS_TCx, REN, EN);
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REGSET(tc, SYS_TCx, INTS, EN);
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REGSET(tc, SYS_TCx, TEN, EN);
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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REGSET(tc, SYS_TCx, REN, DIS);
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REGSET(tc, SYS_TCx, INTS, EN);
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/* fall through */
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case CLOCK_EVT_MODE_UNUSED:
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case CLOCK_EVT_MODE_SHUTDOWN:
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case CLOCK_EVT_MODE_RESUME:
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default:
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REGSET(tc, SYS_TCx, TEN, DIS);
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break;
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}
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__raw_writel(tc, SYS_TC(TIMER_CLOCKEVENT));
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}
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static int ns9xxx_clockevent_setnextevent(unsigned long evt,
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struct clock_event_device *clk)
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{
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u32 tc = __raw_readl(SYS_TC(TIMER_CLOCKEVENT));
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if (REGGET(tc, SYS_TCx, TEN)) {
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REGSET(tc, SYS_TCx, TEN, DIS);
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__raw_writel(tc, SYS_TC(TIMER_CLOCKEVENT));
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}
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REGSET(tc, SYS_TCx, TEN, EN);
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__raw_writel(evt, SYS_TRC(TIMER_CLOCKEVENT));
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__raw_writel(tc, SYS_TC(TIMER_CLOCKEVENT));
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return 0;
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}
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static struct clock_event_device ns9xxx_clockevent_device = {
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.name = "ns9xxx-timer" __stringify(TIMER_CLOCKEVENT),
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.shift = 20,
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.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
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.set_mode = ns9xxx_clockevent_setmode,
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.set_next_event = ns9xxx_clockevent_setnextevent,
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};
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static irqreturn_t ns9xxx_clockevent_handler(int irq, void *dev_id)
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{
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int timerno = irq - IRQ_TIMER0;
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u32 tc;
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struct clock_event_device *evt = &ns9xxx_clockevent_device;
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/* clear irq */
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tc = __raw_readl(SYS_TC(timerno));
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if (REGGET(tc, SYS_TCx, REN) == SYS_TCx_REN_DIS) {
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REGSET(tc, SYS_TCx, TEN, DIS);
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__raw_writel(tc, SYS_TC(timerno));
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}
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REGSET(tc, SYS_TCx, INTC, SET);
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__raw_writel(tc, SYS_TC(timerno));
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REGSET(tc, SYS_TCx, INTC, UNSET);
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__raw_writel(tc, SYS_TC(timerno));
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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static struct irqaction ns9xxx_clockevent_action = {
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.name = "ns9xxx-timer" __stringify(TIMER_CLOCKEVENT),
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.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
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.handler = ns9xxx_clockevent_handler,
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};
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static void __init ns9xxx_timer_init(void)
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{
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int tc;
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tc = __raw_readl(SYS_TC(TIMER_CLOCKSOURCE));
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if (REGGET(tc, SYS_TCx, TEN)) {
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REGSET(tc, SYS_TCx, TEN, DIS);
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__raw_writel(tc, SYS_TC(TIMER_CLOCKSOURCE));
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}
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__raw_writel(0, SYS_TRC(TIMER_CLOCKSOURCE));
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REGSET(tc, SYS_TCx, TEN, EN);
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REGSET(tc, SYS_TCx, TDBG, STOP);
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REGSET(tc, SYS_TCx, TLCS, CPU);
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REGSET(tc, SYS_TCx, TM, IEE);
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REGSET(tc, SYS_TCx, INTS, DIS);
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REGSET(tc, SYS_TCx, UDS, UP);
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REGSET(tc, SYS_TCx, TSZ, 32);
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REGSET(tc, SYS_TCx, REN, EN);
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__raw_writel(tc, SYS_TC(TIMER_CLOCKSOURCE));
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ns9xxx_clocksource.mult = clocksource_hz2mult(ns9xxx_cpuclock(),
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ns9xxx_clocksource.shift);
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clocksource_register(&ns9xxx_clocksource);
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latch = SH_DIV(ns9xxx_cpuclock(), HZ, 0);
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tc = __raw_readl(SYS_TC(TIMER_CLOCKEVENT));
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REGSET(tc, SYS_TCx, TEN, DIS);
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REGSET(tc, SYS_TCx, TDBG, STOP);
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REGSET(tc, SYS_TCx, TLCS, CPU);
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REGSET(tc, SYS_TCx, TM, IEE);
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REGSET(tc, SYS_TCx, INTS, DIS);
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REGSET(tc, SYS_TCx, UDS, DOWN);
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REGSET(tc, SYS_TCx, TSZ, 32);
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REGSET(tc, SYS_TCx, REN, EN);
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__raw_writel(tc, SYS_TC(TIMER_CLOCKEVENT));
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ns9xxx_clockevent_device.mult = div_sc(ns9xxx_cpuclock(),
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NSEC_PER_SEC, ns9xxx_clockevent_device.shift);
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ns9xxx_clockevent_device.max_delta_ns =
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clockevent_delta2ns(-1, &ns9xxx_clockevent_device);
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ns9xxx_clockevent_device.min_delta_ns =
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clockevent_delta2ns(1, &ns9xxx_clockevent_device);
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ns9xxx_clockevent_device.cpumask = cpumask_of_cpu(0);
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clockevents_register_device(&ns9xxx_clockevent_device);
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setup_irq(IRQ_TIMER0 + TIMER_CLOCKEVENT, &ns9xxx_clockevent_action);
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}
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struct sys_timer ns9xxx_timer = {
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.init = ns9xxx_timer_init,
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};
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