![Aaro Koskinen](/assets/img/avatar_default.png)
Refactor RGMII 10 Mbps preamble error checking. The current implementation does not work correctly in phydev mode since only the link status changes trigger the callback, and if we stay on 10 Mbps operation the periodic checks for error counters are never done. Provide a periodic worker also during the phydev operation, and notify the link status changes through the phydev instead of the inband status change interrupt. This also has the benefit that we don't need to use legacy CVMX MDIO calls to check the PHY state, and we can avoid races that trigger bogus "Using 10Mbps with software preamble removal" logs when interfaces are being bringed up. It also avoids some corner-case crashes when the in-band interrupt triggers while the interface is being taken down. Tested on EdgeRouter Lite & D-Link DSR-1000N. Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
167 lines
4.7 KiB
C
167 lines
4.7 KiB
C
/*
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* This file is based on code from OCTEON SDK by Cavium Networks.
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*
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* Copyright (c) 2003-2007 Cavium Networks
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*
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* This file is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, Version 2, as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/netdevice.h>
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#include <linux/interrupt.h>
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#include <linux/phy.h>
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#include <linux/ratelimit.h>
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#include <net/dst.h>
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#include <asm/octeon/octeon.h>
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#include "ethernet-defines.h"
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#include "octeon-ethernet.h"
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#include "ethernet-util.h"
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#include "ethernet-mdio.h"
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#include <asm/octeon/cvmx-helper.h>
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#include <asm/octeon/cvmx-ipd-defs.h>
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#include <asm/octeon/cvmx-npi-defs.h>
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#include <asm/octeon/cvmx-gmxx-defs.h>
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static DEFINE_SPINLOCK(global_register_lock);
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static void cvm_oct_set_hw_preamble(struct octeon_ethernet *priv, bool enable)
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{
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union cvmx_gmxx_rxx_frm_ctl gmxx_rxx_frm_ctl;
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union cvmx_ipd_sub_port_fcs ipd_sub_port_fcs;
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union cvmx_gmxx_rxx_int_reg gmxx_rxx_int_reg;
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int interface = INTERFACE(priv->port);
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int index = INDEX(priv->port);
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/* Set preamble checking. */
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gmxx_rxx_frm_ctl.u64 = cvmx_read_csr(CVMX_GMXX_RXX_FRM_CTL(index,
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interface));
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gmxx_rxx_frm_ctl.s.pre_chk = enable;
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cvmx_write_csr(CVMX_GMXX_RXX_FRM_CTL(index, interface),
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gmxx_rxx_frm_ctl.u64);
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/* Set FCS stripping. */
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ipd_sub_port_fcs.u64 = cvmx_read_csr(CVMX_IPD_SUB_PORT_FCS);
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if (enable)
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ipd_sub_port_fcs.s.port_bit |= 1ull << priv->port;
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else
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ipd_sub_port_fcs.s.port_bit &=
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0xffffffffull ^ (1ull << priv->port);
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cvmx_write_csr(CVMX_IPD_SUB_PORT_FCS, ipd_sub_port_fcs.u64);
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/* Clear any error bits. */
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gmxx_rxx_int_reg.u64 = cvmx_read_csr(CVMX_GMXX_RXX_INT_REG(index,
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interface));
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cvmx_write_csr(CVMX_GMXX_RXX_INT_REG(index, interface),
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gmxx_rxx_int_reg.u64);
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}
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static void cvm_oct_check_preamble_errors(struct net_device *dev)
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{
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struct octeon_ethernet *priv = netdev_priv(dev);
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cvmx_helper_link_info_t link_info;
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unsigned long flags;
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link_info.u64 = priv->link_info;
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/*
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* Take the global register lock since we are going to
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* touch registers that affect more than one port.
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*/
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spin_lock_irqsave(&global_register_lock, flags);
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if (link_info.s.speed == 10 && priv->last_speed == 10) {
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/*
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* Read the GMXX_RXX_INT_REG[PCTERR] bit and see if we are
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* getting preamble errors.
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*/
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int interface = INTERFACE(priv->port);
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int index = INDEX(priv->port);
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union cvmx_gmxx_rxx_int_reg gmxx_rxx_int_reg;
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gmxx_rxx_int_reg.u64 = cvmx_read_csr(CVMX_GMXX_RXX_INT_REG
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(index, interface));
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if (gmxx_rxx_int_reg.s.pcterr) {
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/*
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* We are getting preamble errors at 10Mbps. Most
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* likely the PHY is giving us packets with misaligned
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* preambles. In order to get these packets we need to
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* disable preamble checking and do it in software.
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*/
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cvm_oct_set_hw_preamble(priv, false);
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printk_ratelimited("%s: Using 10Mbps with software preamble removal\n",
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dev->name);
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}
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} else {
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/*
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* Since the 10Mbps preamble workaround is allowed we need to
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* enable preamble checking, FCS stripping, and clear error
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* bits on every speed change. If errors occur during 10Mbps
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* operation the above code will change this stuff
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*/
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if (priv->last_speed != link_info.s.speed)
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cvm_oct_set_hw_preamble(priv, true);
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priv->last_speed = link_info.s.speed;
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}
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spin_unlock_irqrestore(&global_register_lock, flags);
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}
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static void cvm_oct_rgmii_poll(struct net_device *dev)
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{
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struct octeon_ethernet *priv = netdev_priv(dev);
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cvmx_helper_link_info_t link_info;
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bool status_change;
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link_info = cvmx_helper_link_autoconf(priv->port);
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status_change = priv->link_info != link_info.u64;
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priv->link_info = link_info.u64;
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cvm_oct_check_preamble_errors(dev);
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if (likely(!status_change))
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return;
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/* Tell core. */
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if (link_info.s.link_up) {
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if (!netif_carrier_ok(dev))
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netif_carrier_on(dev);
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} else if (netif_carrier_ok(dev)) {
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netif_carrier_off(dev);
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}
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cvm_oct_note_carrier(priv, link_info);
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}
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int cvm_oct_rgmii_open(struct net_device *dev)
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{
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struct octeon_ethernet *priv = netdev_priv(dev);
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int ret;
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ret = cvm_oct_common_open(dev, cvm_oct_rgmii_poll);
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if (ret)
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return ret;
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if (priv->phydev) {
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/*
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* In phydev mode, we need still periodic polling for the
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* preamble error checking, and we also need to call this
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* function on every link state change.
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*
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* Only true RGMII ports need to be polled. In GMII mode, port
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* 0 is really a RGMII port.
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*/
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if ((priv->imode == CVMX_HELPER_INTERFACE_MODE_GMII &&
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priv->port == 0) ||
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(priv->imode == CVMX_HELPER_INTERFACE_MODE_RGMII)) {
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priv->poll = cvm_oct_check_preamble_errors;
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cvm_oct_check_preamble_errors(dev);
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}
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}
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return 0;
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}
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