![Luis de Bethencourt](/assets/img/avatar_default.png)
Clean up all instances of checkpatch.pl checks: CHECK: spaces preferred around that '+' (and other operands) Signed-off-by: Luis de Bethencourt <luisbg@osg.samsung.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
319 lines
12 KiB
C
319 lines
12 KiB
C
/******************************************************************************
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* usb_halinit.c
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*
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* Copyright(c) 2007 - 2010 Realtek Corporation. All rights reserved.
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* Linux device driver for RTL8192SU
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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*
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* Modifications for inclusion into the Linux staging tree are
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* Copyright(c) 2010 Larry Finger. All rights reserved.
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*
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* Contact information:
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* WLAN FAE <wlanfae@realtek.com>
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* Larry Finger <Larry.Finger@lwfinger.net>
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*
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******************************************************************************/
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#define _HCI_HAL_INIT_C_
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#include "osdep_service.h"
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#include "drv_types.h"
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#include "usb_ops.h"
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#include "usb_osintf.h"
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u8 r8712_usb_hal_bus_init(struct _adapter *padapter)
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{
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u8 val8 = 0;
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u8 ret = _SUCCESS;
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int PollingCnt = 20;
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struct registry_priv *pregistrypriv = &padapter->registrypriv;
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if (pregistrypriv->chip_version == RTL8712_FPGA) {
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val8 = 0x01;
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/* switch to 80M clock */
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r8712_write8(padapter, SYS_CLKR, val8);
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val8 = r8712_read8(padapter, SPS1_CTRL);
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val8 = val8 | 0x01;
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/* enable VSPS12 LDO Macro block */
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r8712_write8(padapter, SPS1_CTRL, val8);
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val8 = r8712_read8(padapter, AFE_MISC);
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val8 = val8 | 0x01;
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/* Enable AFE Macro Block's Bandgap */
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r8712_write8(padapter, AFE_MISC, val8);
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val8 = r8712_read8(padapter, LDOA15_CTRL);
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val8 = val8 | 0x01;
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/* enable LDOA15 block */
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r8712_write8(padapter, LDOA15_CTRL, val8);
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val8 = r8712_read8(padapter, SPS1_CTRL);
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val8 = val8 | 0x02;
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/* Enable VSPS12_SW Macro Block */
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r8712_write8(padapter, SPS1_CTRL, val8);
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val8 = r8712_read8(padapter, AFE_MISC);
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val8 = val8 | 0x02;
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/* Enable AFE Macro Block's Mbias */
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r8712_write8(padapter, AFE_MISC, val8);
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val8 = r8712_read8(padapter, SYS_ISO_CTRL + 1);
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val8 = val8 | 0x08;
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/* isolate PCIe Analog 1.2V to PCIe 3.3V and PCIE Digital */
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r8712_write8(padapter, SYS_ISO_CTRL + 1, val8);
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val8 = r8712_read8(padapter, SYS_ISO_CTRL + 1);
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val8 = val8 & 0xEF;
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/* attatch AFE PLL to MACTOP/BB/PCIe Digital */
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r8712_write8(padapter, SYS_ISO_CTRL + 1, val8);
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val8 = r8712_read8(padapter, AFE_XTAL_CTRL + 1);
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val8 = val8 & 0xFB;
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/* enable AFE clock */
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r8712_write8(padapter, AFE_XTAL_CTRL + 1, val8);
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val8 = r8712_read8(padapter, AFE_PLL_CTRL);
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val8 = val8 | 0x01;
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/* Enable AFE PLL Macro Block */
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r8712_write8(padapter, AFE_PLL_CTRL, val8);
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val8 = 0xEE;
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/* release isolation AFE PLL & MD */
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r8712_write8(padapter, SYS_ISO_CTRL, val8);
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val8 = r8712_read8(padapter, SYS_CLKR + 1);
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val8 = val8 | 0x08;
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/* enable MAC clock */
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r8712_write8(padapter, SYS_CLKR + 1, val8);
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val8 = r8712_read8(padapter, SYS_FUNC_EN + 1);
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val8 = val8 | 0x08;
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/* enable Core digital and enable IOREG R/W */
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r8712_write8(padapter, SYS_FUNC_EN + 1, val8);
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val8 = val8 | 0x80;
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/* enable REG_EN */
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r8712_write8(padapter, SYS_FUNC_EN + 1, val8);
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val8 = r8712_read8(padapter, SYS_CLKR + 1);
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val8 = (val8 | 0x80) & 0xBF;
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/* switch the control path */
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r8712_write8(padapter, SYS_CLKR + 1, val8);
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val8 = 0xFC;
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r8712_write8(padapter, CR, val8);
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val8 = 0x37;
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r8712_write8(padapter, CR + 1, val8);
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/* reduce EndPoint & init it */
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r8712_write8(padapter, 0x102500ab, r8712_read8(padapter,
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0x102500ab) | BIT(6) | BIT(7));
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/* consideration of power consumption - init */
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r8712_write8(padapter, 0x10250008, r8712_read8(padapter,
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0x10250008) & 0xfffffffb);
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} else if (pregistrypriv->chip_version == RTL8712_1stCUT) {
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/* Initialization for power on sequence, */
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r8712_write8(padapter, SPS0_CTRL + 1, 0x53);
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r8712_write8(padapter, SPS0_CTRL, 0x57);
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/* Enable AFE Macro Block's Bandgap and Enable AFE Macro
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* Block's Mbias
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*/
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val8 = r8712_read8(padapter, AFE_MISC);
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r8712_write8(padapter, AFE_MISC, (val8 | AFE_MISC_BGEN |
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AFE_MISC_MBEN));
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/* Enable LDOA15 block */
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val8 = r8712_read8(padapter, LDOA15_CTRL);
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r8712_write8(padapter, LDOA15_CTRL, (val8 | LDA15_EN));
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val8 = r8712_read8(padapter, SPS1_CTRL);
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r8712_write8(padapter, SPS1_CTRL, (val8 | SPS1_LDEN));
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msleep(20);
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/* Enable Switch Regulator Block */
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val8 = r8712_read8(padapter, SPS1_CTRL);
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r8712_write8(padapter, SPS1_CTRL, (val8 | SPS1_SWEN));
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r8712_write32(padapter, SPS1_CTRL, 0x00a7b267);
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val8 = r8712_read8(padapter, SYS_ISO_CTRL + 1);
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r8712_write8(padapter, SYS_ISO_CTRL + 1, (val8 | 0x08));
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/* Engineer Packet CP test Enable */
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val8 = r8712_read8(padapter, SYS_FUNC_EN + 1);
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r8712_write8(padapter, SYS_FUNC_EN + 1, (val8 | 0x20));
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val8 = r8712_read8(padapter, SYS_ISO_CTRL + 1);
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r8712_write8(padapter, SYS_ISO_CTRL + 1, (val8 & 0x6F));
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/* Enable AFE clock */
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val8 = r8712_read8(padapter, AFE_XTAL_CTRL + 1);
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r8712_write8(padapter, AFE_XTAL_CTRL + 1, (val8 & 0xfb));
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/* Enable AFE PLL Macro Block */
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val8 = r8712_read8(padapter, AFE_PLL_CTRL);
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r8712_write8(padapter, AFE_PLL_CTRL, (val8 | 0x11));
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/* Attach AFE PLL to MACTOP/BB/PCIe Digital */
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val8 = r8712_read8(padapter, SYS_ISO_CTRL);
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r8712_write8(padapter, SYS_ISO_CTRL, (val8 & 0xEE));
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/* Switch to 40M clock */
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val8 = r8712_read8(padapter, SYS_CLKR);
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r8712_write8(padapter, SYS_CLKR, val8 & (~SYS_CLKSEL));
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/* SSC Disable */
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val8 = r8712_read8(padapter, SYS_CLKR);
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/* Enable MAC clock */
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val8 = r8712_read8(padapter, SYS_CLKR + 1);
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r8712_write8(padapter, SYS_CLKR + 1, (val8 | 0x18));
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/* Revised POS, */
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r8712_write8(padapter, PMC_FSM, 0x02);
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/* Enable Core digital and enable IOREG R/W */
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val8 = r8712_read8(padapter, SYS_FUNC_EN + 1);
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r8712_write8(padapter, SYS_FUNC_EN + 1, (val8 | 0x08));
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/* Enable REG_EN */
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val8 = r8712_read8(padapter, SYS_FUNC_EN + 1);
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r8712_write8(padapter, SYS_FUNC_EN + 1, (val8 | 0x80));
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/* Switch the control path to FW */
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val8 = r8712_read8(padapter, SYS_CLKR + 1);
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r8712_write8(padapter, SYS_CLKR + 1, (val8 | 0x80) & 0xBF);
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r8712_write8(padapter, CR, 0xFC);
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r8712_write8(padapter, CR + 1, 0x37);
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/* Fix the RX FIFO issue(usb error), */
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val8 = r8712_read8(padapter, 0x1025FE5c);
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r8712_write8(padapter, 0x1025FE5c, (val8 | BIT(7)));
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val8 = r8712_read8(padapter, 0x102500ab);
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r8712_write8(padapter, 0x102500ab, (val8 | BIT(6) | BIT(7)));
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/* For power save, used this in the bit file after 970621 */
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val8 = r8712_read8(padapter, SYS_CLKR);
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r8712_write8(padapter, SYS_CLKR, val8 & (~CPU_CLKSEL));
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} else if (pregistrypriv->chip_version == RTL8712_2ndCUT ||
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pregistrypriv->chip_version == RTL8712_3rdCUT) {
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/* Initialization for power on sequence,
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* E-Fuse leakage prevention sequence
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*/
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r8712_write8(padapter, 0x37, 0xb0);
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msleep(20);
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r8712_write8(padapter, 0x37, 0x30);
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/* Set control path switch to HW control and reset Digital Core,
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* CPU Core and MAC I/O to solve FW download fail when system
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* from resume sate.
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*/
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val8 = r8712_read8(padapter, SYS_CLKR + 1);
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if (val8 & 0x80) {
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val8 &= 0x3f;
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r8712_write8(padapter, SYS_CLKR + 1, val8);
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}
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val8 = r8712_read8(padapter, SYS_FUNC_EN + 1);
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val8 &= 0x73;
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r8712_write8(padapter, SYS_FUNC_EN + 1, val8);
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msleep(20);
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/* Revised POS, */
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/* Enable AFE Macro Block's Bandgap and Enable AFE Macro
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* Block's Mbias */
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r8712_write8(padapter, SPS0_CTRL + 1, 0x53);
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r8712_write8(padapter, SPS0_CTRL, 0x57);
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val8 = r8712_read8(padapter, AFE_MISC);
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/*Bandgap*/
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r8712_write8(padapter, AFE_MISC, (val8 | AFE_MISC_BGEN));
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r8712_write8(padapter, AFE_MISC, (val8 | AFE_MISC_BGEN |
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AFE_MISC_MBEN | AFE_MISC_I32_EN));
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/* Enable PLL Power (LDOA15V) */
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val8 = r8712_read8(padapter, LDOA15_CTRL);
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r8712_write8(padapter, LDOA15_CTRL, (val8 | LDA15_EN));
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/* Enable LDOV12D block */
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val8 = r8712_read8(padapter, LDOV12D_CTRL);
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r8712_write8(padapter, LDOV12D_CTRL, (val8 | LDV12_EN));
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val8 = r8712_read8(padapter, SYS_ISO_CTRL + 1);
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r8712_write8(padapter, SYS_ISO_CTRL + 1, (val8 | 0x08));
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/* Engineer Packet CP test Enable */
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val8 = r8712_read8(padapter, SYS_FUNC_EN + 1);
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r8712_write8(padapter, SYS_FUNC_EN + 1, (val8 | 0x20));
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/* Support 64k IMEM */
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val8 = r8712_read8(padapter, SYS_ISO_CTRL + 1);
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r8712_write8(padapter, SYS_ISO_CTRL + 1, (val8 & 0x68));
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/* Enable AFE clock */
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val8 = r8712_read8(padapter, AFE_XTAL_CTRL + 1);
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r8712_write8(padapter, AFE_XTAL_CTRL + 1, (val8 & 0xfb));
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/* Enable AFE PLL Macro Block */
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val8 = r8712_read8(padapter, AFE_PLL_CTRL);
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r8712_write8(padapter, AFE_PLL_CTRL, (val8 | 0x11));
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/* Some sample will download fw failure. The clock will be
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* stable with 500 us delay after reset the PLL
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* TODO: When usleep is added to kernel, change next 3
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* udelay(500) to usleep(500)
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*/
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udelay(500);
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r8712_write8(padapter, AFE_PLL_CTRL, (val8 | 0x51));
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udelay(500);
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r8712_write8(padapter, AFE_PLL_CTRL, (val8 | 0x11));
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udelay(500);
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/* Attach AFE PLL to MACTOP/BB/PCIe Digital */
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val8 = r8712_read8(padapter, SYS_ISO_CTRL);
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r8712_write8(padapter, SYS_ISO_CTRL, (val8 & 0xEE));
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/* Switch to 40M clock */
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r8712_write8(padapter, SYS_CLKR, 0x00);
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/* CPU Clock and 80M Clock SSC Disable to overcome FW download
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* fail timing issue.
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*/
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val8 = r8712_read8(padapter, SYS_CLKR);
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r8712_write8(padapter, SYS_CLKR, (val8 | 0xa0));
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/* Enable MAC clock */
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val8 = r8712_read8(padapter, SYS_CLKR + 1);
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r8712_write8(padapter, SYS_CLKR + 1, (val8 | 0x18));
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/* Revised POS, */
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r8712_write8(padapter, PMC_FSM, 0x02);
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/* Enable Core digital and enable IOREG R/W */
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val8 = r8712_read8(padapter, SYS_FUNC_EN + 1);
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r8712_write8(padapter, SYS_FUNC_EN + 1, (val8 | 0x08));
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/* Enable REG_EN */
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val8 = r8712_read8(padapter, SYS_FUNC_EN + 1);
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r8712_write8(padapter, SYS_FUNC_EN + 1, (val8 | 0x80));
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/* Switch the control path to FW */
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val8 = r8712_read8(padapter, SYS_CLKR + 1);
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r8712_write8(padapter, SYS_CLKR + 1, (val8 | 0x80) & 0xBF);
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r8712_write8(padapter, CR, 0xFC);
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r8712_write8(padapter, CR + 1, 0x37);
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/* Fix the RX FIFO issue(usb error), 970410 */
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val8 = r8712_read8(padapter, 0x1025FE5c);
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r8712_write8(padapter, 0x1025FE5c, (val8 | BIT(7)));
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/* For power save, used this in the bit file after 970621 */
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val8 = r8712_read8(padapter, SYS_CLKR);
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r8712_write8(padapter, SYS_CLKR, val8 & (~CPU_CLKSEL));
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/* Revised for 8051 ROM code wrong operation. */
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r8712_write8(padapter, 0x1025fe1c, 0x80);
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/* To make sure that TxDMA can ready to download FW.
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* We should reset TxDMA if IMEM RPT was not ready.
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*/
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do {
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val8 = r8712_read8(padapter, TCR);
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if ((val8 & _TXDMA_INIT_VALUE) == _TXDMA_INIT_VALUE)
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break;
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udelay(5); /* PlatformStallExecution(5); */
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} while (PollingCnt--); /* Delay 1ms */
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if (PollingCnt <= 0) {
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val8 = r8712_read8(padapter, CR);
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r8712_write8(padapter, CR, val8 & (~_TXDMA_EN));
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udelay(2); /* PlatformStallExecution(2); */
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/* Reset TxDMA */
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r8712_write8(padapter, CR, val8 | _TXDMA_EN);
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}
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} else {
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ret = _FAIL;
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}
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return ret;
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}
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unsigned int r8712_usb_inirp_init(struct _adapter *padapter)
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{
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u8 i;
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struct recv_buf *precvbuf;
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struct intf_hdl *pintfhdl = &padapter->pio_queue->intf;
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struct recv_priv *precvpriv = &(padapter->recvpriv);
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precvpriv->ff_hwaddr = RTL8712_DMA_RX0FF; /* mapping rx fifo address */
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/* issue Rx irp to receive data */
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precvbuf = (struct recv_buf *)precvpriv->precv_buf;
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for (i = 0; i < NR_RECVBUFF; i++) {
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if (r8712_usb_read_port(pintfhdl, precvpriv->ff_hwaddr, 0,
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(unsigned char *)precvbuf) == false)
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return _FAIL;
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precvbuf++;
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precvpriv->free_recv_buf_queue_cnt--;
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}
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return _SUCCESS;
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}
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unsigned int r8712_usb_inirp_deinit(struct _adapter *padapter)
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{
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r8712_usb_read_port_cancel(padapter);
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return _SUCCESS;
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}
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