![Thomas Gleixner](/assets/img/avatar_default.png)
timer interrupts are excluded from being disabled during suspend. The clock events code manages the disabling of clock events on its own because the timer interrupt needs to be functional before the resume code reenables the device interrupts. The hpet per cpu timers request their interrupt without setting the IRQF_TIMER flag so suspend_device_irqs() disables them as well which results in a fatal resume failure on the boot CPU. Adding IRQF_TIMER to the interupt flags when requesting the hpet per cpu timer interrupts solves the problem. Reported-by: Benjamin S. <sbenni@gmx.de> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Benjamin S. <sbenni@gmx.de> Cc: stable@kernel.org
1203 lines
27 KiB
C
1203 lines
27 KiB
C
#include <linux/clocksource.h>
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#include <linux/clockchips.h>
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#include <linux/interrupt.h>
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#include <linux/sysdev.h>
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#include <linux/delay.h>
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#include <linux/errno.h>
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#include <linux/hpet.h>
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#include <linux/init.h>
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#include <linux/cpu.h>
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#include <linux/pm.h>
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#include <linux/io.h>
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#include <asm/fixmap.h>
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#include <asm/i8253.h>
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#include <asm/hpet.h>
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#define HPET_MASK CLOCKSOURCE_MASK(32)
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#define HPET_SHIFT 22
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/* FSEC = 10^-15
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NSEC = 10^-9 */
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#define FSEC_PER_NSEC 1000000L
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#define HPET_DEV_USED_BIT 2
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#define HPET_DEV_USED (1 << HPET_DEV_USED_BIT)
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#define HPET_DEV_VALID 0x8
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#define HPET_DEV_FSB_CAP 0x1000
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#define HPET_DEV_PERI_CAP 0x2000
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#define EVT_TO_HPET_DEV(evt) container_of(evt, struct hpet_dev, evt)
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/*
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* HPET address is set in acpi/boot.c, when an ACPI entry exists
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*/
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unsigned long hpet_address;
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#ifdef CONFIG_PCI_MSI
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static unsigned long hpet_num_timers;
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#endif
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static void __iomem *hpet_virt_address;
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struct hpet_dev {
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struct clock_event_device evt;
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unsigned int num;
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int cpu;
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unsigned int irq;
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unsigned int flags;
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char name[10];
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};
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unsigned long hpet_readl(unsigned long a)
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{
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return readl(hpet_virt_address + a);
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}
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static inline void hpet_writel(unsigned long d, unsigned long a)
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{
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writel(d, hpet_virt_address + a);
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}
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#ifdef CONFIG_X86_64
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#include <asm/pgtable.h>
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#endif
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static inline void hpet_set_mapping(void)
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{
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hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE);
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#ifdef CONFIG_X86_64
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__set_fixmap(VSYSCALL_HPET, hpet_address, PAGE_KERNEL_VSYSCALL_NOCACHE);
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#endif
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}
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static inline void hpet_clear_mapping(void)
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{
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iounmap(hpet_virt_address);
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hpet_virt_address = NULL;
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}
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/*
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* HPET command line enable / disable
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*/
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static int boot_hpet_disable;
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int hpet_force_user;
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static int hpet_verbose;
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static int __init hpet_setup(char *str)
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{
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if (str) {
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if (!strncmp("disable", str, 7))
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boot_hpet_disable = 1;
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if (!strncmp("force", str, 5))
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hpet_force_user = 1;
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if (!strncmp("verbose", str, 7))
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hpet_verbose = 1;
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}
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return 1;
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}
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__setup("hpet=", hpet_setup);
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static int __init disable_hpet(char *str)
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{
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boot_hpet_disable = 1;
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return 1;
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}
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__setup("nohpet", disable_hpet);
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static inline int is_hpet_capable(void)
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{
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return !boot_hpet_disable && hpet_address;
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}
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/*
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* HPET timer interrupt enable / disable
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*/
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static int hpet_legacy_int_enabled;
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/**
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* is_hpet_enabled - check whether the hpet timer interrupt is enabled
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*/
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int is_hpet_enabled(void)
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{
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return is_hpet_capable() && hpet_legacy_int_enabled;
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}
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EXPORT_SYMBOL_GPL(is_hpet_enabled);
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static void _hpet_print_config(const char *function, int line)
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{
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u32 i, timers, l, h;
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printk(KERN_INFO "hpet: %s(%d):\n", function, line);
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l = hpet_readl(HPET_ID);
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h = hpet_readl(HPET_PERIOD);
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timers = ((l & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
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printk(KERN_INFO "hpet: ID: 0x%x, PERIOD: 0x%x\n", l, h);
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l = hpet_readl(HPET_CFG);
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h = hpet_readl(HPET_STATUS);
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printk(KERN_INFO "hpet: CFG: 0x%x, STATUS: 0x%x\n", l, h);
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l = hpet_readl(HPET_COUNTER);
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h = hpet_readl(HPET_COUNTER+4);
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printk(KERN_INFO "hpet: COUNTER_l: 0x%x, COUNTER_h: 0x%x\n", l, h);
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for (i = 0; i < timers; i++) {
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l = hpet_readl(HPET_Tn_CFG(i));
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h = hpet_readl(HPET_Tn_CFG(i)+4);
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printk(KERN_INFO "hpet: T%d: CFG_l: 0x%x, CFG_h: 0x%x\n",
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i, l, h);
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l = hpet_readl(HPET_Tn_CMP(i));
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h = hpet_readl(HPET_Tn_CMP(i)+4);
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printk(KERN_INFO "hpet: T%d: CMP_l: 0x%x, CMP_h: 0x%x\n",
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i, l, h);
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l = hpet_readl(HPET_Tn_ROUTE(i));
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h = hpet_readl(HPET_Tn_ROUTE(i)+4);
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printk(KERN_INFO "hpet: T%d ROUTE_l: 0x%x, ROUTE_h: 0x%x\n",
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i, l, h);
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}
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}
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#define hpet_print_config() \
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do { \
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if (hpet_verbose) \
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_hpet_print_config(__FUNCTION__, __LINE__); \
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} while (0)
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/*
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* When the hpet driver (/dev/hpet) is enabled, we need to reserve
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* timer 0 and timer 1 in case of RTC emulation.
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*/
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#ifdef CONFIG_HPET
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static void hpet_reserve_msi_timers(struct hpet_data *hd);
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static void hpet_reserve_platform_timers(unsigned long id)
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{
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struct hpet __iomem *hpet = hpet_virt_address;
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struct hpet_timer __iomem *timer = &hpet->hpet_timers[2];
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unsigned int nrtimers, i;
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struct hpet_data hd;
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nrtimers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
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memset(&hd, 0, sizeof(hd));
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hd.hd_phys_address = hpet_address;
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hd.hd_address = hpet;
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hd.hd_nirqs = nrtimers;
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hpet_reserve_timer(&hd, 0);
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#ifdef CONFIG_HPET_EMULATE_RTC
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hpet_reserve_timer(&hd, 1);
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#endif
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/*
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* NOTE that hd_irq[] reflects IOAPIC input pins (LEGACY_8254
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* is wrong for i8259!) not the output IRQ. Many BIOS writers
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* don't bother configuring *any* comparator interrupts.
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*/
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hd.hd_irq[0] = HPET_LEGACY_8254;
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hd.hd_irq[1] = HPET_LEGACY_RTC;
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for (i = 2; i < nrtimers; timer++, i++) {
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hd.hd_irq[i] = (readl(&timer->hpet_config) &
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Tn_INT_ROUTE_CNF_MASK) >> Tn_INT_ROUTE_CNF_SHIFT;
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}
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hpet_reserve_msi_timers(&hd);
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hpet_alloc(&hd);
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}
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#else
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static void hpet_reserve_platform_timers(unsigned long id) { }
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#endif
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/*
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* Common hpet info
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*/
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static unsigned long hpet_period;
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static void hpet_legacy_set_mode(enum clock_event_mode mode,
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struct clock_event_device *evt);
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static int hpet_legacy_next_event(unsigned long delta,
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struct clock_event_device *evt);
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/*
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* The hpet clock event device
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*/
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static struct clock_event_device hpet_clockevent = {
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.name = "hpet",
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.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
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.set_mode = hpet_legacy_set_mode,
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.set_next_event = hpet_legacy_next_event,
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.shift = 32,
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.irq = 0,
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.rating = 50,
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};
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static void hpet_stop_counter(void)
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{
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unsigned long cfg = hpet_readl(HPET_CFG);
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cfg &= ~HPET_CFG_ENABLE;
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hpet_writel(cfg, HPET_CFG);
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}
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static void hpet_reset_counter(void)
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{
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hpet_writel(0, HPET_COUNTER);
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hpet_writel(0, HPET_COUNTER + 4);
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}
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static void hpet_start_counter(void)
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{
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unsigned long cfg = hpet_readl(HPET_CFG);
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cfg |= HPET_CFG_ENABLE;
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hpet_writel(cfg, HPET_CFG);
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}
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static void hpet_restart_counter(void)
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{
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hpet_stop_counter();
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hpet_reset_counter();
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hpet_start_counter();
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}
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static void hpet_resume_device(void)
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{
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force_hpet_resume();
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}
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static void hpet_resume_counter(void)
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{
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hpet_resume_device();
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hpet_restart_counter();
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}
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static void hpet_enable_legacy_int(void)
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{
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unsigned long cfg = hpet_readl(HPET_CFG);
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cfg |= HPET_CFG_LEGACY;
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hpet_writel(cfg, HPET_CFG);
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hpet_legacy_int_enabled = 1;
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}
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static void hpet_legacy_clockevent_register(void)
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{
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/* Start HPET legacy interrupts */
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hpet_enable_legacy_int();
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/*
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* The mult factor is defined as (include/linux/clockchips.h)
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* mult/2^shift = cyc/ns (in contrast to ns/cyc in clocksource.h)
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* hpet_period is in units of femtoseconds (per cycle), so
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* mult/2^shift = cyc/ns = 10^6/hpet_period
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* mult = (10^6 * 2^shift)/hpet_period
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* mult = (FSEC_PER_NSEC << hpet_clockevent.shift)/hpet_period
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*/
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hpet_clockevent.mult = div_sc((unsigned long) FSEC_PER_NSEC,
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hpet_period, hpet_clockevent.shift);
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/* Calculate the min / max delta */
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hpet_clockevent.max_delta_ns = clockevent_delta2ns(0x7FFFFFFF,
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&hpet_clockevent);
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/* 5 usec minimum reprogramming delta. */
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hpet_clockevent.min_delta_ns = 5000;
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/*
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* Start hpet with the boot cpu mask and make it
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* global after the IO_APIC has been initialized.
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*/
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hpet_clockevent.cpumask = cpumask_of(smp_processor_id());
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clockevents_register_device(&hpet_clockevent);
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global_clock_event = &hpet_clockevent;
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printk(KERN_DEBUG "hpet clockevent registered\n");
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}
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static int hpet_setup_msi_irq(unsigned int irq);
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static void hpet_set_mode(enum clock_event_mode mode,
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struct clock_event_device *evt, int timer)
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{
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unsigned long cfg, cmp, now;
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uint64_t delta;
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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hpet_stop_counter();
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delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * evt->mult;
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delta >>= evt->shift;
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now = hpet_readl(HPET_COUNTER);
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cmp = now + (unsigned long) delta;
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cfg = hpet_readl(HPET_Tn_CFG(timer));
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/* Make sure we use edge triggered interrupts */
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cfg &= ~HPET_TN_LEVEL;
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cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC |
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HPET_TN_SETVAL | HPET_TN_32BIT;
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hpet_writel(cfg, HPET_Tn_CFG(timer));
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hpet_writel(cmp, HPET_Tn_CMP(timer));
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udelay(1);
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/*
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* HPET on AMD 81xx needs a second write (with HPET_TN_SETVAL
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* cleared) to T0_CMP to set the period. The HPET_TN_SETVAL
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* bit is automatically cleared after the first write.
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* (See AMD-8111 HyperTransport I/O Hub Data Sheet,
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* Publication # 24674)
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*/
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hpet_writel((unsigned long) delta, HPET_Tn_CMP(timer));
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hpet_start_counter();
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hpet_print_config();
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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cfg = hpet_readl(HPET_Tn_CFG(timer));
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cfg &= ~HPET_TN_PERIODIC;
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cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
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hpet_writel(cfg, HPET_Tn_CFG(timer));
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break;
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case CLOCK_EVT_MODE_UNUSED:
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case CLOCK_EVT_MODE_SHUTDOWN:
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cfg = hpet_readl(HPET_Tn_CFG(timer));
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cfg &= ~HPET_TN_ENABLE;
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hpet_writel(cfg, HPET_Tn_CFG(timer));
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break;
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case CLOCK_EVT_MODE_RESUME:
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if (timer == 0) {
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hpet_enable_legacy_int();
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} else {
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struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
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hpet_setup_msi_irq(hdev->irq);
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disable_irq(hdev->irq);
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irq_set_affinity(hdev->irq, cpumask_of(hdev->cpu));
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enable_irq(hdev->irq);
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}
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hpet_print_config();
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break;
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}
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}
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static int hpet_next_event(unsigned long delta,
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struct clock_event_device *evt, int timer)
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{
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u32 cnt;
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cnt = hpet_readl(HPET_COUNTER);
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cnt += (u32) delta;
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hpet_writel(cnt, HPET_Tn_CMP(timer));
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/*
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* We need to read back the CMP register to make sure that
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* what we wrote hit the chip before we compare it to the
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* counter.
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*/
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WARN_ON_ONCE((u32)hpet_readl(HPET_Tn_CMP(timer)) != cnt);
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return (s32)((u32)hpet_readl(HPET_COUNTER) - cnt) >= 0 ? -ETIME : 0;
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}
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static void hpet_legacy_set_mode(enum clock_event_mode mode,
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struct clock_event_device *evt)
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{
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hpet_set_mode(mode, evt, 0);
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}
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static int hpet_legacy_next_event(unsigned long delta,
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struct clock_event_device *evt)
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{
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return hpet_next_event(delta, evt, 0);
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}
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/*
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* HPET MSI Support
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*/
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#ifdef CONFIG_PCI_MSI
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static DEFINE_PER_CPU(struct hpet_dev *, cpu_hpet_dev);
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static struct hpet_dev *hpet_devs;
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void hpet_msi_unmask(unsigned int irq)
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{
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struct hpet_dev *hdev = get_irq_data(irq);
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unsigned long cfg;
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/* unmask it */
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cfg = hpet_readl(HPET_Tn_CFG(hdev->num));
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cfg |= HPET_TN_FSB;
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hpet_writel(cfg, HPET_Tn_CFG(hdev->num));
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}
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void hpet_msi_mask(unsigned int irq)
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{
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unsigned long cfg;
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struct hpet_dev *hdev = get_irq_data(irq);
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/* mask it */
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cfg = hpet_readl(HPET_Tn_CFG(hdev->num));
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cfg &= ~HPET_TN_FSB;
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hpet_writel(cfg, HPET_Tn_CFG(hdev->num));
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}
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void hpet_msi_write(unsigned int irq, struct msi_msg *msg)
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{
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struct hpet_dev *hdev = get_irq_data(irq);
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hpet_writel(msg->data, HPET_Tn_ROUTE(hdev->num));
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hpet_writel(msg->address_lo, HPET_Tn_ROUTE(hdev->num) + 4);
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}
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void hpet_msi_read(unsigned int irq, struct msi_msg *msg)
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{
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struct hpet_dev *hdev = get_irq_data(irq);
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msg->data = hpet_readl(HPET_Tn_ROUTE(hdev->num));
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msg->address_lo = hpet_readl(HPET_Tn_ROUTE(hdev->num) + 4);
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msg->address_hi = 0;
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}
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static void hpet_msi_set_mode(enum clock_event_mode mode,
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struct clock_event_device *evt)
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{
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struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
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hpet_set_mode(mode, evt, hdev->num);
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}
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static int hpet_msi_next_event(unsigned long delta,
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struct clock_event_device *evt)
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{
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struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
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return hpet_next_event(delta, evt, hdev->num);
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}
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static int hpet_setup_msi_irq(unsigned int irq)
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{
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if (arch_setup_hpet_msi(irq)) {
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destroy_irq(irq);
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return -EINVAL;
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}
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return 0;
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}
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|
static int hpet_assign_irq(struct hpet_dev *dev)
|
|
{
|
|
unsigned int irq;
|
|
|
|
irq = create_irq();
|
|
if (!irq)
|
|
return -EINVAL;
|
|
|
|
set_irq_data(irq, dev);
|
|
|
|
if (hpet_setup_msi_irq(irq))
|
|
return -EINVAL;
|
|
|
|
dev->irq = irq;
|
|
return 0;
|
|
}
|
|
|
|
static irqreturn_t hpet_interrupt_handler(int irq, void *data)
|
|
{
|
|
struct hpet_dev *dev = (struct hpet_dev *)data;
|
|
struct clock_event_device *hevt = &dev->evt;
|
|
|
|
if (!hevt->event_handler) {
|
|
printk(KERN_INFO "Spurious HPET timer interrupt on HPET timer %d\n",
|
|
dev->num);
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
hevt->event_handler(hevt);
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static int hpet_setup_irq(struct hpet_dev *dev)
|
|
{
|
|
|
|
if (request_irq(dev->irq, hpet_interrupt_handler,
|
|
IRQF_TIMER | IRQF_DISABLED | IRQF_NOBALANCING,
|
|
dev->name, dev))
|
|
return -1;
|
|
|
|
disable_irq(dev->irq);
|
|
irq_set_affinity(dev->irq, cpumask_of(dev->cpu));
|
|
enable_irq(dev->irq);
|
|
|
|
printk(KERN_DEBUG "hpet: %s irq %d for MSI\n",
|
|
dev->name, dev->irq);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* This should be called in specific @cpu */
|
|
static void init_one_hpet_msi_clockevent(struct hpet_dev *hdev, int cpu)
|
|
{
|
|
struct clock_event_device *evt = &hdev->evt;
|
|
uint64_t hpet_freq;
|
|
|
|
WARN_ON(cpu != smp_processor_id());
|
|
if (!(hdev->flags & HPET_DEV_VALID))
|
|
return;
|
|
|
|
if (hpet_setup_msi_irq(hdev->irq))
|
|
return;
|
|
|
|
hdev->cpu = cpu;
|
|
per_cpu(cpu_hpet_dev, cpu) = hdev;
|
|
evt->name = hdev->name;
|
|
hpet_setup_irq(hdev);
|
|
evt->irq = hdev->irq;
|
|
|
|
evt->rating = 110;
|
|
evt->features = CLOCK_EVT_FEAT_ONESHOT;
|
|
if (hdev->flags & HPET_DEV_PERI_CAP)
|
|
evt->features |= CLOCK_EVT_FEAT_PERIODIC;
|
|
|
|
evt->set_mode = hpet_msi_set_mode;
|
|
evt->set_next_event = hpet_msi_next_event;
|
|
evt->shift = 32;
|
|
|
|
/*
|
|
* The period is a femto seconds value. We need to calculate the
|
|
* scaled math multiplication factor for nanosecond to hpet tick
|
|
* conversion.
|
|
*/
|
|
hpet_freq = 1000000000000000ULL;
|
|
do_div(hpet_freq, hpet_period);
|
|
evt->mult = div_sc((unsigned long) hpet_freq,
|
|
NSEC_PER_SEC, evt->shift);
|
|
/* Calculate the max delta */
|
|
evt->max_delta_ns = clockevent_delta2ns(0x7FFFFFFF, evt);
|
|
/* 5 usec minimum reprogramming delta. */
|
|
evt->min_delta_ns = 5000;
|
|
|
|
evt->cpumask = cpumask_of(hdev->cpu);
|
|
clockevents_register_device(evt);
|
|
}
|
|
|
|
#ifdef CONFIG_HPET
|
|
/* Reserve at least one timer for userspace (/dev/hpet) */
|
|
#define RESERVE_TIMERS 1
|
|
#else
|
|
#define RESERVE_TIMERS 0
|
|
#endif
|
|
|
|
static void hpet_msi_capability_lookup(unsigned int start_timer)
|
|
{
|
|
unsigned int id;
|
|
unsigned int num_timers;
|
|
unsigned int num_timers_used = 0;
|
|
int i;
|
|
|
|
id = hpet_readl(HPET_ID);
|
|
|
|
num_timers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT);
|
|
num_timers++; /* Value read out starts from 0 */
|
|
hpet_print_config();
|
|
|
|
hpet_devs = kzalloc(sizeof(struct hpet_dev) * num_timers, GFP_KERNEL);
|
|
if (!hpet_devs)
|
|
return;
|
|
|
|
hpet_num_timers = num_timers;
|
|
|
|
for (i = start_timer; i < num_timers - RESERVE_TIMERS; i++) {
|
|
struct hpet_dev *hdev = &hpet_devs[num_timers_used];
|
|
unsigned long cfg = hpet_readl(HPET_Tn_CFG(i));
|
|
|
|
/* Only consider HPET timer with MSI support */
|
|
if (!(cfg & HPET_TN_FSB_CAP))
|
|
continue;
|
|
|
|
hdev->flags = 0;
|
|
if (cfg & HPET_TN_PERIODIC_CAP)
|
|
hdev->flags |= HPET_DEV_PERI_CAP;
|
|
hdev->num = i;
|
|
|
|
sprintf(hdev->name, "hpet%d", i);
|
|
if (hpet_assign_irq(hdev))
|
|
continue;
|
|
|
|
hdev->flags |= HPET_DEV_FSB_CAP;
|
|
hdev->flags |= HPET_DEV_VALID;
|
|
num_timers_used++;
|
|
if (num_timers_used == num_possible_cpus())
|
|
break;
|
|
}
|
|
|
|
printk(KERN_INFO "HPET: %d timers in total, %d timers will be used for per-cpu timer\n",
|
|
num_timers, num_timers_used);
|
|
}
|
|
|
|
#ifdef CONFIG_HPET
|
|
static void hpet_reserve_msi_timers(struct hpet_data *hd)
|
|
{
|
|
int i;
|
|
|
|
if (!hpet_devs)
|
|
return;
|
|
|
|
for (i = 0; i < hpet_num_timers; i++) {
|
|
struct hpet_dev *hdev = &hpet_devs[i];
|
|
|
|
if (!(hdev->flags & HPET_DEV_VALID))
|
|
continue;
|
|
|
|
hd->hd_irq[hdev->num] = hdev->irq;
|
|
hpet_reserve_timer(hd, hdev->num);
|
|
}
|
|
}
|
|
#endif
|
|
|
|
static struct hpet_dev *hpet_get_unused_timer(void)
|
|
{
|
|
int i;
|
|
|
|
if (!hpet_devs)
|
|
return NULL;
|
|
|
|
for (i = 0; i < hpet_num_timers; i++) {
|
|
struct hpet_dev *hdev = &hpet_devs[i];
|
|
|
|
if (!(hdev->flags & HPET_DEV_VALID))
|
|
continue;
|
|
if (test_and_set_bit(HPET_DEV_USED_BIT,
|
|
(unsigned long *)&hdev->flags))
|
|
continue;
|
|
return hdev;
|
|
}
|
|
return NULL;
|
|
}
|
|
|
|
struct hpet_work_struct {
|
|
struct delayed_work work;
|
|
struct completion complete;
|
|
};
|
|
|
|
static void hpet_work(struct work_struct *w)
|
|
{
|
|
struct hpet_dev *hdev;
|
|
int cpu = smp_processor_id();
|
|
struct hpet_work_struct *hpet_work;
|
|
|
|
hpet_work = container_of(w, struct hpet_work_struct, work.work);
|
|
|
|
hdev = hpet_get_unused_timer();
|
|
if (hdev)
|
|
init_one_hpet_msi_clockevent(hdev, cpu);
|
|
|
|
complete(&hpet_work->complete);
|
|
}
|
|
|
|
static int hpet_cpuhp_notify(struct notifier_block *n,
|
|
unsigned long action, void *hcpu)
|
|
{
|
|
unsigned long cpu = (unsigned long)hcpu;
|
|
struct hpet_work_struct work;
|
|
struct hpet_dev *hdev = per_cpu(cpu_hpet_dev, cpu);
|
|
|
|
switch (action & 0xf) {
|
|
case CPU_ONLINE:
|
|
INIT_DELAYED_WORK_ON_STACK(&work.work, hpet_work);
|
|
init_completion(&work.complete);
|
|
/* FIXME: add schedule_work_on() */
|
|
schedule_delayed_work_on(cpu, &work.work, 0);
|
|
wait_for_completion(&work.complete);
|
|
destroy_timer_on_stack(&work.work.timer);
|
|
break;
|
|
case CPU_DEAD:
|
|
if (hdev) {
|
|
free_irq(hdev->irq, hdev);
|
|
hdev->flags &= ~HPET_DEV_USED;
|
|
per_cpu(cpu_hpet_dev, cpu) = NULL;
|
|
}
|
|
break;
|
|
}
|
|
return NOTIFY_OK;
|
|
}
|
|
#else
|
|
|
|
static int hpet_setup_msi_irq(unsigned int irq)
|
|
{
|
|
return 0;
|
|
}
|
|
static void hpet_msi_capability_lookup(unsigned int start_timer)
|
|
{
|
|
return;
|
|
}
|
|
|
|
#ifdef CONFIG_HPET
|
|
static void hpet_reserve_msi_timers(struct hpet_data *hd)
|
|
{
|
|
return;
|
|
}
|
|
#endif
|
|
|
|
static int hpet_cpuhp_notify(struct notifier_block *n,
|
|
unsigned long action, void *hcpu)
|
|
{
|
|
return NOTIFY_OK;
|
|
}
|
|
|
|
#endif
|
|
|
|
/*
|
|
* Clock source related code
|
|
*/
|
|
static cycle_t read_hpet(struct clocksource *cs)
|
|
{
|
|
return (cycle_t)hpet_readl(HPET_COUNTER);
|
|
}
|
|
|
|
#ifdef CONFIG_X86_64
|
|
static cycle_t __vsyscall_fn vread_hpet(void)
|
|
{
|
|
return readl((const void __iomem *)fix_to_virt(VSYSCALL_HPET) + 0xf0);
|
|
}
|
|
#endif
|
|
|
|
static struct clocksource clocksource_hpet = {
|
|
.name = "hpet",
|
|
.rating = 250,
|
|
.read = read_hpet,
|
|
.mask = HPET_MASK,
|
|
.shift = HPET_SHIFT,
|
|
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
|
|
.resume = hpet_resume_counter,
|
|
#ifdef CONFIG_X86_64
|
|
.vread = vread_hpet,
|
|
#endif
|
|
};
|
|
|
|
static int hpet_clocksource_register(void)
|
|
{
|
|
u64 start, now;
|
|
cycle_t t1;
|
|
|
|
/* Start the counter */
|
|
hpet_restart_counter();
|
|
|
|
/* Verify whether hpet counter works */
|
|
t1 = hpet_readl(HPET_COUNTER);
|
|
rdtscll(start);
|
|
|
|
/*
|
|
* We don't know the TSC frequency yet, but waiting for
|
|
* 200000 TSC cycles is safe:
|
|
* 4 GHz == 50us
|
|
* 1 GHz == 200us
|
|
*/
|
|
do {
|
|
rep_nop();
|
|
rdtscll(now);
|
|
} while ((now - start) < 200000UL);
|
|
|
|
if (t1 == hpet_readl(HPET_COUNTER)) {
|
|
printk(KERN_WARNING
|
|
"HPET counter not counting. HPET disabled\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
/*
|
|
* The definition of mult is (include/linux/clocksource.h)
|
|
* mult/2^shift = ns/cyc and hpet_period is in units of fsec/cyc
|
|
* so we first need to convert hpet_period to ns/cyc units:
|
|
* mult/2^shift = ns/cyc = hpet_period/10^6
|
|
* mult = (hpet_period * 2^shift)/10^6
|
|
* mult = (hpet_period << shift)/FSEC_PER_NSEC
|
|
*/
|
|
clocksource_hpet.mult = div_sc(hpet_period, FSEC_PER_NSEC, HPET_SHIFT);
|
|
|
|
clocksource_register(&clocksource_hpet);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* hpet_enable - Try to setup the HPET timer. Returns 1 on success.
|
|
*/
|
|
int __init hpet_enable(void)
|
|
{
|
|
unsigned long id;
|
|
int i;
|
|
|
|
if (!is_hpet_capable())
|
|
return 0;
|
|
|
|
hpet_set_mapping();
|
|
|
|
/*
|
|
* Read the period and check for a sane value:
|
|
*/
|
|
hpet_period = hpet_readl(HPET_PERIOD);
|
|
|
|
/*
|
|
* AMD SB700 based systems with spread spectrum enabled use a
|
|
* SMM based HPET emulation to provide proper frequency
|
|
* setting. The SMM code is initialized with the first HPET
|
|
* register access and takes some time to complete. During
|
|
* this time the config register reads 0xffffffff. We check
|
|
* for max. 1000 loops whether the config register reads a non
|
|
* 0xffffffff value to make sure that HPET is up and running
|
|
* before we go further. A counting loop is safe, as the HPET
|
|
* access takes thousands of CPU cycles. On non SB700 based
|
|
* machines this check is only done once and has no side
|
|
* effects.
|
|
*/
|
|
for (i = 0; hpet_readl(HPET_CFG) == 0xFFFFFFFF; i++) {
|
|
if (i == 1000) {
|
|
printk(KERN_WARNING
|
|
"HPET config register value = 0xFFFFFFFF. "
|
|
"Disabling HPET\n");
|
|
goto out_nohpet;
|
|
}
|
|
}
|
|
|
|
if (hpet_period < HPET_MIN_PERIOD || hpet_period > HPET_MAX_PERIOD)
|
|
goto out_nohpet;
|
|
|
|
/*
|
|
* Read the HPET ID register to retrieve the IRQ routing
|
|
* information and the number of channels
|
|
*/
|
|
id = hpet_readl(HPET_ID);
|
|
hpet_print_config();
|
|
|
|
#ifdef CONFIG_HPET_EMULATE_RTC
|
|
/*
|
|
* The legacy routing mode needs at least two channels, tick timer
|
|
* and the rtc emulation channel.
|
|
*/
|
|
if (!(id & HPET_ID_NUMBER))
|
|
goto out_nohpet;
|
|
#endif
|
|
|
|
if (hpet_clocksource_register())
|
|
goto out_nohpet;
|
|
|
|
if (id & HPET_ID_LEGSUP) {
|
|
hpet_legacy_clockevent_register();
|
|
hpet_msi_capability_lookup(2);
|
|
return 1;
|
|
}
|
|
hpet_msi_capability_lookup(0);
|
|
return 0;
|
|
|
|
out_nohpet:
|
|
hpet_clear_mapping();
|
|
hpet_address = 0;
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Needs to be late, as the reserve_timer code calls kalloc !
|
|
*
|
|
* Not a problem on i386 as hpet_enable is called from late_time_init,
|
|
* but on x86_64 it is necessary !
|
|
*/
|
|
static __init int hpet_late_init(void)
|
|
{
|
|
int cpu;
|
|
|
|
if (boot_hpet_disable)
|
|
return -ENODEV;
|
|
|
|
if (!hpet_address) {
|
|
if (!force_hpet_address)
|
|
return -ENODEV;
|
|
|
|
hpet_address = force_hpet_address;
|
|
hpet_enable();
|
|
}
|
|
|
|
if (!hpet_virt_address)
|
|
return -ENODEV;
|
|
|
|
hpet_reserve_platform_timers(hpet_readl(HPET_ID));
|
|
hpet_print_config();
|
|
|
|
for_each_online_cpu(cpu) {
|
|
hpet_cpuhp_notify(NULL, CPU_ONLINE, (void *)(long)cpu);
|
|
}
|
|
|
|
/* This notifier should be called after workqueue is ready */
|
|
hotcpu_notifier(hpet_cpuhp_notify, -20);
|
|
|
|
return 0;
|
|
}
|
|
fs_initcall(hpet_late_init);
|
|
|
|
void hpet_disable(void)
|
|
{
|
|
if (is_hpet_capable()) {
|
|
unsigned long cfg = hpet_readl(HPET_CFG);
|
|
|
|
if (hpet_legacy_int_enabled) {
|
|
cfg &= ~HPET_CFG_LEGACY;
|
|
hpet_legacy_int_enabled = 0;
|
|
}
|
|
cfg &= ~HPET_CFG_ENABLE;
|
|
hpet_writel(cfg, HPET_CFG);
|
|
}
|
|
}
|
|
|
|
#ifdef CONFIG_HPET_EMULATE_RTC
|
|
|
|
/* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET
|
|
* is enabled, we support RTC interrupt functionality in software.
|
|
* RTC has 3 kinds of interrupts:
|
|
* 1) Update Interrupt - generate an interrupt, every sec, when RTC clock
|
|
* is updated
|
|
* 2) Alarm Interrupt - generate an interrupt at a specific time of day
|
|
* 3) Periodic Interrupt - generate periodic interrupt, with frequencies
|
|
* 2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2)
|
|
* (1) and (2) above are implemented using polling at a frequency of
|
|
* 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt
|
|
* overhead. (DEFAULT_RTC_INT_FREQ)
|
|
* For (3), we use interrupts at 64Hz or user specified periodic
|
|
* frequency, whichever is higher.
|
|
*/
|
|
#include <linux/mc146818rtc.h>
|
|
#include <linux/rtc.h>
|
|
#include <asm/rtc.h>
|
|
|
|
#define DEFAULT_RTC_INT_FREQ 64
|
|
#define DEFAULT_RTC_SHIFT 6
|
|
#define RTC_NUM_INTS 1
|
|
|
|
static unsigned long hpet_rtc_flags;
|
|
static int hpet_prev_update_sec;
|
|
static struct rtc_time hpet_alarm_time;
|
|
static unsigned long hpet_pie_count;
|
|
static u32 hpet_t1_cmp;
|
|
static unsigned long hpet_default_delta;
|
|
static unsigned long hpet_pie_delta;
|
|
static unsigned long hpet_pie_limit;
|
|
|
|
static rtc_irq_handler irq_handler;
|
|
|
|
/*
|
|
* Check that the hpet counter c1 is ahead of the c2
|
|
*/
|
|
static inline int hpet_cnt_ahead(u32 c1, u32 c2)
|
|
{
|
|
return (s32)(c2 - c1) < 0;
|
|
}
|
|
|
|
/*
|
|
* Registers a IRQ handler.
|
|
*/
|
|
int hpet_register_irq_handler(rtc_irq_handler handler)
|
|
{
|
|
if (!is_hpet_enabled())
|
|
return -ENODEV;
|
|
if (irq_handler)
|
|
return -EBUSY;
|
|
|
|
irq_handler = handler;
|
|
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL_GPL(hpet_register_irq_handler);
|
|
|
|
/*
|
|
* Deregisters the IRQ handler registered with hpet_register_irq_handler()
|
|
* and does cleanup.
|
|
*/
|
|
void hpet_unregister_irq_handler(rtc_irq_handler handler)
|
|
{
|
|
if (!is_hpet_enabled())
|
|
return;
|
|
|
|
irq_handler = NULL;
|
|
hpet_rtc_flags = 0;
|
|
}
|
|
EXPORT_SYMBOL_GPL(hpet_unregister_irq_handler);
|
|
|
|
/*
|
|
* Timer 1 for RTC emulation. We use one shot mode, as periodic mode
|
|
* is not supported by all HPET implementations for timer 1.
|
|
*
|
|
* hpet_rtc_timer_init() is called when the rtc is initialized.
|
|
*/
|
|
int hpet_rtc_timer_init(void)
|
|
{
|
|
unsigned long cfg, cnt, delta, flags;
|
|
|
|
if (!is_hpet_enabled())
|
|
return 0;
|
|
|
|
if (!hpet_default_delta) {
|
|
uint64_t clc;
|
|
|
|
clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
|
|
clc >>= hpet_clockevent.shift + DEFAULT_RTC_SHIFT;
|
|
hpet_default_delta = (unsigned long) clc;
|
|
}
|
|
|
|
if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
|
|
delta = hpet_default_delta;
|
|
else
|
|
delta = hpet_pie_delta;
|
|
|
|
local_irq_save(flags);
|
|
|
|
cnt = delta + hpet_readl(HPET_COUNTER);
|
|
hpet_writel(cnt, HPET_T1_CMP);
|
|
hpet_t1_cmp = cnt;
|
|
|
|
cfg = hpet_readl(HPET_T1_CFG);
|
|
cfg &= ~HPET_TN_PERIODIC;
|
|
cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
|
|
hpet_writel(cfg, HPET_T1_CFG);
|
|
|
|
local_irq_restore(flags);
|
|
|
|
return 1;
|
|
}
|
|
EXPORT_SYMBOL_GPL(hpet_rtc_timer_init);
|
|
|
|
/*
|
|
* The functions below are called from rtc driver.
|
|
* Return 0 if HPET is not being used.
|
|
* Otherwise do the necessary changes and return 1.
|
|
*/
|
|
int hpet_mask_rtc_irq_bit(unsigned long bit_mask)
|
|
{
|
|
if (!is_hpet_enabled())
|
|
return 0;
|
|
|
|
hpet_rtc_flags &= ~bit_mask;
|
|
return 1;
|
|
}
|
|
EXPORT_SYMBOL_GPL(hpet_mask_rtc_irq_bit);
|
|
|
|
int hpet_set_rtc_irq_bit(unsigned long bit_mask)
|
|
{
|
|
unsigned long oldbits = hpet_rtc_flags;
|
|
|
|
if (!is_hpet_enabled())
|
|
return 0;
|
|
|
|
hpet_rtc_flags |= bit_mask;
|
|
|
|
if ((bit_mask & RTC_UIE) && !(oldbits & RTC_UIE))
|
|
hpet_prev_update_sec = -1;
|
|
|
|
if (!oldbits)
|
|
hpet_rtc_timer_init();
|
|
|
|
return 1;
|
|
}
|
|
EXPORT_SYMBOL_GPL(hpet_set_rtc_irq_bit);
|
|
|
|
int hpet_set_alarm_time(unsigned char hrs, unsigned char min,
|
|
unsigned char sec)
|
|
{
|
|
if (!is_hpet_enabled())
|
|
return 0;
|
|
|
|
hpet_alarm_time.tm_hour = hrs;
|
|
hpet_alarm_time.tm_min = min;
|
|
hpet_alarm_time.tm_sec = sec;
|
|
|
|
return 1;
|
|
}
|
|
EXPORT_SYMBOL_GPL(hpet_set_alarm_time);
|
|
|
|
int hpet_set_periodic_freq(unsigned long freq)
|
|
{
|
|
uint64_t clc;
|
|
|
|
if (!is_hpet_enabled())
|
|
return 0;
|
|
|
|
if (freq <= DEFAULT_RTC_INT_FREQ)
|
|
hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq;
|
|
else {
|
|
clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
|
|
do_div(clc, freq);
|
|
clc >>= hpet_clockevent.shift;
|
|
hpet_pie_delta = (unsigned long) clc;
|
|
}
|
|
return 1;
|
|
}
|
|
EXPORT_SYMBOL_GPL(hpet_set_periodic_freq);
|
|
|
|
int hpet_rtc_dropped_irq(void)
|
|
{
|
|
return is_hpet_enabled();
|
|
}
|
|
EXPORT_SYMBOL_GPL(hpet_rtc_dropped_irq);
|
|
|
|
static void hpet_rtc_timer_reinit(void)
|
|
{
|
|
unsigned long cfg, delta;
|
|
int lost_ints = -1;
|
|
|
|
if (unlikely(!hpet_rtc_flags)) {
|
|
cfg = hpet_readl(HPET_T1_CFG);
|
|
cfg &= ~HPET_TN_ENABLE;
|
|
hpet_writel(cfg, HPET_T1_CFG);
|
|
return;
|
|
}
|
|
|
|
if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
|
|
delta = hpet_default_delta;
|
|
else
|
|
delta = hpet_pie_delta;
|
|
|
|
/*
|
|
* Increment the comparator value until we are ahead of the
|
|
* current count.
|
|
*/
|
|
do {
|
|
hpet_t1_cmp += delta;
|
|
hpet_writel(hpet_t1_cmp, HPET_T1_CMP);
|
|
lost_ints++;
|
|
} while (!hpet_cnt_ahead(hpet_t1_cmp, hpet_readl(HPET_COUNTER)));
|
|
|
|
if (lost_ints) {
|
|
if (hpet_rtc_flags & RTC_PIE)
|
|
hpet_pie_count += lost_ints;
|
|
if (printk_ratelimit())
|
|
printk(KERN_WARNING "hpet1: lost %d rtc interrupts\n",
|
|
lost_ints);
|
|
}
|
|
}
|
|
|
|
irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id)
|
|
{
|
|
struct rtc_time curr_time;
|
|
unsigned long rtc_int_flag = 0;
|
|
|
|
hpet_rtc_timer_reinit();
|
|
memset(&curr_time, 0, sizeof(struct rtc_time));
|
|
|
|
if (hpet_rtc_flags & (RTC_UIE | RTC_AIE))
|
|
get_rtc_time(&curr_time);
|
|
|
|
if (hpet_rtc_flags & RTC_UIE &&
|
|
curr_time.tm_sec != hpet_prev_update_sec) {
|
|
if (hpet_prev_update_sec >= 0)
|
|
rtc_int_flag = RTC_UF;
|
|
hpet_prev_update_sec = curr_time.tm_sec;
|
|
}
|
|
|
|
if (hpet_rtc_flags & RTC_PIE &&
|
|
++hpet_pie_count >= hpet_pie_limit) {
|
|
rtc_int_flag |= RTC_PF;
|
|
hpet_pie_count = 0;
|
|
}
|
|
|
|
if (hpet_rtc_flags & RTC_AIE &&
|
|
(curr_time.tm_sec == hpet_alarm_time.tm_sec) &&
|
|
(curr_time.tm_min == hpet_alarm_time.tm_min) &&
|
|
(curr_time.tm_hour == hpet_alarm_time.tm_hour))
|
|
rtc_int_flag |= RTC_AF;
|
|
|
|
if (rtc_int_flag) {
|
|
rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8));
|
|
if (irq_handler)
|
|
irq_handler(rtc_int_flag, dev_id);
|
|
}
|
|
return IRQ_HANDLED;
|
|
}
|
|
EXPORT_SYMBOL_GPL(hpet_rtc_interrupt);
|
|
#endif
|