![Alok Kataria](/assets/img/avatar_default.png)
With CONFIG_STACK_PROTECTOR turned on, VMI doesn't boot with more than one processor. The problem is with the gs value not being initialized correctly when registering the secondary processor for VMI's case. The patch below initializes the gs value for the AP to __KERNEL_STACK_CANARY. Without this the secondary processor keeps on taking a GP on every gs access. Signed-off-by: Alok N Kataria <akataria@vmware.com> Cc: <stable@kernel.org> # for v2.6.30.x LKML-Reference: <1249425262.18955.40.camel@ank32.eng.vmware.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
914 lines
27 KiB
C
914 lines
27 KiB
C
/*
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* VMI specific paravirt-ops implementation
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*
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* Copyright (C) 2005, VMware, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for more
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* details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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* Send feedback to zach@vmware.com
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*
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*/
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#include <linux/module.h>
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#include <linux/cpu.h>
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#include <linux/bootmem.h>
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#include <linux/mm.h>
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#include <linux/highmem.h>
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#include <linux/sched.h>
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#include <asm/vmi.h>
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#include <asm/io.h>
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#include <asm/fixmap.h>
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#include <asm/apicdef.h>
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#include <asm/apic.h>
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#include <asm/processor.h>
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#include <asm/timer.h>
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#include <asm/vmi_time.h>
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#include <asm/kmap_types.h>
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#include <asm/setup.h>
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/* Convenient for calling VMI functions indirectly in the ROM */
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typedef u32 __attribute__((regparm(1))) (VROMFUNC)(void);
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typedef u64 __attribute__((regparm(2))) (VROMLONGFUNC)(int);
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#define call_vrom_func(rom,func) \
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(((VROMFUNC *)(rom->func))())
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#define call_vrom_long_func(rom,func,arg) \
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(((VROMLONGFUNC *)(rom->func)) (arg))
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static struct vrom_header *vmi_rom;
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static int disable_pge;
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static int disable_pse;
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static int disable_sep;
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static int disable_tsc;
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static int disable_mtrr;
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static int disable_noidle;
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static int disable_vmi_timer;
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/* Cached VMI operations */
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static struct {
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void (*cpuid)(void /* non-c */);
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void (*_set_ldt)(u32 selector);
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void (*set_tr)(u32 selector);
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void (*write_idt_entry)(struct desc_struct *, int, u32, u32);
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void (*write_gdt_entry)(struct desc_struct *, int, u32, u32);
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void (*write_ldt_entry)(struct desc_struct *, int, u32, u32);
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void (*set_kernel_stack)(u32 selector, u32 sp0);
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void (*allocate_page)(u32, u32, u32, u32, u32);
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void (*release_page)(u32, u32);
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void (*set_pte)(pte_t, pte_t *, unsigned);
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void (*update_pte)(pte_t *, unsigned);
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void (*set_linear_mapping)(int, void *, u32, u32);
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void (*_flush_tlb)(int);
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void (*set_initial_ap_state)(int, int);
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void (*halt)(void);
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void (*set_lazy_mode)(int mode);
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} vmi_ops;
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/* Cached VMI operations */
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struct vmi_timer_ops vmi_timer_ops;
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/*
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* VMI patching routines.
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*/
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#define MNEM_CALL 0xe8
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#define MNEM_JMP 0xe9
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#define MNEM_RET 0xc3
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#define IRQ_PATCH_INT_MASK 0
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#define IRQ_PATCH_DISABLE 5
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static inline void patch_offset(void *insnbuf,
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unsigned long ip, unsigned long dest)
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{
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*(unsigned long *)(insnbuf+1) = dest-ip-5;
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}
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static unsigned patch_internal(int call, unsigned len, void *insnbuf,
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unsigned long ip)
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{
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u64 reloc;
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struct vmi_relocation_info *const rel = (struct vmi_relocation_info *)&reloc;
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reloc = call_vrom_long_func(vmi_rom, get_reloc, call);
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switch(rel->type) {
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case VMI_RELOCATION_CALL_REL:
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BUG_ON(len < 5);
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*(char *)insnbuf = MNEM_CALL;
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patch_offset(insnbuf, ip, (unsigned long)rel->eip);
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return 5;
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case VMI_RELOCATION_JUMP_REL:
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BUG_ON(len < 5);
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*(char *)insnbuf = MNEM_JMP;
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patch_offset(insnbuf, ip, (unsigned long)rel->eip);
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return 5;
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case VMI_RELOCATION_NOP:
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/* obliterate the whole thing */
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return 0;
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case VMI_RELOCATION_NONE:
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/* leave native code in place */
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break;
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default:
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BUG();
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}
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return len;
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}
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/*
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* Apply patch if appropriate, return length of new instruction
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* sequence. The callee does nop padding for us.
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*/
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static unsigned vmi_patch(u8 type, u16 clobbers, void *insns,
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unsigned long ip, unsigned len)
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{
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switch (type) {
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case PARAVIRT_PATCH(pv_irq_ops.irq_disable):
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return patch_internal(VMI_CALL_DisableInterrupts, len,
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insns, ip);
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case PARAVIRT_PATCH(pv_irq_ops.irq_enable):
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return patch_internal(VMI_CALL_EnableInterrupts, len,
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insns, ip);
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case PARAVIRT_PATCH(pv_irq_ops.restore_fl):
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return patch_internal(VMI_CALL_SetInterruptMask, len,
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insns, ip);
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case PARAVIRT_PATCH(pv_irq_ops.save_fl):
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return patch_internal(VMI_CALL_GetInterruptMask, len,
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insns, ip);
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case PARAVIRT_PATCH(pv_cpu_ops.iret):
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return patch_internal(VMI_CALL_IRET, len, insns, ip);
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case PARAVIRT_PATCH(pv_cpu_ops.irq_enable_sysexit):
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return patch_internal(VMI_CALL_SYSEXIT, len, insns, ip);
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default:
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break;
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}
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return len;
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}
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/* CPUID has non-C semantics, and paravirt-ops API doesn't match hardware ISA */
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static void vmi_cpuid(unsigned int *ax, unsigned int *bx,
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unsigned int *cx, unsigned int *dx)
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{
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int override = 0;
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if (*ax == 1)
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override = 1;
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asm volatile ("call *%6"
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: "=a" (*ax),
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"=b" (*bx),
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"=c" (*cx),
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"=d" (*dx)
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: "0" (*ax), "2" (*cx), "r" (vmi_ops.cpuid));
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if (override) {
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if (disable_pse)
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*dx &= ~X86_FEATURE_PSE;
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if (disable_pge)
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*dx &= ~X86_FEATURE_PGE;
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if (disable_sep)
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*dx &= ~X86_FEATURE_SEP;
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if (disable_tsc)
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*dx &= ~X86_FEATURE_TSC;
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if (disable_mtrr)
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*dx &= ~X86_FEATURE_MTRR;
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}
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}
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static inline void vmi_maybe_load_tls(struct desc_struct *gdt, int nr, struct desc_struct *new)
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{
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if (gdt[nr].a != new->a || gdt[nr].b != new->b)
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write_gdt_entry(gdt, nr, new, 0);
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}
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static void vmi_load_tls(struct thread_struct *t, unsigned int cpu)
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{
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struct desc_struct *gdt = get_cpu_gdt_table(cpu);
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vmi_maybe_load_tls(gdt, GDT_ENTRY_TLS_MIN + 0, &t->tls_array[0]);
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vmi_maybe_load_tls(gdt, GDT_ENTRY_TLS_MIN + 1, &t->tls_array[1]);
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vmi_maybe_load_tls(gdt, GDT_ENTRY_TLS_MIN + 2, &t->tls_array[2]);
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}
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static void vmi_set_ldt(const void *addr, unsigned entries)
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{
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unsigned cpu = smp_processor_id();
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struct desc_struct desc;
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pack_descriptor(&desc, (unsigned long)addr,
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entries * sizeof(struct desc_struct) - 1,
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DESC_LDT, 0);
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write_gdt_entry(get_cpu_gdt_table(cpu), GDT_ENTRY_LDT, &desc, DESC_LDT);
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vmi_ops._set_ldt(entries ? GDT_ENTRY_LDT*sizeof(struct desc_struct) : 0);
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}
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static void vmi_set_tr(void)
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{
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vmi_ops.set_tr(GDT_ENTRY_TSS*sizeof(struct desc_struct));
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}
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static void vmi_write_idt_entry(gate_desc *dt, int entry, const gate_desc *g)
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{
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u32 *idt_entry = (u32 *)g;
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vmi_ops.write_idt_entry(dt, entry, idt_entry[0], idt_entry[1]);
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}
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static void vmi_write_gdt_entry(struct desc_struct *dt, int entry,
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const void *desc, int type)
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{
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u32 *gdt_entry = (u32 *)desc;
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vmi_ops.write_gdt_entry(dt, entry, gdt_entry[0], gdt_entry[1]);
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}
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static void vmi_write_ldt_entry(struct desc_struct *dt, int entry,
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const void *desc)
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{
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u32 *ldt_entry = (u32 *)desc;
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vmi_ops.write_ldt_entry(dt, entry, ldt_entry[0], ldt_entry[1]);
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}
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static void vmi_load_sp0(struct tss_struct *tss,
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struct thread_struct *thread)
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{
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tss->x86_tss.sp0 = thread->sp0;
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/* This can only happen when SEP is enabled, no need to test "SEP"arately */
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if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) {
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tss->x86_tss.ss1 = thread->sysenter_cs;
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wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
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}
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vmi_ops.set_kernel_stack(__KERNEL_DS, tss->x86_tss.sp0);
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}
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static void vmi_flush_tlb_user(void)
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{
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vmi_ops._flush_tlb(VMI_FLUSH_TLB);
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}
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static void vmi_flush_tlb_kernel(void)
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{
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vmi_ops._flush_tlb(VMI_FLUSH_TLB | VMI_FLUSH_GLOBAL);
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}
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/* Stub to do nothing at all; used for delays and unimplemented calls */
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static void vmi_nop(void)
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{
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}
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#ifdef CONFIG_HIGHPTE
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static void *vmi_kmap_atomic_pte(struct page *page, enum km_type type)
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{
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void *va = kmap_atomic(page, type);
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/*
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* Internally, the VMI ROM must map virtual addresses to physical
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* addresses for processing MMU updates. By the time MMU updates
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* are issued, this information is typically already lost.
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* Fortunately, the VMI provides a cache of mapping slots for active
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* page tables.
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*
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* We use slot zero for the linear mapping of physical memory, and
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* in HIGHPTE kernels, slot 1 and 2 for KM_PTE0 and KM_PTE1.
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*
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* args: SLOT VA COUNT PFN
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*/
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BUG_ON(type != KM_PTE0 && type != KM_PTE1);
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vmi_ops.set_linear_mapping((type - KM_PTE0)+1, va, 1, page_to_pfn(page));
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return va;
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}
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#endif
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static void vmi_allocate_pte(struct mm_struct *mm, unsigned long pfn)
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{
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vmi_ops.allocate_page(pfn, VMI_PAGE_L1, 0, 0, 0);
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}
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static void vmi_allocate_pmd(struct mm_struct *mm, unsigned long pfn)
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{
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/*
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* This call comes in very early, before mem_map is setup.
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* It is called only for swapper_pg_dir, which already has
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* data on it.
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*/
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vmi_ops.allocate_page(pfn, VMI_PAGE_L2, 0, 0, 0);
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}
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static void vmi_allocate_pmd_clone(unsigned long pfn, unsigned long clonepfn, unsigned long start, unsigned long count)
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{
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vmi_ops.allocate_page(pfn, VMI_PAGE_L2 | VMI_PAGE_CLONE, clonepfn, start, count);
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}
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static void vmi_release_pte(unsigned long pfn)
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{
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vmi_ops.release_page(pfn, VMI_PAGE_L1);
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}
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static void vmi_release_pmd(unsigned long pfn)
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{
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vmi_ops.release_page(pfn, VMI_PAGE_L2);
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}
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/*
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* We use the pgd_free hook for releasing the pgd page:
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*/
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static void vmi_pgd_free(struct mm_struct *mm, pgd_t *pgd)
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{
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unsigned long pfn = __pa(pgd) >> PAGE_SHIFT;
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vmi_ops.release_page(pfn, VMI_PAGE_L2);
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}
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/*
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* Helper macros for MMU update flags. We can defer updates until a flush
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* or page invalidation only if the update is to the current address space
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* (otherwise, there is no flush). We must check against init_mm, since
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* this could be a kernel update, which usually passes init_mm, although
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* sometimes this check can be skipped if we know the particular function
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* is only called on user mode PTEs. We could change the kernel to pass
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* current->active_mm here, but in particular, I was unsure if changing
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* mm/highmem.c to do this would still be correct on other architectures.
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*/
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#define is_current_as(mm, mustbeuser) ((mm) == current->active_mm || \
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(!mustbeuser && (mm) == &init_mm))
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#define vmi_flags_addr(mm, addr, level, user) \
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((level) | (is_current_as(mm, user) ? \
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(VMI_PAGE_CURRENT_AS | ((addr) & VMI_PAGE_VA_MASK)) : 0))
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#define vmi_flags_addr_defer(mm, addr, level, user) \
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((level) | (is_current_as(mm, user) ? \
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(VMI_PAGE_DEFER | VMI_PAGE_CURRENT_AS | ((addr) & VMI_PAGE_VA_MASK)) : 0))
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static void vmi_update_pte(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
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{
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vmi_ops.update_pte(ptep, vmi_flags_addr(mm, addr, VMI_PAGE_PT, 0));
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}
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static void vmi_update_pte_defer(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
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{
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vmi_ops.update_pte(ptep, vmi_flags_addr_defer(mm, addr, VMI_PAGE_PT, 0));
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}
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static void vmi_set_pte(pte_t *ptep, pte_t pte)
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{
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/* XXX because of set_pmd_pte, this can be called on PT or PD layers */
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vmi_ops.set_pte(pte, ptep, VMI_PAGE_PT);
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}
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static void vmi_set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep, pte_t pte)
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{
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vmi_ops.set_pte(pte, ptep, vmi_flags_addr(mm, addr, VMI_PAGE_PT, 0));
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}
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static void vmi_set_pmd(pmd_t *pmdp, pmd_t pmdval)
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{
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#ifdef CONFIG_X86_PAE
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const pte_t pte = { .pte = pmdval.pmd };
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#else
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const pte_t pte = { pmdval.pud.pgd.pgd };
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#endif
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vmi_ops.set_pte(pte, (pte_t *)pmdp, VMI_PAGE_PD);
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}
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#ifdef CONFIG_X86_PAE
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static void vmi_set_pte_atomic(pte_t *ptep, pte_t pteval)
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{
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/*
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* XXX This is called from set_pmd_pte, but at both PT
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* and PD layers so the VMI_PAGE_PT flag is wrong. But
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* it is only called for large page mapping changes,
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* the Xen backend, doesn't support large pages, and the
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* ESX backend doesn't depend on the flag.
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*/
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set_64bit((unsigned long long *)ptep,pte_val(pteval));
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vmi_ops.update_pte(ptep, VMI_PAGE_PT);
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}
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static void vmi_set_pud(pud_t *pudp, pud_t pudval)
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{
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/* Um, eww */
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const pte_t pte = { .pte = pudval.pgd.pgd };
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vmi_ops.set_pte(pte, (pte_t *)pudp, VMI_PAGE_PDP);
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}
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static void vmi_pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
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{
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const pte_t pte = { .pte = 0 };
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vmi_ops.set_pte(pte, ptep, vmi_flags_addr(mm, addr, VMI_PAGE_PT, 0));
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}
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static void vmi_pmd_clear(pmd_t *pmd)
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{
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const pte_t pte = { .pte = 0 };
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vmi_ops.set_pte(pte, (pte_t *)pmd, VMI_PAGE_PD);
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}
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#endif
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#ifdef CONFIG_SMP
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static void __devinit
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vmi_startup_ipi_hook(int phys_apicid, unsigned long start_eip,
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unsigned long start_esp)
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{
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struct vmi_ap_state ap;
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/* Default everything to zero. This is fine for most GPRs. */
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memset(&ap, 0, sizeof(struct vmi_ap_state));
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ap.gdtr_limit = GDT_SIZE - 1;
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ap.gdtr_base = (unsigned long) get_cpu_gdt_table(phys_apicid);
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ap.idtr_limit = IDT_ENTRIES * 8 - 1;
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ap.idtr_base = (unsigned long) idt_table;
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ap.ldtr = 0;
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ap.cs = __KERNEL_CS;
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ap.eip = (unsigned long) start_eip;
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ap.ss = __KERNEL_DS;
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ap.esp = (unsigned long) start_esp;
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ap.ds = __USER_DS;
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ap.es = __USER_DS;
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ap.fs = __KERNEL_PERCPU;
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ap.gs = __KERNEL_STACK_CANARY;
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ap.eflags = 0;
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#ifdef CONFIG_X86_PAE
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/* efer should match BSP efer. */
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|
if (cpu_has_nx) {
|
|
unsigned l, h;
|
|
rdmsr(MSR_EFER, l, h);
|
|
ap.efer = (unsigned long long) h << 32 | l;
|
|
}
|
|
#endif
|
|
|
|
ap.cr3 = __pa(swapper_pg_dir);
|
|
/* Protected mode, paging, AM, WP, NE, MP. */
|
|
ap.cr0 = 0x80050023;
|
|
ap.cr4 = mmu_cr4_features;
|
|
vmi_ops.set_initial_ap_state((u32)&ap, phys_apicid);
|
|
}
|
|
#endif
|
|
|
|
static void vmi_start_context_switch(struct task_struct *prev)
|
|
{
|
|
paravirt_start_context_switch(prev);
|
|
vmi_ops.set_lazy_mode(2);
|
|
}
|
|
|
|
static void vmi_end_context_switch(struct task_struct *next)
|
|
{
|
|
vmi_ops.set_lazy_mode(0);
|
|
paravirt_end_context_switch(next);
|
|
}
|
|
|
|
static void vmi_enter_lazy_mmu(void)
|
|
{
|
|
paravirt_enter_lazy_mmu();
|
|
vmi_ops.set_lazy_mode(1);
|
|
}
|
|
|
|
static void vmi_leave_lazy_mmu(void)
|
|
{
|
|
vmi_ops.set_lazy_mode(0);
|
|
paravirt_leave_lazy_mmu();
|
|
}
|
|
|
|
static inline int __init check_vmi_rom(struct vrom_header *rom)
|
|
{
|
|
struct pci_header *pci;
|
|
struct pnp_header *pnp;
|
|
const char *manufacturer = "UNKNOWN";
|
|
const char *product = "UNKNOWN";
|
|
const char *license = "unspecified";
|
|
|
|
if (rom->rom_signature != 0xaa55)
|
|
return 0;
|
|
if (rom->vrom_signature != VMI_SIGNATURE)
|
|
return 0;
|
|
if (rom->api_version_maj != VMI_API_REV_MAJOR ||
|
|
rom->api_version_min+1 < VMI_API_REV_MINOR+1) {
|
|
printk(KERN_WARNING "VMI: Found mismatched rom version %d.%d\n",
|
|
rom->api_version_maj,
|
|
rom->api_version_min);
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Relying on the VMI_SIGNATURE field is not 100% safe, so check
|
|
* the PCI header and device type to make sure this is really a
|
|
* VMI device.
|
|
*/
|
|
if (!rom->pci_header_offs) {
|
|
printk(KERN_WARNING "VMI: ROM does not contain PCI header.\n");
|
|
return 0;
|
|
}
|
|
|
|
pci = (struct pci_header *)((char *)rom+rom->pci_header_offs);
|
|
if (pci->vendorID != PCI_VENDOR_ID_VMWARE ||
|
|
pci->deviceID != PCI_DEVICE_ID_VMWARE_VMI) {
|
|
/* Allow it to run... anyways, but warn */
|
|
printk(KERN_WARNING "VMI: ROM from unknown manufacturer\n");
|
|
}
|
|
|
|
if (rom->pnp_header_offs) {
|
|
pnp = (struct pnp_header *)((char *)rom+rom->pnp_header_offs);
|
|
if (pnp->manufacturer_offset)
|
|
manufacturer = (const char *)rom+pnp->manufacturer_offset;
|
|
if (pnp->product_offset)
|
|
product = (const char *)rom+pnp->product_offset;
|
|
}
|
|
|
|
if (rom->license_offs)
|
|
license = (char *)rom+rom->license_offs;
|
|
|
|
printk(KERN_INFO "VMI: Found %s %s, API version %d.%d, ROM version %d.%d\n",
|
|
manufacturer, product,
|
|
rom->api_version_maj, rom->api_version_min,
|
|
pci->rom_version_maj, pci->rom_version_min);
|
|
|
|
/* Don't allow BSD/MIT here for now because we don't want to end up
|
|
with any binary only shim layers */
|
|
if (strcmp(license, "GPL") && strcmp(license, "GPL v2")) {
|
|
printk(KERN_WARNING "VMI: Non GPL license `%s' found for ROM. Not used.\n",
|
|
license);
|
|
return 0;
|
|
}
|
|
|
|
return 1;
|
|
}
|
|
|
|
/*
|
|
* Probe for the VMI option ROM
|
|
*/
|
|
static inline int __init probe_vmi_rom(void)
|
|
{
|
|
unsigned long base;
|
|
|
|
/* VMI ROM is in option ROM area, check signature */
|
|
for (base = 0xC0000; base < 0xE0000; base += 2048) {
|
|
struct vrom_header *romstart;
|
|
romstart = (struct vrom_header *)isa_bus_to_virt(base);
|
|
if (check_vmi_rom(romstart)) {
|
|
vmi_rom = romstart;
|
|
return 1;
|
|
}
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* VMI setup common to all processors
|
|
*/
|
|
void vmi_bringup(void)
|
|
{
|
|
/* We must establish the lowmem mapping for MMU ops to work */
|
|
if (vmi_ops.set_linear_mapping)
|
|
vmi_ops.set_linear_mapping(0, (void *)__PAGE_OFFSET, MAXMEM_PFN, 0);
|
|
}
|
|
|
|
/*
|
|
* Return a pointer to a VMI function or NULL if unimplemented
|
|
*/
|
|
static void *vmi_get_function(int vmicall)
|
|
{
|
|
u64 reloc;
|
|
const struct vmi_relocation_info *rel = (struct vmi_relocation_info *)&reloc;
|
|
reloc = call_vrom_long_func(vmi_rom, get_reloc, vmicall);
|
|
BUG_ON(rel->type == VMI_RELOCATION_JUMP_REL);
|
|
if (rel->type == VMI_RELOCATION_CALL_REL)
|
|
return (void *)rel->eip;
|
|
else
|
|
return NULL;
|
|
}
|
|
|
|
/*
|
|
* Helper macro for making the VMI paravirt-ops fill code readable.
|
|
* For unimplemented operations, fall back to default, unless nop
|
|
* is returned by the ROM.
|
|
*/
|
|
#define para_fill(opname, vmicall) \
|
|
do { \
|
|
reloc = call_vrom_long_func(vmi_rom, get_reloc, \
|
|
VMI_CALL_##vmicall); \
|
|
if (rel->type == VMI_RELOCATION_CALL_REL) \
|
|
opname = (void *)rel->eip; \
|
|
else if (rel->type == VMI_RELOCATION_NOP) \
|
|
opname = (void *)vmi_nop; \
|
|
else if (rel->type != VMI_RELOCATION_NONE) \
|
|
printk(KERN_WARNING "VMI: Unknown relocation " \
|
|
"type %d for " #vmicall"\n",\
|
|
rel->type); \
|
|
} while (0)
|
|
|
|
/*
|
|
* Helper macro for making the VMI paravirt-ops fill code readable.
|
|
* For cached operations which do not match the VMI ROM ABI and must
|
|
* go through a tranlation stub. Ignore NOPs, since it is not clear
|
|
* a NOP * VMI function corresponds to a NOP paravirt-op when the
|
|
* functions are not in 1-1 correspondence.
|
|
*/
|
|
#define para_wrap(opname, wrapper, cache, vmicall) \
|
|
do { \
|
|
reloc = call_vrom_long_func(vmi_rom, get_reloc, \
|
|
VMI_CALL_##vmicall); \
|
|
BUG_ON(rel->type == VMI_RELOCATION_JUMP_REL); \
|
|
if (rel->type == VMI_RELOCATION_CALL_REL) { \
|
|
opname = wrapper; \
|
|
vmi_ops.cache = (void *)rel->eip; \
|
|
} \
|
|
} while (0)
|
|
|
|
/*
|
|
* Activate the VMI interface and switch into paravirtualized mode
|
|
*/
|
|
static inline int __init activate_vmi(void)
|
|
{
|
|
short kernel_cs;
|
|
u64 reloc;
|
|
const struct vmi_relocation_info *rel = (struct vmi_relocation_info *)&reloc;
|
|
|
|
if (call_vrom_func(vmi_rom, vmi_init) != 0) {
|
|
printk(KERN_ERR "VMI ROM failed to initialize!");
|
|
return 0;
|
|
}
|
|
savesegment(cs, kernel_cs);
|
|
|
|
pv_info.paravirt_enabled = 1;
|
|
pv_info.kernel_rpl = kernel_cs & SEGMENT_RPL_MASK;
|
|
pv_info.name = "vmi";
|
|
|
|
pv_init_ops.patch = vmi_patch;
|
|
|
|
/*
|
|
* Many of these operations are ABI compatible with VMI.
|
|
* This means we can fill in the paravirt-ops with direct
|
|
* pointers into the VMI ROM. If the calling convention for
|
|
* these operations changes, this code needs to be updated.
|
|
*
|
|
* Exceptions
|
|
* CPUID paravirt-op uses pointers, not the native ISA
|
|
* halt has no VMI equivalent; all VMI halts are "safe"
|
|
* no MSR support yet - just trap and emulate. VMI uses the
|
|
* same ABI as the native ISA, but Linux wants exceptions
|
|
* from bogus MSR read / write handled
|
|
* rdpmc is not yet used in Linux
|
|
*/
|
|
|
|
/* CPUID is special, so very special it gets wrapped like a present */
|
|
para_wrap(pv_cpu_ops.cpuid, vmi_cpuid, cpuid, CPUID);
|
|
|
|
para_fill(pv_cpu_ops.clts, CLTS);
|
|
para_fill(pv_cpu_ops.get_debugreg, GetDR);
|
|
para_fill(pv_cpu_ops.set_debugreg, SetDR);
|
|
para_fill(pv_cpu_ops.read_cr0, GetCR0);
|
|
para_fill(pv_mmu_ops.read_cr2, GetCR2);
|
|
para_fill(pv_mmu_ops.read_cr3, GetCR3);
|
|
para_fill(pv_cpu_ops.read_cr4, GetCR4);
|
|
para_fill(pv_cpu_ops.write_cr0, SetCR0);
|
|
para_fill(pv_mmu_ops.write_cr2, SetCR2);
|
|
para_fill(pv_mmu_ops.write_cr3, SetCR3);
|
|
para_fill(pv_cpu_ops.write_cr4, SetCR4);
|
|
|
|
para_fill(pv_irq_ops.save_fl.func, GetInterruptMask);
|
|
para_fill(pv_irq_ops.restore_fl.func, SetInterruptMask);
|
|
para_fill(pv_irq_ops.irq_disable.func, DisableInterrupts);
|
|
para_fill(pv_irq_ops.irq_enable.func, EnableInterrupts);
|
|
|
|
para_fill(pv_cpu_ops.wbinvd, WBINVD);
|
|
para_fill(pv_cpu_ops.read_tsc, RDTSC);
|
|
|
|
/* The following we emulate with trap and emulate for now */
|
|
/* paravirt_ops.read_msr = vmi_rdmsr */
|
|
/* paravirt_ops.write_msr = vmi_wrmsr */
|
|
/* paravirt_ops.rdpmc = vmi_rdpmc */
|
|
|
|
/* TR interface doesn't pass TR value, wrap */
|
|
para_wrap(pv_cpu_ops.load_tr_desc, vmi_set_tr, set_tr, SetTR);
|
|
|
|
/* LDT is special, too */
|
|
para_wrap(pv_cpu_ops.set_ldt, vmi_set_ldt, _set_ldt, SetLDT);
|
|
|
|
para_fill(pv_cpu_ops.load_gdt, SetGDT);
|
|
para_fill(pv_cpu_ops.load_idt, SetIDT);
|
|
para_fill(pv_cpu_ops.store_gdt, GetGDT);
|
|
para_fill(pv_cpu_ops.store_idt, GetIDT);
|
|
para_fill(pv_cpu_ops.store_tr, GetTR);
|
|
pv_cpu_ops.load_tls = vmi_load_tls;
|
|
para_wrap(pv_cpu_ops.write_ldt_entry, vmi_write_ldt_entry,
|
|
write_ldt_entry, WriteLDTEntry);
|
|
para_wrap(pv_cpu_ops.write_gdt_entry, vmi_write_gdt_entry,
|
|
write_gdt_entry, WriteGDTEntry);
|
|
para_wrap(pv_cpu_ops.write_idt_entry, vmi_write_idt_entry,
|
|
write_idt_entry, WriteIDTEntry);
|
|
para_wrap(pv_cpu_ops.load_sp0, vmi_load_sp0, set_kernel_stack, UpdateKernelStack);
|
|
para_fill(pv_cpu_ops.set_iopl_mask, SetIOPLMask);
|
|
para_fill(pv_cpu_ops.io_delay, IODelay);
|
|
|
|
para_wrap(pv_cpu_ops.start_context_switch, vmi_start_context_switch,
|
|
set_lazy_mode, SetLazyMode);
|
|
para_wrap(pv_cpu_ops.end_context_switch, vmi_end_context_switch,
|
|
set_lazy_mode, SetLazyMode);
|
|
|
|
para_wrap(pv_mmu_ops.lazy_mode.enter, vmi_enter_lazy_mmu,
|
|
set_lazy_mode, SetLazyMode);
|
|
para_wrap(pv_mmu_ops.lazy_mode.leave, vmi_leave_lazy_mmu,
|
|
set_lazy_mode, SetLazyMode);
|
|
|
|
/* user and kernel flush are just handled with different flags to FlushTLB */
|
|
para_wrap(pv_mmu_ops.flush_tlb_user, vmi_flush_tlb_user, _flush_tlb, FlushTLB);
|
|
para_wrap(pv_mmu_ops.flush_tlb_kernel, vmi_flush_tlb_kernel, _flush_tlb, FlushTLB);
|
|
para_fill(pv_mmu_ops.flush_tlb_single, InvalPage);
|
|
|
|
/*
|
|
* Until a standard flag format can be agreed on, we need to
|
|
* implement these as wrappers in Linux. Get the VMI ROM
|
|
* function pointers for the two backend calls.
|
|
*/
|
|
#ifdef CONFIG_X86_PAE
|
|
vmi_ops.set_pte = vmi_get_function(VMI_CALL_SetPxELong);
|
|
vmi_ops.update_pte = vmi_get_function(VMI_CALL_UpdatePxELong);
|
|
#else
|
|
vmi_ops.set_pte = vmi_get_function(VMI_CALL_SetPxE);
|
|
vmi_ops.update_pte = vmi_get_function(VMI_CALL_UpdatePxE);
|
|
#endif
|
|
|
|
if (vmi_ops.set_pte) {
|
|
pv_mmu_ops.set_pte = vmi_set_pte;
|
|
pv_mmu_ops.set_pte_at = vmi_set_pte_at;
|
|
pv_mmu_ops.set_pmd = vmi_set_pmd;
|
|
#ifdef CONFIG_X86_PAE
|
|
pv_mmu_ops.set_pte_atomic = vmi_set_pte_atomic;
|
|
pv_mmu_ops.set_pud = vmi_set_pud;
|
|
pv_mmu_ops.pte_clear = vmi_pte_clear;
|
|
pv_mmu_ops.pmd_clear = vmi_pmd_clear;
|
|
#endif
|
|
}
|
|
|
|
if (vmi_ops.update_pte) {
|
|
pv_mmu_ops.pte_update = vmi_update_pte;
|
|
pv_mmu_ops.pte_update_defer = vmi_update_pte_defer;
|
|
}
|
|
|
|
vmi_ops.allocate_page = vmi_get_function(VMI_CALL_AllocatePage);
|
|
if (vmi_ops.allocate_page) {
|
|
pv_mmu_ops.alloc_pte = vmi_allocate_pte;
|
|
pv_mmu_ops.alloc_pmd = vmi_allocate_pmd;
|
|
pv_mmu_ops.alloc_pmd_clone = vmi_allocate_pmd_clone;
|
|
}
|
|
|
|
vmi_ops.release_page = vmi_get_function(VMI_CALL_ReleasePage);
|
|
if (vmi_ops.release_page) {
|
|
pv_mmu_ops.release_pte = vmi_release_pte;
|
|
pv_mmu_ops.release_pmd = vmi_release_pmd;
|
|
pv_mmu_ops.pgd_free = vmi_pgd_free;
|
|
}
|
|
|
|
/* Set linear is needed in all cases */
|
|
vmi_ops.set_linear_mapping = vmi_get_function(VMI_CALL_SetLinearMapping);
|
|
#ifdef CONFIG_HIGHPTE
|
|
if (vmi_ops.set_linear_mapping)
|
|
pv_mmu_ops.kmap_atomic_pte = vmi_kmap_atomic_pte;
|
|
#endif
|
|
|
|
/*
|
|
* These MUST always be patched. Don't support indirect jumps
|
|
* through these operations, as the VMI interface may use either
|
|
* a jump or a call to get to these operations, depending on
|
|
* the backend. They are performance critical anyway, so requiring
|
|
* a patch is not a big problem.
|
|
*/
|
|
pv_cpu_ops.irq_enable_sysexit = (void *)0xfeedbab0;
|
|
pv_cpu_ops.iret = (void *)0xbadbab0;
|
|
|
|
#ifdef CONFIG_SMP
|
|
para_wrap(pv_apic_ops.startup_ipi_hook, vmi_startup_ipi_hook, set_initial_ap_state, SetInitialAPState);
|
|
#endif
|
|
|
|
#ifdef CONFIG_X86_LOCAL_APIC
|
|
para_fill(apic->read, APICRead);
|
|
para_fill(apic->write, APICWrite);
|
|
#endif
|
|
|
|
/*
|
|
* Check for VMI timer functionality by probing for a cycle frequency method
|
|
*/
|
|
reloc = call_vrom_long_func(vmi_rom, get_reloc, VMI_CALL_GetCycleFrequency);
|
|
if (!disable_vmi_timer && rel->type != VMI_RELOCATION_NONE) {
|
|
vmi_timer_ops.get_cycle_frequency = (void *)rel->eip;
|
|
vmi_timer_ops.get_cycle_counter =
|
|
vmi_get_function(VMI_CALL_GetCycleCounter);
|
|
vmi_timer_ops.get_wallclock =
|
|
vmi_get_function(VMI_CALL_GetWallclockTime);
|
|
vmi_timer_ops.wallclock_updated =
|
|
vmi_get_function(VMI_CALL_WallclockUpdated);
|
|
vmi_timer_ops.set_alarm = vmi_get_function(VMI_CALL_SetAlarm);
|
|
vmi_timer_ops.cancel_alarm =
|
|
vmi_get_function(VMI_CALL_CancelAlarm);
|
|
pv_time_ops.time_init = vmi_time_init;
|
|
pv_time_ops.get_wallclock = vmi_get_wallclock;
|
|
pv_time_ops.set_wallclock = vmi_set_wallclock;
|
|
#ifdef CONFIG_X86_LOCAL_APIC
|
|
pv_apic_ops.setup_boot_clock = vmi_time_bsp_init;
|
|
pv_apic_ops.setup_secondary_clock = vmi_time_ap_init;
|
|
#endif
|
|
pv_time_ops.sched_clock = vmi_sched_clock;
|
|
pv_time_ops.get_tsc_khz = vmi_tsc_khz;
|
|
|
|
/* We have true wallclock functions; disable CMOS clock sync */
|
|
no_sync_cmos_clock = 1;
|
|
} else {
|
|
disable_noidle = 1;
|
|
disable_vmi_timer = 1;
|
|
}
|
|
|
|
para_fill(pv_irq_ops.safe_halt, Halt);
|
|
|
|
/*
|
|
* Alternative instruction rewriting doesn't happen soon enough
|
|
* to convert VMI_IRET to a call instead of a jump; so we have
|
|
* to do this before IRQs get reenabled. Fortunately, it is
|
|
* idempotent.
|
|
*/
|
|
apply_paravirt(__parainstructions, __parainstructions_end);
|
|
|
|
vmi_bringup();
|
|
|
|
return 1;
|
|
}
|
|
|
|
#undef para_fill
|
|
|
|
void __init vmi_init(void)
|
|
{
|
|
if (!vmi_rom)
|
|
probe_vmi_rom();
|
|
else
|
|
check_vmi_rom(vmi_rom);
|
|
|
|
/* In case probing for or validating the ROM failed, basil */
|
|
if (!vmi_rom)
|
|
return;
|
|
|
|
reserve_top_address(-vmi_rom->virtual_top);
|
|
|
|
#ifdef CONFIG_X86_IO_APIC
|
|
/* This is virtual hardware; timer routing is wired correctly */
|
|
no_timer_check = 1;
|
|
#endif
|
|
}
|
|
|
|
void __init vmi_activate(void)
|
|
{
|
|
unsigned long flags;
|
|
|
|
if (!vmi_rom)
|
|
return;
|
|
|
|
local_irq_save(flags);
|
|
activate_vmi();
|
|
local_irq_restore(flags & X86_EFLAGS_IF);
|
|
}
|
|
|
|
static int __init parse_vmi(char *arg)
|
|
{
|
|
if (!arg)
|
|
return -EINVAL;
|
|
|
|
if (!strcmp(arg, "disable_pge")) {
|
|
clear_cpu_cap(&boot_cpu_data, X86_FEATURE_PGE);
|
|
disable_pge = 1;
|
|
} else if (!strcmp(arg, "disable_pse")) {
|
|
clear_cpu_cap(&boot_cpu_data, X86_FEATURE_PSE);
|
|
disable_pse = 1;
|
|
} else if (!strcmp(arg, "disable_sep")) {
|
|
clear_cpu_cap(&boot_cpu_data, X86_FEATURE_SEP);
|
|
disable_sep = 1;
|
|
} else if (!strcmp(arg, "disable_tsc")) {
|
|
clear_cpu_cap(&boot_cpu_data, X86_FEATURE_TSC);
|
|
disable_tsc = 1;
|
|
} else if (!strcmp(arg, "disable_mtrr")) {
|
|
clear_cpu_cap(&boot_cpu_data, X86_FEATURE_MTRR);
|
|
disable_mtrr = 1;
|
|
} else if (!strcmp(arg, "disable_timer")) {
|
|
disable_vmi_timer = 1;
|
|
disable_noidle = 1;
|
|
} else if (!strcmp(arg, "disable_noidle"))
|
|
disable_noidle = 1;
|
|
return 0;
|
|
}
|
|
|
|
early_param("vmi", parse_vmi);
|