![Will Deacon](/assets/img/avatar_default.png)
Now that we have arm-smmu.h defining various SMMU constants, ensure that they are namespaced with the ARM_SMMU_ prefix in order to avoid conflicts with the CPU, such as the one we're currently bodging around with the TCR. Cc: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Will Deacon <will@kernel.org>
178 lines
4.4 KiB
C
178 lines
4.4 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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// Miscellaneous Arm SMMU implementation and integration quirks
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// Copyright (C) 2019 Arm Limited
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#define pr_fmt(fmt) "arm-smmu: " fmt
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#include <linux/bitfield.h>
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#include <linux/of.h>
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#include "arm-smmu.h"
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static int arm_smmu_gr0_ns(int offset)
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{
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switch(offset) {
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case ARM_SMMU_GR0_sCR0:
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case ARM_SMMU_GR0_sACR:
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case ARM_SMMU_GR0_sGFSR:
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case ARM_SMMU_GR0_sGFSYNR0:
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case ARM_SMMU_GR0_sGFSYNR1:
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case ARM_SMMU_GR0_sGFSYNR2:
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return offset + 0x400;
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default:
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return offset;
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}
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}
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static u32 arm_smmu_read_ns(struct arm_smmu_device *smmu, int page,
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int offset)
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{
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if (page == ARM_SMMU_GR0)
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offset = arm_smmu_gr0_ns(offset);
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return readl_relaxed(arm_smmu_page(smmu, page) + offset);
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}
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static void arm_smmu_write_ns(struct arm_smmu_device *smmu, int page,
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int offset, u32 val)
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{
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if (page == ARM_SMMU_GR0)
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offset = arm_smmu_gr0_ns(offset);
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writel_relaxed(val, arm_smmu_page(smmu, page) + offset);
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}
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/* Since we don't care for sGFAR, we can do without 64-bit accessors */
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static const struct arm_smmu_impl calxeda_impl = {
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.read_reg = arm_smmu_read_ns,
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.write_reg = arm_smmu_write_ns,
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};
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struct cavium_smmu {
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struct arm_smmu_device smmu;
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u32 id_base;
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};
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static int cavium_cfg_probe(struct arm_smmu_device *smmu)
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{
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static atomic_t context_count = ATOMIC_INIT(0);
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struct cavium_smmu *cs = container_of(smmu, struct cavium_smmu, smmu);
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/*
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* Cavium CN88xx erratum #27704.
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* Ensure ASID and VMID allocation is unique across all SMMUs in
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* the system.
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*/
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cs->id_base = atomic_fetch_add(smmu->num_context_banks, &context_count);
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dev_notice(smmu->dev, "\tenabling workaround for Cavium erratum 27704\n");
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return 0;
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}
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static int cavium_init_context(struct arm_smmu_domain *smmu_domain)
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{
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struct cavium_smmu *cs = container_of(smmu_domain->smmu,
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struct cavium_smmu, smmu);
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if (smmu_domain->stage == ARM_SMMU_DOMAIN_S2)
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smmu_domain->cfg.vmid += cs->id_base;
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else
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smmu_domain->cfg.asid += cs->id_base;
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return 0;
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}
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static const struct arm_smmu_impl cavium_impl = {
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.cfg_probe = cavium_cfg_probe,
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.init_context = cavium_init_context,
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};
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static struct arm_smmu_device *cavium_smmu_impl_init(struct arm_smmu_device *smmu)
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{
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struct cavium_smmu *cs;
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cs = devm_kzalloc(smmu->dev, sizeof(*cs), GFP_KERNEL);
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if (!cs)
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return ERR_PTR(-ENOMEM);
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cs->smmu = *smmu;
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cs->smmu.impl = &cavium_impl;
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devm_kfree(smmu->dev, smmu);
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return &cs->smmu;
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}
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#define ARM_MMU500_ACTLR_CPRE (1 << 1)
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#define ARM_MMU500_ACR_CACHE_LOCK (1 << 26)
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#define ARM_MMU500_ACR_S2CRB_TLBEN (1 << 10)
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#define ARM_MMU500_ACR_SMTNMB_TLBEN (1 << 8)
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int arm_mmu500_reset(struct arm_smmu_device *smmu)
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{
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u32 reg, major;
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int i;
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/*
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* On MMU-500 r2p0 onwards we need to clear ACR.CACHE_LOCK before
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* writes to the context bank ACTLRs will stick. And we just hope that
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* Secure has also cleared SACR.CACHE_LOCK for this to take effect...
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*/
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reg = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_ID7);
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major = FIELD_GET(ARM_SMMU_ID7_MAJOR, reg);
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reg = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_sACR);
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if (major >= 2)
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reg &= ~ARM_MMU500_ACR_CACHE_LOCK;
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/*
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* Allow unmatched Stream IDs to allocate bypass
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* TLB entries for reduced latency.
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*/
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reg |= ARM_MMU500_ACR_SMTNMB_TLBEN | ARM_MMU500_ACR_S2CRB_TLBEN;
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arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_sACR, reg);
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/*
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* Disable MMU-500's not-particularly-beneficial next-page
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* prefetcher for the sake of errata #841119 and #826419.
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*/
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for (i = 0; i < smmu->num_context_banks; ++i) {
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reg = arm_smmu_cb_read(smmu, i, ARM_SMMU_CB_ACTLR);
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reg &= ~ARM_MMU500_ACTLR_CPRE;
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arm_smmu_cb_write(smmu, i, ARM_SMMU_CB_ACTLR, reg);
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}
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return 0;
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}
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static const struct arm_smmu_impl arm_mmu500_impl = {
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.reset = arm_mmu500_reset,
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};
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struct arm_smmu_device *arm_smmu_impl_init(struct arm_smmu_device *smmu)
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{
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/*
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* We will inevitably have to combine model-specific implementation
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* quirks with platform-specific integration quirks, but everything
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* we currently support happens to work out as straightforward
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* mutually-exclusive assignments.
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*/
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switch (smmu->model) {
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case ARM_MMU500:
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smmu->impl = &arm_mmu500_impl;
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break;
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case CAVIUM_SMMUV2:
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return cavium_smmu_impl_init(smmu);
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default:
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break;
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}
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if (of_property_read_bool(smmu->dev->of_node,
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"calxeda,smmu-secure-config-access"))
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smmu->impl = &calxeda_impl;
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if (of_device_is_compatible(smmu->dev->of_node, "qcom,sdm845-smmu-500"))
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return qcom_smmu_impl_init(smmu);
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return smmu;
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}
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