![Jiaxun Yang](/assets/img/avatar_default.png)
The 1.0 version of that controller has a bug that status bit of LPC IRQ sometimes doesn't get set correctly. So we can always blame LPC IRQ when spurious interrupt happens at the parent interrupt line which LPC IRQ supposed to route to. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Co-developed-by: Huacai Chen <chenhc@lemote.com> Signed-off-by: Huacai Chen <chenhc@lemote.com> Reviewed-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
272 lines
6.9 KiB
C
272 lines
6.9 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2020, Jiaxun Yang <jiaxun.yang@flygoat.com>
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* Loongson Local IO Interrupt Controller support
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*/
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#include <linux/errno.h>
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#include <linux/init.h>
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#include <linux/types.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/irqchip.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/io.h>
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#include <linux/smp.h>
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#include <linux/irqchip/chained_irq.h>
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#include <boot_param.h>
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#define LIOINTC_CHIP_IRQ 32
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#define LIOINTC_NUM_PARENT 4
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#define LIOINTC_INTC_CHIP_START 0x20
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#define LIOINTC_REG_INTC_STATUS (LIOINTC_INTC_CHIP_START + 0x20)
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#define LIOINTC_REG_INTC_EN_STATUS (LIOINTC_INTC_CHIP_START + 0x04)
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#define LIOINTC_REG_INTC_ENABLE (LIOINTC_INTC_CHIP_START + 0x08)
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#define LIOINTC_REG_INTC_DISABLE (LIOINTC_INTC_CHIP_START + 0x0c)
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#define LIOINTC_REG_INTC_POL (LIOINTC_INTC_CHIP_START + 0x10)
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#define LIOINTC_REG_INTC_EDGE (LIOINTC_INTC_CHIP_START + 0x14)
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#define LIOINTC_SHIFT_INTx 4
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#define LIOINTC_ERRATA_IRQ 10
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struct liointc_handler_data {
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struct liointc_priv *priv;
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u32 parent_int_map;
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};
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struct liointc_priv {
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struct irq_chip_generic *gc;
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struct liointc_handler_data handler[LIOINTC_NUM_PARENT];
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u8 map_cache[LIOINTC_CHIP_IRQ];
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bool has_lpc_irq_errata;
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};
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static void liointc_chained_handle_irq(struct irq_desc *desc)
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{
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struct liointc_handler_data *handler = irq_desc_get_handler_data(desc);
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struct irq_chip *chip = irq_desc_get_chip(desc);
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struct irq_chip_generic *gc = handler->priv->gc;
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u32 pending;
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chained_irq_enter(chip, desc);
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pending = readl(gc->reg_base + LIOINTC_REG_INTC_STATUS);
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if (!pending) {
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/* Always blame LPC IRQ if we have that bug */
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if (handler->priv->has_lpc_irq_errata &&
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(handler->parent_int_map & ~gc->mask_cache &
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BIT(LIOINTC_ERRATA_IRQ)))
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pending = BIT(LIOINTC_ERRATA_IRQ);
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else
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spurious_interrupt();
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}
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while (pending) {
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int bit = __ffs(pending);
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generic_handle_irq(irq_find_mapping(gc->domain, bit));
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pending &= ~BIT(bit);
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}
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chained_irq_exit(chip, desc);
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}
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static void liointc_set_bit(struct irq_chip_generic *gc,
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unsigned int offset,
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u32 mask, bool set)
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{
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if (set)
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writel(readl(gc->reg_base + offset) | mask,
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gc->reg_base + offset);
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else
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writel(readl(gc->reg_base + offset) & ~mask,
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gc->reg_base + offset);
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}
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static int liointc_set_type(struct irq_data *data, unsigned int type)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
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u32 mask = data->mask;
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unsigned long flags;
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irq_gc_lock_irqsave(gc, flags);
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switch (type) {
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case IRQ_TYPE_LEVEL_HIGH:
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liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, false);
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liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, true);
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break;
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case IRQ_TYPE_LEVEL_LOW:
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liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, false);
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liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, false);
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break;
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case IRQ_TYPE_EDGE_RISING:
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liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, true);
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liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, true);
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break;
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case IRQ_TYPE_EDGE_FALLING:
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liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, true);
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liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, false);
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break;
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default:
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return -EINVAL;
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}
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irq_gc_unlock_irqrestore(gc, flags);
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irqd_set_trigger_type(data, type);
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return 0;
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}
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static void liointc_resume(struct irq_chip_generic *gc)
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{
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struct liointc_priv *priv = gc->private;
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unsigned long flags;
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int i;
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irq_gc_lock_irqsave(gc, flags);
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/* Disable all at first */
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writel(0xffffffff, gc->reg_base + LIOINTC_REG_INTC_DISABLE);
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/* Revert map cache */
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for (i = 0; i < LIOINTC_CHIP_IRQ; i++)
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writeb(priv->map_cache[i], gc->reg_base + i);
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/* Revert mask cache */
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writel(~gc->mask_cache, gc->reg_base + LIOINTC_REG_INTC_ENABLE);
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irq_gc_unlock_irqrestore(gc, flags);
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}
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static const char * const parent_names[] = {"int0", "int1", "int2", "int3"};
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int __init liointc_of_init(struct device_node *node,
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struct device_node *parent)
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{
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struct irq_chip_generic *gc;
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struct irq_domain *domain;
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struct irq_chip_type *ct;
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struct liointc_priv *priv;
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void __iomem *base;
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u32 of_parent_int_map[LIOINTC_NUM_PARENT];
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int parent_irq[LIOINTC_NUM_PARENT];
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bool have_parent = FALSE;
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int sz, i, err = 0;
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priv = kzalloc(sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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base = of_iomap(node, 0);
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if (!base) {
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err = -ENODEV;
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goto out_free_priv;
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}
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for (i = 0; i < LIOINTC_NUM_PARENT; i++) {
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parent_irq[i] = of_irq_get_byname(node, parent_names[i]);
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if (parent_irq[i] > 0)
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have_parent = TRUE;
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}
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if (!have_parent) {
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err = -ENODEV;
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goto out_iounmap;
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}
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sz = of_property_read_variable_u32_array(node,
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"loongson,parent_int_map",
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&of_parent_int_map[0],
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LIOINTC_NUM_PARENT,
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LIOINTC_NUM_PARENT);
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if (sz < 4) {
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pr_err("loongson-liointc: No parent_int_map\n");
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err = -ENODEV;
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goto out_iounmap;
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}
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for (i = 0; i < LIOINTC_NUM_PARENT; i++)
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priv->handler[i].parent_int_map = of_parent_int_map[i];
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/* Setup IRQ domain */
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domain = irq_domain_add_linear(node, 32,
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&irq_generic_chip_ops, priv);
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if (!domain) {
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pr_err("loongson-liointc: cannot add IRQ domain\n");
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err = -EINVAL;
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goto out_iounmap;
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}
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err = irq_alloc_domain_generic_chips(domain, 32, 1,
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node->full_name, handle_level_irq,
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IRQ_NOPROBE, 0, 0);
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if (err) {
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pr_err("loongson-liointc: unable to register IRQ domain\n");
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goto out_free_domain;
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}
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/* Disable all IRQs */
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writel(0xffffffff, base + LIOINTC_REG_INTC_DISABLE);
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/* Set to level triggered */
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writel(0x0, base + LIOINTC_REG_INTC_EDGE);
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/* Generate parent INT part of map cache */
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for (i = 0; i < LIOINTC_NUM_PARENT; i++) {
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u32 pending = priv->handler[i].parent_int_map;
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while (pending) {
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int bit = __ffs(pending);
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priv->map_cache[bit] = BIT(i) << LIOINTC_SHIFT_INTx;
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pending &= ~BIT(bit);
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}
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}
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for (i = 0; i < LIOINTC_CHIP_IRQ; i++) {
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/* Generate core part of map cache */
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priv->map_cache[i] |= BIT(loongson_sysconf.boot_cpu_id);
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writeb(priv->map_cache[i], base + i);
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}
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gc = irq_get_domain_generic_chip(domain, 0);
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gc->private = priv;
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gc->reg_base = base;
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gc->domain = domain;
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gc->resume = liointc_resume;
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ct = gc->chip_types;
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ct->regs.enable = LIOINTC_REG_INTC_ENABLE;
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ct->regs.disable = LIOINTC_REG_INTC_DISABLE;
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ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
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ct->chip.irq_mask = irq_gc_mask_disable_reg;
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ct->chip.irq_mask_ack = irq_gc_mask_disable_reg;
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ct->chip.irq_set_type = liointc_set_type;
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gc->mask_cache = 0xffffffff;
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priv->gc = gc;
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for (i = 0; i < LIOINTC_NUM_PARENT; i++) {
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if (parent_irq[i] <= 0)
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continue;
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priv->handler[i].priv = priv;
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irq_set_chained_handler_and_data(parent_irq[i],
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liointc_chained_handle_irq, &priv->handler[i]);
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}
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return 0;
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out_free_domain:
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irq_domain_remove(domain);
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out_iounmap:
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iounmap(base);
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out_free_priv:
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kfree(priv);
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return err;
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}
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IRQCHIP_DECLARE(loongson_liointc_1_0, "loongson,liointc-1.0", liointc_of_init);
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IRQCHIP_DECLARE(loongson_liointc_1_0a, "loongson,liointc-1.0a", liointc_of_init);
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