46350b71a0
Table 8 from MX6DL datasheet (IMX6SDLCEC Rev. 5, 06/2015): http://cache.nxp.com/files/32bit/doc/data_sheet/IMX6SDLCEC.pdf states the following: "LDO Output Set Point (VDD_ARM_CAP) = 1.125 V minimum for operation up to 396 MHz." So fix the entry by adding the 25mV margin value as done in the other entries of the table, which results in 1.15V for 396MHz operation. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
134 lines
2.8 KiB
Plaintext
134 lines
2.8 KiB
Plaintext
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/*
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* Copyright 2013 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <dt-bindings/interrupt-controller/irq.h>
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#include "imx6dl-pinfunc.h"
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#include "imx6qdl.dtsi"
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/ {
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aliases {
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i2c3 = &i2c4;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "arm,cortex-a9";
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device_type = "cpu";
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reg = <0>;
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next-level-cache = <&L2>;
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operating-points = <
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/* kHz uV */
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996000 1250000
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792000 1175000
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396000 1150000
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>;
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fsl,soc-operating-points = <
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/* ARM kHz SOC-PU uV */
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996000 1175000
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792000 1175000
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396000 1175000
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>;
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clock-latency = <61036>; /* two CLK32 periods */
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clocks = <&clks IMX6QDL_CLK_ARM>,
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<&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
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<&clks IMX6QDL_CLK_STEP>,
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<&clks IMX6QDL_CLK_PLL1_SW>,
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<&clks IMX6QDL_CLK_PLL1_SYS>;
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clock-names = "arm", "pll2_pfd2_396m", "step",
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"pll1_sw", "pll1_sys";
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arm-supply = <®_arm>;
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pu-supply = <®_pu>;
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soc-supply = <®_soc>;
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};
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cpu@1 {
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compatible = "arm,cortex-a9";
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device_type = "cpu";
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reg = <1>;
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next-level-cache = <&L2>;
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};
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};
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soc {
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ocram: sram@00900000 {
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compatible = "mmio-sram";
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reg = <0x00900000 0x20000>;
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clocks = <&clks IMX6QDL_CLK_OCRAM>;
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};
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aips1: aips-bus@02000000 {
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iomuxc: iomuxc@020e0000 {
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compatible = "fsl,imx6dl-iomuxc";
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};
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pxp: pxp@020f0000 {
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reg = <0x020f0000 0x4000>;
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interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
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};
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epdc: epdc@020f4000 {
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reg = <0x020f4000 0x4000>;
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interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
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};
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lcdif: lcdif@020f8000 {
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reg = <0x020f8000 0x4000>;
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interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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aips2: aips-bus@02100000 {
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i2c4: i2c@021f8000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
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reg = <0x021f8000 0x4000>;
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interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX6DL_CLK_I2C4>;
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status = "disabled";
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};
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};
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};
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display-subsystem {
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compatible = "fsl,imx-display-subsystem";
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ports = <&ipu1_di0>, <&ipu1_di1>;
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};
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gpu-subsystem {
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compatible = "fsl,imx-gpu-subsystem";
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cores = <&gpu_2d>, <&gpu_3d>;
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};
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};
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&gpt {
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compatible = "fsl,imx6dl-gpt";
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};
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&hdmi {
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compatible = "fsl,imx6dl-hdmi";
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};
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&ldb {
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clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
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<&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
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<&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>;
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clock-names = "di0_pll", "di1_pll",
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"di0_sel", "di1_sel",
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"di0", "di1";
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};
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&vpu {
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compatible = "fsl,imx6dl-vpu", "cnm,coda960";
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};
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