34d5003bfb
The debug base clock can be bypassed from the main PLL to the OSC1 clock. The bypass register is the staysoc1(0x10) register that is in the clock manager. This patch adds the option to get the correct parent for the debug base clock. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
120 lines
3 KiB
C
120 lines
3 KiB
C
/*
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* Copyright 2011-2012 Calxeda, Inc.
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* Copyright (C) 2012-2013 Altera Corporation <www.altera.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Based from clk-highbank.c
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*
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*/
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#include <linux/slab.h>
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include "clk.h"
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#define to_socfpga_periph_clk(p) container_of(p, struct socfpga_periph_clk, hw.hw)
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static unsigned long clk_periclk_recalc_rate(struct clk_hw *hwclk,
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unsigned long parent_rate)
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{
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struct socfpga_periph_clk *socfpgaclk = to_socfpga_periph_clk(hwclk);
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u32 div, val;
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if (socfpgaclk->fixed_div) {
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div = socfpgaclk->fixed_div;
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} else {
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if (socfpgaclk->div_reg) {
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val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
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val &= GENMASK(socfpgaclk->width - 1, 0);
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parent_rate /= (val + 1);
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}
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div = ((readl(socfpgaclk->hw.reg) & 0x1ff) + 1);
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}
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return parent_rate / div;
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}
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static u8 clk_periclk_get_parent(struct clk_hw *hwclk)
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{
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u32 clk_src;
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clk_src = readl(clk_mgr_base_addr + CLKMGR_DBCTRL);
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return clk_src & 0x1;
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}
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static const struct clk_ops periclk_ops = {
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.recalc_rate = clk_periclk_recalc_rate,
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.get_parent = clk_periclk_get_parent,
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};
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static __init void __socfpga_periph_init(struct device_node *node,
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const struct clk_ops *ops)
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{
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u32 reg;
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struct clk *clk;
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struct socfpga_periph_clk *periph_clk;
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const char *clk_name = node->name;
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const char *parent_name[SOCFPGA_MAX_PARENTS];
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struct clk_init_data init;
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int rc;
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u32 fixed_div;
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u32 div_reg[3];
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of_property_read_u32(node, "reg", ®);
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periph_clk = kzalloc(sizeof(*periph_clk), GFP_KERNEL);
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if (WARN_ON(!periph_clk))
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return;
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periph_clk->hw.reg = clk_mgr_base_addr + reg;
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rc = of_property_read_u32_array(node, "div-reg", div_reg, 3);
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if (!rc) {
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periph_clk->div_reg = clk_mgr_base_addr + div_reg[0];
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periph_clk->shift = div_reg[1];
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periph_clk->width = div_reg[2];
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} else {
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periph_clk->div_reg = NULL;
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}
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rc = of_property_read_u32(node, "fixed-divider", &fixed_div);
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if (rc)
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periph_clk->fixed_div = 0;
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else
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periph_clk->fixed_div = fixed_div;
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of_property_read_string(node, "clock-output-names", &clk_name);
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init.name = clk_name;
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init.ops = ops;
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init.flags = 0;
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init.num_parents = of_clk_parent_fill(node, parent_name,
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SOCFPGA_MAX_PARENTS);
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init.parent_names = parent_name;
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periph_clk->hw.hw.init = &init;
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clk = clk_register(NULL, &periph_clk->hw.hw);
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if (WARN_ON(IS_ERR(clk))) {
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kfree(periph_clk);
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return;
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}
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rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
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}
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void __init socfpga_periph_init(struct device_node *node)
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{
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__socfpga_periph_init(node, &periclk_ops);
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}
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