554c0a3abf
The rtl8723bs is found on quite a few systems used by Linux users, such as on Atom systems (Intel Computestick and various other Atom based devices) and on many (budget) ARM boards such as the CHIP. The plan moving forward with this is for the new clean, written from scratch, rtl8xxxu driver to eventually gain support for sdio devices. But there is no clear timeline for that, so lets add this driver included in staging for now. Cc: Bastien Nocera <hadess@hadess.net> Cc: Larry Finger <Larry.Finger@lwfinger.net> Cc: Jes Sorensen <jes.sorensen@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
119 lines
4.4 KiB
C
119 lines
4.4 KiB
C
/******************************************************************************
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*
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* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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******************************************************************************/
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#ifndef _RTW_HT_H_
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#define _RTW_HT_H_
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struct ht_priv
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{
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u8 ht_option;
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u8 ampdu_enable;/* for enable Tx A-MPDU */
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u8 tx_amsdu_enable;/* for enable Tx A-MSDU */
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u8 bss_coexist;/* for 20/40 Bss coexist */
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/* u8 baddbareq_issued[16]; */
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u32 tx_amsdu_maxlen; /* 1: 8k, 0:4k ; default:8k, for tx */
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u32 rx_ampdu_maxlen; /* for rx reordering ctrl win_sz, updated when join_callback. */
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u8 rx_ampdu_min_spacing;
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u8 ch_offset;/* PRIME_CHNL_OFFSET */
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u8 sgi_20m;
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u8 sgi_40m;
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/* for processing Tx A-MPDU */
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u8 agg_enable_bitmap;
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/* u8 ADDBA_retry_count; */
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u8 candidate_tid_bitmap;
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u8 ldpc_cap;
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u8 stbc_cap;
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u8 beamform_cap;
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struct rtw_ieee80211_ht_cap ht_cap;
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};
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typedef enum AGGRE_SIZE{
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HT_AGG_SIZE_8K = 0,
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HT_AGG_SIZE_16K = 1,
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HT_AGG_SIZE_32K = 2,
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HT_AGG_SIZE_64K = 3,
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VHT_AGG_SIZE_128K = 4,
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VHT_AGG_SIZE_256K = 5,
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VHT_AGG_SIZE_512K = 6,
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VHT_AGG_SIZE_1024K = 7,
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}AGGRE_SIZE_E, *PAGGRE_SIZE_E;
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typedef enum _RT_HT_INF0_CAP{
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RT_HT_CAP_USE_TURBO_AGGR = 0x01,
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RT_HT_CAP_USE_LONG_PREAMBLE = 0x02,
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RT_HT_CAP_USE_AMPDU = 0x04,
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RT_HT_CAP_USE_WOW = 0x8,
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RT_HT_CAP_USE_SOFTAP = 0x10,
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RT_HT_CAP_USE_92SE = 0x20,
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RT_HT_CAP_USE_88C_92C = 0x40,
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RT_HT_CAP_USE_AP_CLIENT_MODE = 0x80, /* AP team request to reserve this bit, by Emily */
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}RT_HT_INF0_CAPBILITY, *PRT_HT_INF0_CAPBILITY;
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typedef enum _RT_HT_INF1_CAP{
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RT_HT_CAP_USE_VIDEO_CLIENT = 0x01,
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RT_HT_CAP_USE_JAGUAR_BCUT = 0x02,
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RT_HT_CAP_USE_JAGUAR_CCUT = 0x04,
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}RT_HT_INF1_CAPBILITY, *PRT_HT_INF1_CAPBILITY;
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#define LDPC_HT_ENABLE_RX BIT0
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#define LDPC_HT_ENABLE_TX BIT1
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#define LDPC_HT_TEST_TX_ENABLE BIT2
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#define LDPC_HT_CAP_TX BIT3
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#define STBC_HT_ENABLE_RX BIT0
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#define STBC_HT_ENABLE_TX BIT1
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#define STBC_HT_TEST_TX_ENABLE BIT2
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#define STBC_HT_CAP_TX BIT3
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#define BEAMFORMING_HT_BEAMFORMER_ENABLE BIT0 /* Declare our NIC supports beamformer */
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#define BEAMFORMING_HT_BEAMFORMEE_ENABLE BIT1 /* Declare our NIC supports beamformee */
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#define BEAMFORMING_HT_BEAMFORMER_TEST BIT2 /* Transmiting Beamforming no matter the target supports it or not */
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/* */
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/* The HT Control field */
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/* */
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#define SET_HT_CTRL_CSI_STEERING(_pEleStart, _val) SET_BITS_TO_LE_1BYTE((_pEleStart)+2, 6, 2, _val)
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#define SET_HT_CTRL_NDP_ANNOUNCEMENT(_pEleStart, _val) SET_BITS_TO_LE_1BYTE((_pEleStart)+3, 0, 1, _val)
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#define GET_HT_CTRL_NDP_ANNOUNCEMENT(_pEleStart) LE_BITS_TO_1BYTE((_pEleStart)+3, 0, 1)
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/* 20/40 BSS Coexist */
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#define SET_EXT_CAPABILITY_ELE_BSS_COEXIST(_pEleStart, _val) SET_BITS_TO_LE_1BYTE((_pEleStart), 0, 1, _val)
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#define GET_EXT_CAPABILITY_ELE_BSS_COEXIST(_pEleStart) LE_BITS_TO_1BYTE((_pEleStart), 0, 1)
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#define GET_HT_CAPABILITY_ELE_LDPC_CAP(_pEleStart) LE_BITS_TO_1BYTE(_pEleStart, 0, 1)
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#define GET_HT_CAPABILITY_ELE_TX_STBC(_pEleStart) LE_BITS_TO_1BYTE(_pEleStart, 7, 1)
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#define GET_HT_CAPABILITY_ELE_RX_STBC(_pEleStart) LE_BITS_TO_1BYTE((_pEleStart)+1, 0, 2)
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/* TXBF Capabilities */
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#define SET_HT_CAP_TXBF_RECEIVE_NDP_CAP(_pEleStart, _val) SET_BITS_TO_LE_4BYTE(((u8 *)(_pEleStart))+21, 3, 1, ((u8)_val))
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#define SET_HT_CAP_TXBF_TRANSMIT_NDP_CAP(_pEleStart, _val) SET_BITS_TO_LE_4BYTE(((u8 *)(_pEleStart))+21, 4, 1, ((u8)_val))
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#define SET_HT_CAP_TXBF_EXPLICIT_COMP_STEERING_CAP(_pEleStart, _val) SET_BITS_TO_LE_4BYTE(((u8 *)(_pEleStart))+21, 10, 1, ((u8)_val))
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#define SET_HT_CAP_TXBF_EXPLICIT_COMP_FEEDBACK_CAP(_pEleStart, _val) SET_BITS_TO_LE_4BYTE(((u8 *)(_pEleStart))+21, 15, 2, ((u8)_val))
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#define SET_HT_CAP_TXBF_COMP_STEERING_NUM_ANTENNAS(_pEleStart, _val) SET_BITS_TO_LE_4BYTE(((u8 *)(_pEleStart))+21, 23, 2, ((u8)_val))
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#define GET_HT_CAP_TXBF_EXPLICIT_COMP_STEERING_CAP(_pEleStart) LE_BITS_TO_4BYTE((_pEleStart)+21, 10, 1)
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#define GET_HT_CAP_TXBF_EXPLICIT_COMP_FEEDBACK_CAP(_pEleStart) LE_BITS_TO_4BYTE((_pEleStart)+21, 15, 2)
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#endif /* _RTL871X_HT_H_ */
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