![Bjorn Helgaas](/assets/img/avatar_default.png)
Fix some misspellings in comments. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
230 lines
6 KiB
C
230 lines
6 KiB
C
/*
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* Copyright (c) 2012, Intel Corporation
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* Copyright (c) 2015, Red Hat, Inc.
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* Copyright (c) 2015, 2016 Linaro Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#define pr_fmt(fmt) "ACPI: SPCR: " fmt
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#include <linux/acpi.h>
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#include <linux/console.h>
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#include <linux/kernel.h>
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#include <linux/serial_core.h>
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/*
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* Erratum 44 for QDF2432v1 and QDF2400v1 SoCs describes the BUSY bit as
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* occasionally getting stuck as 1. To avoid the potential for a hang, check
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* TXFE == 0 instead of BUSY == 1. This may not be suitable for all UART
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* implementations, so only do so if an affected platform is detected in
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* acpi_parse_spcr().
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*/
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bool qdf2400_e44_present;
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EXPORT_SYMBOL(qdf2400_e44_present);
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/*
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* Some Qualcomm Datacenter Technologies SoCs have a defective UART BUSY bit.
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* Detect them by examining the OEM fields in the SPCR header, similar to PCI
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* quirk detection in pci_mcfg.c.
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*/
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static bool qdf2400_erratum_44_present(struct acpi_table_header *h)
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{
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if (memcmp(h->oem_id, "QCOM ", ACPI_OEM_ID_SIZE))
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return false;
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if (!memcmp(h->oem_table_id, "QDF2432 ", ACPI_OEM_TABLE_ID_SIZE))
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return true;
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if (!memcmp(h->oem_table_id, "QDF2400 ", ACPI_OEM_TABLE_ID_SIZE) &&
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h->oem_revision == 1)
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return true;
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return false;
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}
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/*
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* APM X-Gene v1 and v2 UART hardware is an 16550 like device but has its
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* register aligned to 32-bit. In addition, the BIOS also encoded the
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* access width to be 8 bits. This function detects this errata condition.
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*/
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static bool xgene_8250_erratum_present(struct acpi_table_spcr *tb)
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{
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bool xgene_8250 = false;
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if (tb->interface_type != ACPI_DBG2_16550_COMPATIBLE)
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return false;
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if (memcmp(tb->header.oem_id, "APMC0D", ACPI_OEM_ID_SIZE) &&
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memcmp(tb->header.oem_id, "HPE ", ACPI_OEM_ID_SIZE))
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return false;
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if (!memcmp(tb->header.oem_table_id, "XGENESPC",
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ACPI_OEM_TABLE_ID_SIZE) && tb->header.oem_revision == 0)
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xgene_8250 = true;
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if (!memcmp(tb->header.oem_table_id, "ProLiant",
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ACPI_OEM_TABLE_ID_SIZE) && tb->header.oem_revision == 1)
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xgene_8250 = true;
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return xgene_8250;
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}
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/**
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* acpi_parse_spcr() - parse ACPI SPCR table and add preferred console
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*
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* @enable_earlycon: set up earlycon for the console specified by the table
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* @enable_console: setup the console specified by the table.
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*
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* For the architectures with support for ACPI, CONFIG_ACPI_SPCR_TABLE may be
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* defined to parse ACPI SPCR table. As a result of the parsing preferred
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* console is registered and if @enable_earlycon is true, earlycon is set up.
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* If @enable_console is true the system console is also configured.
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*
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* When CONFIG_ACPI_SPCR_TABLE is defined, this function should be called
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* from arch initialization code as soon as the DT/ACPI decision is made.
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*
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*/
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int __init acpi_parse_spcr(bool enable_earlycon, bool enable_console)
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{
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static char opts[64];
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struct acpi_table_spcr *table;
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acpi_status status;
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char *uart;
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char *iotype;
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int baud_rate;
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int err;
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if (acpi_disabled)
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return -ENODEV;
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status = acpi_get_table(ACPI_SIG_SPCR, 0,
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(struct acpi_table_header **)&table);
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if (ACPI_FAILURE(status))
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return -ENOENT;
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if (table->header.revision < 2)
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pr_info("SPCR table version %d\n", table->header.revision);
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if (table->serial_port.space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) {
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switch (ACPI_ACCESS_BIT_WIDTH((
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table->serial_port.access_width))) {
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default:
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pr_err("Unexpected SPCR Access Width. Defaulting to byte size\n");
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/* fall through */
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case 8:
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iotype = "mmio";
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break;
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case 16:
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iotype = "mmio16";
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break;
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case 32:
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iotype = "mmio32";
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break;
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}
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} else
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iotype = "io";
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switch (table->interface_type) {
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case ACPI_DBG2_ARM_SBSA_32BIT:
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iotype = "mmio32";
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/* fall through */
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case ACPI_DBG2_ARM_PL011:
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case ACPI_DBG2_ARM_SBSA_GENERIC:
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case ACPI_DBG2_BCM2835:
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uart = "pl011";
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break;
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case ACPI_DBG2_16550_COMPATIBLE:
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case ACPI_DBG2_16550_SUBSET:
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uart = "uart";
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break;
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default:
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err = -ENOENT;
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goto done;
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}
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switch (table->baud_rate) {
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case 0:
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/*
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* SPCR 1.04 defines 0 as a preconfigured state of UART.
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* Assume firmware or bootloader configures console correctly.
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*/
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baud_rate = 0;
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break;
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case 3:
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baud_rate = 9600;
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break;
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case 4:
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baud_rate = 19200;
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break;
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case 6:
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baud_rate = 57600;
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break;
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case 7:
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baud_rate = 115200;
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break;
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default:
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err = -ENOENT;
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goto done;
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}
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/*
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* If the E44 erratum is required, then we need to tell the pl011
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* driver to implement the work-around.
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*
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* The global variable is used by the probe function when it
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* creates the UARTs, whether or not they're used as a console.
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*
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* If the user specifies "traditional" earlycon, the qdf2400_e44
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* console name matches the EARLYCON_DECLARE() statement, and
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* SPCR is not used. Parameter "earlycon" is false.
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*
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* If the user specifies "SPCR" earlycon, then we need to update
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* the console name so that it also says "qdf2400_e44". Parameter
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* "earlycon" is true.
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*
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* For consistency, if we change the console name, then we do it
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* for everyone, not just earlycon.
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*/
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if (qdf2400_erratum_44_present(&table->header)) {
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qdf2400_e44_present = true;
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if (enable_earlycon)
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uart = "qdf2400_e44";
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}
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if (xgene_8250_erratum_present(table)) {
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iotype = "mmio32";
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/* for xgene v1 and v2 we don't know the clock rate of the
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* UART so don't attempt to change to the baud rate state
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* in the table because driver cannot calculate the dividers
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*/
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baud_rate = 0;
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}
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if (!baud_rate) {
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snprintf(opts, sizeof(opts), "%s,%s,0x%llx", uart, iotype,
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table->serial_port.address);
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} else {
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snprintf(opts, sizeof(opts), "%s,%s,0x%llx,%d", uart, iotype,
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table->serial_port.address, baud_rate);
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}
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pr_info("console: %s\n", opts);
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if (enable_earlycon)
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setup_earlycon(opts);
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if (enable_console)
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err = add_preferred_console(uart, 0, opts + strlen(uart) + 1);
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else
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err = 0;
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done:
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acpi_put_table((struct acpi_table_header *)table);
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return err;
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}
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