![Uwe Kleine-König](/assets/img/avatar_default.png)
When the EXTENSION.WADA bit is set, register 0x19 contains a bitmap of
week days, not a day of month. As Linux only handles a single alarm
without repetition using day of month is more flexible, so clear this
bit. (Otherwise a value depending on time.tm_wday would have to be
written to register 0x19.)
Also optimize setting the AIE bit to use a single register write instead
of a bulk write of three registers.
Fixes: ee0981be77
("rtc: ds1307: Add support for Epson RX8130CE")
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
1896 lines
47 KiB
C
1896 lines
47 KiB
C
/*
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* rtc-ds1307.c - RTC driver for some mostly-compatible I2C chips.
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*
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* Copyright (C) 2005 James Chapman (ds1337 core)
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* Copyright (C) 2006 David Brownell
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* Copyright (C) 2009 Matthias Fuchs (rx8025 support)
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* Copyright (C) 2012 Bertrand Achard (nvram access fixes)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/acpi.h>
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#include <linux/bcd.h>
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#include <linux/i2c.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/rtc/ds1307.h>
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#include <linux/rtc.h>
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#include <linux/slab.h>
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#include <linux/string.h>
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#include <linux/hwmon.h>
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#include <linux/hwmon-sysfs.h>
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#include <linux/clk-provider.h>
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#include <linux/regmap.h>
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/*
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* We can't determine type by probing, but if we expect pre-Linux code
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* to have set the chip up as a clock (turning on the oscillator and
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* setting the date and time), Linux can ignore the non-clock features.
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* That's a natural job for a factory or repair bench.
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*/
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enum ds_type {
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ds_1307,
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ds_1308,
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ds_1337,
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ds_1338,
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ds_1339,
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ds_1340,
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ds_1341,
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ds_1388,
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ds_3231,
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m41t0,
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m41t00,
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m41t11,
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mcp794xx,
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rx_8025,
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rx_8130,
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last_ds_type /* always last */
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/* rs5c372 too? different address... */
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};
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/* RTC registers don't differ much, except for the century flag */
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#define DS1307_REG_SECS 0x00 /* 00-59 */
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# define DS1307_BIT_CH 0x80
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# define DS1340_BIT_nEOSC 0x80
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# define MCP794XX_BIT_ST 0x80
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#define DS1307_REG_MIN 0x01 /* 00-59 */
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# define M41T0_BIT_OF 0x80
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#define DS1307_REG_HOUR 0x02 /* 00-23, or 1-12{am,pm} */
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# define DS1307_BIT_12HR 0x40 /* in REG_HOUR */
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# define DS1307_BIT_PM 0x20 /* in REG_HOUR */
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# define DS1340_BIT_CENTURY_EN 0x80 /* in REG_HOUR */
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# define DS1340_BIT_CENTURY 0x40 /* in REG_HOUR */
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#define DS1307_REG_WDAY 0x03 /* 01-07 */
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# define MCP794XX_BIT_VBATEN 0x08
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#define DS1307_REG_MDAY 0x04 /* 01-31 */
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#define DS1307_REG_MONTH 0x05 /* 01-12 */
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# define DS1337_BIT_CENTURY 0x80 /* in REG_MONTH */
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#define DS1307_REG_YEAR 0x06 /* 00-99 */
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/*
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* Other registers (control, status, alarms, trickle charge, NVRAM, etc)
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* start at 7, and they differ a LOT. Only control and status matter for
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* basic RTC date and time functionality; be careful using them.
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*/
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#define DS1307_REG_CONTROL 0x07 /* or ds1338 */
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# define DS1307_BIT_OUT 0x80
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# define DS1338_BIT_OSF 0x20
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# define DS1307_BIT_SQWE 0x10
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# define DS1307_BIT_RS1 0x02
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# define DS1307_BIT_RS0 0x01
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#define DS1337_REG_CONTROL 0x0e
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# define DS1337_BIT_nEOSC 0x80
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# define DS1339_BIT_BBSQI 0x20
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# define DS3231_BIT_BBSQW 0x40 /* same as BBSQI */
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# define DS1337_BIT_RS2 0x10
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# define DS1337_BIT_RS1 0x08
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# define DS1337_BIT_INTCN 0x04
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# define DS1337_BIT_A2IE 0x02
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# define DS1337_BIT_A1IE 0x01
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#define DS1340_REG_CONTROL 0x07
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# define DS1340_BIT_OUT 0x80
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# define DS1340_BIT_FT 0x40
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# define DS1340_BIT_CALIB_SIGN 0x20
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# define DS1340_M_CALIBRATION 0x1f
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#define DS1340_REG_FLAG 0x09
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# define DS1340_BIT_OSF 0x80
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#define DS1337_REG_STATUS 0x0f
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# define DS1337_BIT_OSF 0x80
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# define DS3231_BIT_EN32KHZ 0x08
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# define DS1337_BIT_A2I 0x02
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# define DS1337_BIT_A1I 0x01
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#define DS1339_REG_ALARM1_SECS 0x07
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#define DS13XX_TRICKLE_CHARGER_MAGIC 0xa0
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#define RX8025_REG_CTRL1 0x0e
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# define RX8025_BIT_2412 0x20
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#define RX8025_REG_CTRL2 0x0f
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# define RX8025_BIT_PON 0x10
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# define RX8025_BIT_VDET 0x40
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# define RX8025_BIT_XST 0x20
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#define RX8130_REG_ALARM_MIN 0x17
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#define RX8130_REG_ALARM_HOUR 0x18
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#define RX8130_REG_ALARM_WEEK_OR_DAY 0x19
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#define RX8130_REG_EXTENSION 0x1c
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#define RX8130_REG_EXTENSION_WADA BIT(3)
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#define RX8130_REG_FLAG 0x1d
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#define RX8130_REG_FLAG_VLF BIT(1)
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#define RX8130_REG_FLAG_AF BIT(3)
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#define RX8130_REG_CONTROL0 0x1e
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#define RX8130_REG_CONTROL0_AIE BIT(3)
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#define MCP794XX_REG_CONTROL 0x07
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# define MCP794XX_BIT_ALM0_EN 0x10
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# define MCP794XX_BIT_ALM1_EN 0x20
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#define MCP794XX_REG_ALARM0_BASE 0x0a
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#define MCP794XX_REG_ALARM0_CTRL 0x0d
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#define MCP794XX_REG_ALARM1_BASE 0x11
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#define MCP794XX_REG_ALARM1_CTRL 0x14
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# define MCP794XX_BIT_ALMX_IF BIT(3)
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# define MCP794XX_BIT_ALMX_C0 BIT(4)
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# define MCP794XX_BIT_ALMX_C1 BIT(5)
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# define MCP794XX_BIT_ALMX_C2 BIT(6)
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# define MCP794XX_BIT_ALMX_POL BIT(7)
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# define MCP794XX_MSK_ALMX_MATCH (MCP794XX_BIT_ALMX_C0 | \
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MCP794XX_BIT_ALMX_C1 | \
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MCP794XX_BIT_ALMX_C2)
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#define M41TXX_REG_CONTROL 0x07
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# define M41TXX_BIT_OUT BIT(7)
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# define M41TXX_BIT_FT BIT(6)
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# define M41TXX_BIT_CALIB_SIGN BIT(5)
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# define M41TXX_M_CALIBRATION GENMASK(4, 0)
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/* negative offset step is -2.034ppm */
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#define M41TXX_NEG_OFFSET_STEP_PPB 2034
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/* positive offset step is +4.068ppm */
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#define M41TXX_POS_OFFSET_STEP_PPB 4068
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/* Min and max values supported with 'offset' interface by M41TXX */
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#define M41TXX_MIN_OFFSET ((-31) * M41TXX_NEG_OFFSET_STEP_PPB)
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#define M41TXX_MAX_OFFSET ((31) * M41TXX_POS_OFFSET_STEP_PPB)
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struct ds1307 {
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enum ds_type type;
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unsigned long flags;
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#define HAS_NVRAM 0 /* bit 0 == sysfs file active */
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#define HAS_ALARM 1 /* bit 1 == irq claimed */
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struct device *dev;
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struct regmap *regmap;
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const char *name;
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struct rtc_device *rtc;
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#ifdef CONFIG_COMMON_CLK
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struct clk_hw clks[2];
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#endif
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};
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struct chip_desc {
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unsigned alarm:1;
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u16 nvram_offset;
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u16 nvram_size;
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u8 offset; /* register's offset */
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u8 century_reg;
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u8 century_enable_bit;
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u8 century_bit;
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u8 bbsqi_bit;
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irq_handler_t irq_handler;
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const struct rtc_class_ops *rtc_ops;
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u16 trickle_charger_reg;
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u8 (*do_trickle_setup)(struct ds1307 *, u32,
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bool);
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};
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static const struct chip_desc chips[last_ds_type];
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static int ds1307_get_time(struct device *dev, struct rtc_time *t)
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{
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struct ds1307 *ds1307 = dev_get_drvdata(dev);
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int tmp, ret;
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const struct chip_desc *chip = &chips[ds1307->type];
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u8 regs[7];
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if (ds1307->type == rx_8130) {
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unsigned int regflag;
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ret = regmap_read(ds1307->regmap, RX8130_REG_FLAG, ®flag);
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if (ret) {
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dev_err(dev, "%s error %d\n", "read", ret);
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return ret;
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}
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if (regflag & RX8130_REG_FLAG_VLF) {
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dev_warn_once(dev, "oscillator failed, set time!\n");
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return -EINVAL;
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}
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}
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/* read the RTC date and time registers all at once */
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ret = regmap_bulk_read(ds1307->regmap, chip->offset, regs,
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sizeof(regs));
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if (ret) {
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dev_err(dev, "%s error %d\n", "read", ret);
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return ret;
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}
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dev_dbg(dev, "%s: %7ph\n", "read", regs);
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/* if oscillator fail bit is set, no data can be trusted */
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if (ds1307->type == m41t0 &&
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regs[DS1307_REG_MIN] & M41T0_BIT_OF) {
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dev_warn_once(dev, "oscillator failed, set time!\n");
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return -EINVAL;
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}
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t->tm_sec = bcd2bin(regs[DS1307_REG_SECS] & 0x7f);
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t->tm_min = bcd2bin(regs[DS1307_REG_MIN] & 0x7f);
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tmp = regs[DS1307_REG_HOUR] & 0x3f;
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t->tm_hour = bcd2bin(tmp);
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t->tm_wday = bcd2bin(regs[DS1307_REG_WDAY] & 0x07) - 1;
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t->tm_mday = bcd2bin(regs[DS1307_REG_MDAY] & 0x3f);
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tmp = regs[DS1307_REG_MONTH] & 0x1f;
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t->tm_mon = bcd2bin(tmp) - 1;
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t->tm_year = bcd2bin(regs[DS1307_REG_YEAR]) + 100;
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if (regs[chip->century_reg] & chip->century_bit &&
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IS_ENABLED(CONFIG_RTC_DRV_DS1307_CENTURY))
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t->tm_year += 100;
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dev_dbg(dev, "%s secs=%d, mins=%d, "
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"hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
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"read", t->tm_sec, t->tm_min,
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t->tm_hour, t->tm_mday,
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t->tm_mon, t->tm_year, t->tm_wday);
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return 0;
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}
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static int ds1307_set_time(struct device *dev, struct rtc_time *t)
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{
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struct ds1307 *ds1307 = dev_get_drvdata(dev);
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const struct chip_desc *chip = &chips[ds1307->type];
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int result;
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int tmp;
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u8 regs[7];
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dev_dbg(dev, "%s secs=%d, mins=%d, "
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"hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
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"write", t->tm_sec, t->tm_min,
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t->tm_hour, t->tm_mday,
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t->tm_mon, t->tm_year, t->tm_wday);
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if (t->tm_year < 100)
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return -EINVAL;
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#ifdef CONFIG_RTC_DRV_DS1307_CENTURY
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if (t->tm_year > (chip->century_bit ? 299 : 199))
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return -EINVAL;
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#else
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if (t->tm_year > 199)
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return -EINVAL;
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#endif
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regs[DS1307_REG_SECS] = bin2bcd(t->tm_sec);
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regs[DS1307_REG_MIN] = bin2bcd(t->tm_min);
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regs[DS1307_REG_HOUR] = bin2bcd(t->tm_hour);
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regs[DS1307_REG_WDAY] = bin2bcd(t->tm_wday + 1);
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regs[DS1307_REG_MDAY] = bin2bcd(t->tm_mday);
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regs[DS1307_REG_MONTH] = bin2bcd(t->tm_mon + 1);
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/* assume 20YY not 19YY */
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tmp = t->tm_year - 100;
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regs[DS1307_REG_YEAR] = bin2bcd(tmp);
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if (chip->century_enable_bit)
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regs[chip->century_reg] |= chip->century_enable_bit;
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if (t->tm_year > 199 && chip->century_bit)
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regs[chip->century_reg] |= chip->century_bit;
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if (ds1307->type == mcp794xx) {
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/*
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* these bits were cleared when preparing the date/time
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* values and need to be set again before writing the
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* regsfer out to the device.
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*/
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regs[DS1307_REG_SECS] |= MCP794XX_BIT_ST;
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regs[DS1307_REG_WDAY] |= MCP794XX_BIT_VBATEN;
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}
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dev_dbg(dev, "%s: %7ph\n", "write", regs);
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result = regmap_bulk_write(ds1307->regmap, chip->offset, regs,
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sizeof(regs));
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if (result) {
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dev_err(dev, "%s error %d\n", "write", result);
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return result;
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}
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if (ds1307->type == rx_8130) {
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/* clear Voltage Loss Flag as data is available now */
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result = regmap_write(ds1307->regmap, RX8130_REG_FLAG,
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~(u8)RX8130_REG_FLAG_VLF);
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if (result) {
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dev_err(dev, "%s error %d\n", "write", result);
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return result;
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}
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}
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return 0;
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}
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static int ds1337_read_alarm(struct device *dev, struct rtc_wkalrm *t)
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{
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struct ds1307 *ds1307 = dev_get_drvdata(dev);
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int ret;
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u8 regs[9];
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if (!test_bit(HAS_ALARM, &ds1307->flags))
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return -EINVAL;
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/* read all ALARM1, ALARM2, and status registers at once */
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ret = regmap_bulk_read(ds1307->regmap, DS1339_REG_ALARM1_SECS,
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regs, sizeof(regs));
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if (ret) {
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dev_err(dev, "%s error %d\n", "alarm read", ret);
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return ret;
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}
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dev_dbg(dev, "%s: %4ph, %3ph, %2ph\n", "alarm read",
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®s[0], ®s[4], ®s[7]);
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/*
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* report alarm time (ALARM1); assume 24 hour and day-of-month modes,
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* and that all four fields are checked matches
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*/
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t->time.tm_sec = bcd2bin(regs[0] & 0x7f);
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t->time.tm_min = bcd2bin(regs[1] & 0x7f);
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t->time.tm_hour = bcd2bin(regs[2] & 0x3f);
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t->time.tm_mday = bcd2bin(regs[3] & 0x3f);
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/* ... and status */
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t->enabled = !!(regs[7] & DS1337_BIT_A1IE);
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t->pending = !!(regs[8] & DS1337_BIT_A1I);
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dev_dbg(dev, "%s secs=%d, mins=%d, "
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"hours=%d, mday=%d, enabled=%d, pending=%d\n",
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"alarm read", t->time.tm_sec, t->time.tm_min,
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t->time.tm_hour, t->time.tm_mday,
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t->enabled, t->pending);
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return 0;
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}
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static int ds1337_set_alarm(struct device *dev, struct rtc_wkalrm *t)
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{
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struct ds1307 *ds1307 = dev_get_drvdata(dev);
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unsigned char regs[9];
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u8 control, status;
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int ret;
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if (!test_bit(HAS_ALARM, &ds1307->flags))
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return -EINVAL;
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dev_dbg(dev, "%s secs=%d, mins=%d, "
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"hours=%d, mday=%d, enabled=%d, pending=%d\n",
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"alarm set", t->time.tm_sec, t->time.tm_min,
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t->time.tm_hour, t->time.tm_mday,
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t->enabled, t->pending);
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/* read current status of both alarms and the chip */
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ret = regmap_bulk_read(ds1307->regmap, DS1339_REG_ALARM1_SECS, regs,
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sizeof(regs));
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if (ret) {
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dev_err(dev, "%s error %d\n", "alarm write", ret);
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return ret;
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}
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control = regs[7];
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status = regs[8];
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dev_dbg(dev, "%s: %4ph, %3ph, %02x %02x\n", "alarm set (old status)",
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®s[0], ®s[4], control, status);
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/* set ALARM1, using 24 hour and day-of-month modes */
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regs[0] = bin2bcd(t->time.tm_sec);
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regs[1] = bin2bcd(t->time.tm_min);
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regs[2] = bin2bcd(t->time.tm_hour);
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regs[3] = bin2bcd(t->time.tm_mday);
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/* set ALARM2 to non-garbage */
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regs[4] = 0;
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regs[5] = 0;
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regs[6] = 0;
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/* disable alarms */
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regs[7] = control & ~(DS1337_BIT_A1IE | DS1337_BIT_A2IE);
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regs[8] = status & ~(DS1337_BIT_A1I | DS1337_BIT_A2I);
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ret = regmap_bulk_write(ds1307->regmap, DS1339_REG_ALARM1_SECS, regs,
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sizeof(regs));
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if (ret) {
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dev_err(dev, "can't set alarm time\n");
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return ret;
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}
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/* optionally enable ALARM1 */
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if (t->enabled) {
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dev_dbg(dev, "alarm IRQ armed\n");
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regs[7] |= DS1337_BIT_A1IE; /* only ALARM1 is used */
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regmap_write(ds1307->regmap, DS1337_REG_CONTROL, regs[7]);
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}
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|
|
|
return 0;
|
|
}
|
|
|
|
static int ds1307_alarm_irq_enable(struct device *dev, unsigned int enabled)
|
|
{
|
|
struct ds1307 *ds1307 = dev_get_drvdata(dev);
|
|
|
|
if (!test_bit(HAS_ALARM, &ds1307->flags))
|
|
return -ENOTTY;
|
|
|
|
return regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
|
|
DS1337_BIT_A1IE,
|
|
enabled ? DS1337_BIT_A1IE : 0);
|
|
}
|
|
|
|
static u8 do_trickle_setup_ds1339(struct ds1307 *ds1307, u32 ohms, bool diode)
|
|
{
|
|
u8 setup = (diode) ? DS1307_TRICKLE_CHARGER_DIODE :
|
|
DS1307_TRICKLE_CHARGER_NO_DIODE;
|
|
|
|
switch (ohms) {
|
|
case 250:
|
|
setup |= DS1307_TRICKLE_CHARGER_250_OHM;
|
|
break;
|
|
case 2000:
|
|
setup |= DS1307_TRICKLE_CHARGER_2K_OHM;
|
|
break;
|
|
case 4000:
|
|
setup |= DS1307_TRICKLE_CHARGER_4K_OHM;
|
|
break;
|
|
default:
|
|
dev_warn(ds1307->dev,
|
|
"Unsupported ohm value %u in dt\n", ohms);
|
|
return 0;
|
|
}
|
|
return setup;
|
|
}
|
|
|
|
static irqreturn_t rx8130_irq(int irq, void *dev_id)
|
|
{
|
|
struct ds1307 *ds1307 = dev_id;
|
|
struct mutex *lock = &ds1307->rtc->ops_lock;
|
|
u8 ctl[3];
|
|
int ret;
|
|
|
|
mutex_lock(lock);
|
|
|
|
/* Read control registers. */
|
|
ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
|
|
sizeof(ctl));
|
|
if (ret < 0)
|
|
goto out;
|
|
if (!(ctl[1] & RX8130_REG_FLAG_AF))
|
|
goto out;
|
|
ctl[1] &= ~RX8130_REG_FLAG_AF;
|
|
ctl[2] &= ~RX8130_REG_CONTROL0_AIE;
|
|
|
|
ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
|
|
sizeof(ctl));
|
|
if (ret < 0)
|
|
goto out;
|
|
|
|
rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
|
|
|
|
out:
|
|
mutex_unlock(lock);
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static int rx8130_read_alarm(struct device *dev, struct rtc_wkalrm *t)
|
|
{
|
|
struct ds1307 *ds1307 = dev_get_drvdata(dev);
|
|
u8 ald[3], ctl[3];
|
|
int ret;
|
|
|
|
if (!test_bit(HAS_ALARM, &ds1307->flags))
|
|
return -EINVAL;
|
|
|
|
/* Read alarm registers. */
|
|
ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_ALARM_MIN, ald,
|
|
sizeof(ald));
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
/* Read control registers. */
|
|
ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
|
|
sizeof(ctl));
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
t->enabled = !!(ctl[2] & RX8130_REG_CONTROL0_AIE);
|
|
t->pending = !!(ctl[1] & RX8130_REG_FLAG_AF);
|
|
|
|
/* Report alarm 0 time assuming 24-hour and day-of-month modes. */
|
|
t->time.tm_sec = -1;
|
|
t->time.tm_min = bcd2bin(ald[0] & 0x7f);
|
|
t->time.tm_hour = bcd2bin(ald[1] & 0x7f);
|
|
t->time.tm_wday = -1;
|
|
t->time.tm_mday = bcd2bin(ald[2] & 0x7f);
|
|
t->time.tm_mon = -1;
|
|
t->time.tm_year = -1;
|
|
t->time.tm_yday = -1;
|
|
t->time.tm_isdst = -1;
|
|
|
|
dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d enabled=%d\n",
|
|
__func__, t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
|
|
t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int rx8130_set_alarm(struct device *dev, struct rtc_wkalrm *t)
|
|
{
|
|
struct ds1307 *ds1307 = dev_get_drvdata(dev);
|
|
u8 ald[3], ctl[3];
|
|
int ret;
|
|
|
|
if (!test_bit(HAS_ALARM, &ds1307->flags))
|
|
return -EINVAL;
|
|
|
|
dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
|
|
"enabled=%d pending=%d\n", __func__,
|
|
t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
|
|
t->time.tm_wday, t->time.tm_mday, t->time.tm_mon,
|
|
t->enabled, t->pending);
|
|
|
|
/* Read control registers. */
|
|
ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
|
|
sizeof(ctl));
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
ctl[0] &= RX8130_REG_EXTENSION_WADA;
|
|
ctl[1] &= ~RX8130_REG_FLAG_AF;
|
|
ctl[2] &= ~RX8130_REG_CONTROL0_AIE;
|
|
|
|
ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
|
|
sizeof(ctl));
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
/* Hardware alarm precision is 1 minute! */
|
|
ald[0] = bin2bcd(t->time.tm_min);
|
|
ald[1] = bin2bcd(t->time.tm_hour);
|
|
ald[2] = bin2bcd(t->time.tm_mday);
|
|
|
|
ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_ALARM_MIN, ald,
|
|
sizeof(ald));
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
if (!t->enabled)
|
|
return 0;
|
|
|
|
ctl[2] |= RX8130_REG_CONTROL0_AIE;
|
|
|
|
return regmap_write(ds1307->regmap, RX8130_REG_CONTROL0, ctl[2]);
|
|
}
|
|
|
|
static int rx8130_alarm_irq_enable(struct device *dev, unsigned int enabled)
|
|
{
|
|
struct ds1307 *ds1307 = dev_get_drvdata(dev);
|
|
int ret, reg;
|
|
|
|
if (!test_bit(HAS_ALARM, &ds1307->flags))
|
|
return -EINVAL;
|
|
|
|
ret = regmap_read(ds1307->regmap, RX8130_REG_CONTROL0, ®);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
if (enabled)
|
|
reg |= RX8130_REG_CONTROL0_AIE;
|
|
else
|
|
reg &= ~RX8130_REG_CONTROL0_AIE;
|
|
|
|
return regmap_write(ds1307->regmap, RX8130_REG_CONTROL0, reg);
|
|
}
|
|
|
|
static irqreturn_t mcp794xx_irq(int irq, void *dev_id)
|
|
{
|
|
struct ds1307 *ds1307 = dev_id;
|
|
struct mutex *lock = &ds1307->rtc->ops_lock;
|
|
int reg, ret;
|
|
|
|
mutex_lock(lock);
|
|
|
|
/* Check and clear alarm 0 interrupt flag. */
|
|
ret = regmap_read(ds1307->regmap, MCP794XX_REG_ALARM0_CTRL, ®);
|
|
if (ret)
|
|
goto out;
|
|
if (!(reg & MCP794XX_BIT_ALMX_IF))
|
|
goto out;
|
|
reg &= ~MCP794XX_BIT_ALMX_IF;
|
|
ret = regmap_write(ds1307->regmap, MCP794XX_REG_ALARM0_CTRL, reg);
|
|
if (ret)
|
|
goto out;
|
|
|
|
/* Disable alarm 0. */
|
|
ret = regmap_update_bits(ds1307->regmap, MCP794XX_REG_CONTROL,
|
|
MCP794XX_BIT_ALM0_EN, 0);
|
|
if (ret)
|
|
goto out;
|
|
|
|
rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
|
|
|
|
out:
|
|
mutex_unlock(lock);
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static int mcp794xx_read_alarm(struct device *dev, struct rtc_wkalrm *t)
|
|
{
|
|
struct ds1307 *ds1307 = dev_get_drvdata(dev);
|
|
u8 regs[10];
|
|
int ret;
|
|
|
|
if (!test_bit(HAS_ALARM, &ds1307->flags))
|
|
return -EINVAL;
|
|
|
|
/* Read control and alarm 0 registers. */
|
|
ret = regmap_bulk_read(ds1307->regmap, MCP794XX_REG_CONTROL, regs,
|
|
sizeof(regs));
|
|
if (ret)
|
|
return ret;
|
|
|
|
t->enabled = !!(regs[0] & MCP794XX_BIT_ALM0_EN);
|
|
|
|
/* Report alarm 0 time assuming 24-hour and day-of-month modes. */
|
|
t->time.tm_sec = bcd2bin(regs[3] & 0x7f);
|
|
t->time.tm_min = bcd2bin(regs[4] & 0x7f);
|
|
t->time.tm_hour = bcd2bin(regs[5] & 0x3f);
|
|
t->time.tm_wday = bcd2bin(regs[6] & 0x7) - 1;
|
|
t->time.tm_mday = bcd2bin(regs[7] & 0x3f);
|
|
t->time.tm_mon = bcd2bin(regs[8] & 0x1f) - 1;
|
|
t->time.tm_year = -1;
|
|
t->time.tm_yday = -1;
|
|
t->time.tm_isdst = -1;
|
|
|
|
dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
|
|
"enabled=%d polarity=%d irq=%d match=%lu\n", __func__,
|
|
t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
|
|
t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled,
|
|
!!(regs[6] & MCP794XX_BIT_ALMX_POL),
|
|
!!(regs[6] & MCP794XX_BIT_ALMX_IF),
|
|
(regs[6] & MCP794XX_MSK_ALMX_MATCH) >> 4);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* We may have a random RTC weekday, therefore calculate alarm weekday based
|
|
* on current weekday we read from the RTC timekeeping regs
|
|
*/
|
|
static int mcp794xx_alm_weekday(struct device *dev, struct rtc_time *tm_alarm)
|
|
{
|
|
struct rtc_time tm_now;
|
|
int days_now, days_alarm, ret;
|
|
|
|
ret = ds1307_get_time(dev, &tm_now);
|
|
if (ret)
|
|
return ret;
|
|
|
|
days_now = div_s64(rtc_tm_to_time64(&tm_now), 24 * 60 * 60);
|
|
days_alarm = div_s64(rtc_tm_to_time64(tm_alarm), 24 * 60 * 60);
|
|
|
|
return (tm_now.tm_wday + days_alarm - days_now) % 7 + 1;
|
|
}
|
|
|
|
static int mcp794xx_set_alarm(struct device *dev, struct rtc_wkalrm *t)
|
|
{
|
|
struct ds1307 *ds1307 = dev_get_drvdata(dev);
|
|
unsigned char regs[10];
|
|
int wday, ret;
|
|
|
|
if (!test_bit(HAS_ALARM, &ds1307->flags))
|
|
return -EINVAL;
|
|
|
|
wday = mcp794xx_alm_weekday(dev, &t->time);
|
|
if (wday < 0)
|
|
return wday;
|
|
|
|
dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
|
|
"enabled=%d pending=%d\n", __func__,
|
|
t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
|
|
t->time.tm_wday, t->time.tm_mday, t->time.tm_mon,
|
|
t->enabled, t->pending);
|
|
|
|
/* Read control and alarm 0 registers. */
|
|
ret = regmap_bulk_read(ds1307->regmap, MCP794XX_REG_CONTROL, regs,
|
|
sizeof(regs));
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* Set alarm 0, using 24-hour and day-of-month modes. */
|
|
regs[3] = bin2bcd(t->time.tm_sec);
|
|
regs[4] = bin2bcd(t->time.tm_min);
|
|
regs[5] = bin2bcd(t->time.tm_hour);
|
|
regs[6] = wday;
|
|
regs[7] = bin2bcd(t->time.tm_mday);
|
|
regs[8] = bin2bcd(t->time.tm_mon + 1);
|
|
|
|
/* Clear the alarm 0 interrupt flag. */
|
|
regs[6] &= ~MCP794XX_BIT_ALMX_IF;
|
|
/* Set alarm match: second, minute, hour, day, date, month. */
|
|
regs[6] |= MCP794XX_MSK_ALMX_MATCH;
|
|
/* Disable interrupt. We will not enable until completely programmed */
|
|
regs[0] &= ~MCP794XX_BIT_ALM0_EN;
|
|
|
|
ret = regmap_bulk_write(ds1307->regmap, MCP794XX_REG_CONTROL, regs,
|
|
sizeof(regs));
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (!t->enabled)
|
|
return 0;
|
|
regs[0] |= MCP794XX_BIT_ALM0_EN;
|
|
return regmap_write(ds1307->regmap, MCP794XX_REG_CONTROL, regs[0]);
|
|
}
|
|
|
|
static int mcp794xx_alarm_irq_enable(struct device *dev, unsigned int enabled)
|
|
{
|
|
struct ds1307 *ds1307 = dev_get_drvdata(dev);
|
|
|
|
if (!test_bit(HAS_ALARM, &ds1307->flags))
|
|
return -EINVAL;
|
|
|
|
return regmap_update_bits(ds1307->regmap, MCP794XX_REG_CONTROL,
|
|
MCP794XX_BIT_ALM0_EN,
|
|
enabled ? MCP794XX_BIT_ALM0_EN : 0);
|
|
}
|
|
|
|
static int m41txx_rtc_read_offset(struct device *dev, long *offset)
|
|
{
|
|
struct ds1307 *ds1307 = dev_get_drvdata(dev);
|
|
unsigned int ctrl_reg;
|
|
u8 val;
|
|
|
|
regmap_read(ds1307->regmap, M41TXX_REG_CONTROL, &ctrl_reg);
|
|
|
|
val = ctrl_reg & M41TXX_M_CALIBRATION;
|
|
|
|
/* check if positive */
|
|
if (ctrl_reg & M41TXX_BIT_CALIB_SIGN)
|
|
*offset = (val * M41TXX_POS_OFFSET_STEP_PPB);
|
|
else
|
|
*offset = -(val * M41TXX_NEG_OFFSET_STEP_PPB);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int m41txx_rtc_set_offset(struct device *dev, long offset)
|
|
{
|
|
struct ds1307 *ds1307 = dev_get_drvdata(dev);
|
|
unsigned int ctrl_reg;
|
|
|
|
if ((offset < M41TXX_MIN_OFFSET) || (offset > M41TXX_MAX_OFFSET))
|
|
return -ERANGE;
|
|
|
|
if (offset >= 0) {
|
|
ctrl_reg = DIV_ROUND_CLOSEST(offset,
|
|
M41TXX_POS_OFFSET_STEP_PPB);
|
|
ctrl_reg |= M41TXX_BIT_CALIB_SIGN;
|
|
} else {
|
|
ctrl_reg = DIV_ROUND_CLOSEST(abs(offset),
|
|
M41TXX_NEG_OFFSET_STEP_PPB);
|
|
}
|
|
|
|
return regmap_update_bits(ds1307->regmap, M41TXX_REG_CONTROL,
|
|
M41TXX_M_CALIBRATION | M41TXX_BIT_CALIB_SIGN,
|
|
ctrl_reg);
|
|
}
|
|
|
|
static const struct rtc_class_ops rx8130_rtc_ops = {
|
|
.read_time = ds1307_get_time,
|
|
.set_time = ds1307_set_time,
|
|
.read_alarm = rx8130_read_alarm,
|
|
.set_alarm = rx8130_set_alarm,
|
|
.alarm_irq_enable = rx8130_alarm_irq_enable,
|
|
};
|
|
|
|
static const struct rtc_class_ops mcp794xx_rtc_ops = {
|
|
.read_time = ds1307_get_time,
|
|
.set_time = ds1307_set_time,
|
|
.read_alarm = mcp794xx_read_alarm,
|
|
.set_alarm = mcp794xx_set_alarm,
|
|
.alarm_irq_enable = mcp794xx_alarm_irq_enable,
|
|
};
|
|
|
|
static const struct rtc_class_ops m41txx_rtc_ops = {
|
|
.read_time = ds1307_get_time,
|
|
.set_time = ds1307_set_time,
|
|
.read_alarm = ds1337_read_alarm,
|
|
.set_alarm = ds1337_set_alarm,
|
|
.alarm_irq_enable = ds1307_alarm_irq_enable,
|
|
.read_offset = m41txx_rtc_read_offset,
|
|
.set_offset = m41txx_rtc_set_offset,
|
|
};
|
|
|
|
static const struct chip_desc chips[last_ds_type] = {
|
|
[ds_1307] = {
|
|
.nvram_offset = 8,
|
|
.nvram_size = 56,
|
|
},
|
|
[ds_1308] = {
|
|
.nvram_offset = 8,
|
|
.nvram_size = 56,
|
|
},
|
|
[ds_1337] = {
|
|
.alarm = 1,
|
|
.century_reg = DS1307_REG_MONTH,
|
|
.century_bit = DS1337_BIT_CENTURY,
|
|
},
|
|
[ds_1338] = {
|
|
.nvram_offset = 8,
|
|
.nvram_size = 56,
|
|
},
|
|
[ds_1339] = {
|
|
.alarm = 1,
|
|
.century_reg = DS1307_REG_MONTH,
|
|
.century_bit = DS1337_BIT_CENTURY,
|
|
.bbsqi_bit = DS1339_BIT_BBSQI,
|
|
.trickle_charger_reg = 0x10,
|
|
.do_trickle_setup = &do_trickle_setup_ds1339,
|
|
},
|
|
[ds_1340] = {
|
|
.century_reg = DS1307_REG_HOUR,
|
|
.century_enable_bit = DS1340_BIT_CENTURY_EN,
|
|
.century_bit = DS1340_BIT_CENTURY,
|
|
.do_trickle_setup = &do_trickle_setup_ds1339,
|
|
.trickle_charger_reg = 0x08,
|
|
},
|
|
[ds_1341] = {
|
|
.century_reg = DS1307_REG_MONTH,
|
|
.century_bit = DS1337_BIT_CENTURY,
|
|
},
|
|
[ds_1388] = {
|
|
.offset = 1,
|
|
.trickle_charger_reg = 0x0a,
|
|
},
|
|
[ds_3231] = {
|
|
.alarm = 1,
|
|
.century_reg = DS1307_REG_MONTH,
|
|
.century_bit = DS1337_BIT_CENTURY,
|
|
.bbsqi_bit = DS3231_BIT_BBSQW,
|
|
},
|
|
[rx_8130] = {
|
|
.alarm = 1,
|
|
/* this is battery backed SRAM */
|
|
.nvram_offset = 0x20,
|
|
.nvram_size = 4, /* 32bit (4 word x 8 bit) */
|
|
.offset = 0x10,
|
|
.irq_handler = rx8130_irq,
|
|
.rtc_ops = &rx8130_rtc_ops,
|
|
},
|
|
[m41t0] = {
|
|
.rtc_ops = &m41txx_rtc_ops,
|
|
},
|
|
[m41t00] = {
|
|
.rtc_ops = &m41txx_rtc_ops,
|
|
},
|
|
[m41t11] = {
|
|
/* this is battery backed SRAM */
|
|
.nvram_offset = 8,
|
|
.nvram_size = 56,
|
|
.rtc_ops = &m41txx_rtc_ops,
|
|
},
|
|
[mcp794xx] = {
|
|
.alarm = 1,
|
|
/* this is battery backed SRAM */
|
|
.nvram_offset = 0x20,
|
|
.nvram_size = 0x40,
|
|
.irq_handler = mcp794xx_irq,
|
|
.rtc_ops = &mcp794xx_rtc_ops,
|
|
},
|
|
};
|
|
|
|
static const struct i2c_device_id ds1307_id[] = {
|
|
{ "ds1307", ds_1307 },
|
|
{ "ds1308", ds_1308 },
|
|
{ "ds1337", ds_1337 },
|
|
{ "ds1338", ds_1338 },
|
|
{ "ds1339", ds_1339 },
|
|
{ "ds1388", ds_1388 },
|
|
{ "ds1340", ds_1340 },
|
|
{ "ds1341", ds_1341 },
|
|
{ "ds3231", ds_3231 },
|
|
{ "m41t0", m41t0 },
|
|
{ "m41t00", m41t00 },
|
|
{ "m41t11", m41t11 },
|
|
{ "mcp7940x", mcp794xx },
|
|
{ "mcp7941x", mcp794xx },
|
|
{ "pt7c4338", ds_1307 },
|
|
{ "rx8025", rx_8025 },
|
|
{ "isl12057", ds_1337 },
|
|
{ "rx8130", rx_8130 },
|
|
{ }
|
|
};
|
|
MODULE_DEVICE_TABLE(i2c, ds1307_id);
|
|
|
|
#ifdef CONFIG_OF
|
|
static const struct of_device_id ds1307_of_match[] = {
|
|
{
|
|
.compatible = "dallas,ds1307",
|
|
.data = (void *)ds_1307
|
|
},
|
|
{
|
|
.compatible = "dallas,ds1308",
|
|
.data = (void *)ds_1308
|
|
},
|
|
{
|
|
.compatible = "dallas,ds1337",
|
|
.data = (void *)ds_1337
|
|
},
|
|
{
|
|
.compatible = "dallas,ds1338",
|
|
.data = (void *)ds_1338
|
|
},
|
|
{
|
|
.compatible = "dallas,ds1339",
|
|
.data = (void *)ds_1339
|
|
},
|
|
{
|
|
.compatible = "dallas,ds1388",
|
|
.data = (void *)ds_1388
|
|
},
|
|
{
|
|
.compatible = "dallas,ds1340",
|
|
.data = (void *)ds_1340
|
|
},
|
|
{
|
|
.compatible = "dallas,ds1341",
|
|
.data = (void *)ds_1341
|
|
},
|
|
{
|
|
.compatible = "maxim,ds3231",
|
|
.data = (void *)ds_3231
|
|
},
|
|
{
|
|
.compatible = "st,m41t0",
|
|
.data = (void *)m41t0
|
|
},
|
|
{
|
|
.compatible = "st,m41t00",
|
|
.data = (void *)m41t00
|
|
},
|
|
{
|
|
.compatible = "st,m41t11",
|
|
.data = (void *)m41t11
|
|
},
|
|
{
|
|
.compatible = "microchip,mcp7940x",
|
|
.data = (void *)mcp794xx
|
|
},
|
|
{
|
|
.compatible = "microchip,mcp7941x",
|
|
.data = (void *)mcp794xx
|
|
},
|
|
{
|
|
.compatible = "pericom,pt7c4338",
|
|
.data = (void *)ds_1307
|
|
},
|
|
{
|
|
.compatible = "epson,rx8025",
|
|
.data = (void *)rx_8025
|
|
},
|
|
{
|
|
.compatible = "isil,isl12057",
|
|
.data = (void *)ds_1337
|
|
},
|
|
{
|
|
.compatible = "epson,rx8130",
|
|
.data = (void *)rx_8130
|
|
},
|
|
{ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, ds1307_of_match);
|
|
#endif
|
|
|
|
#ifdef CONFIG_ACPI
|
|
static const struct acpi_device_id ds1307_acpi_ids[] = {
|
|
{ .id = "DS1307", .driver_data = ds_1307 },
|
|
{ .id = "DS1308", .driver_data = ds_1308 },
|
|
{ .id = "DS1337", .driver_data = ds_1337 },
|
|
{ .id = "DS1338", .driver_data = ds_1338 },
|
|
{ .id = "DS1339", .driver_data = ds_1339 },
|
|
{ .id = "DS1388", .driver_data = ds_1388 },
|
|
{ .id = "DS1340", .driver_data = ds_1340 },
|
|
{ .id = "DS1341", .driver_data = ds_1341 },
|
|
{ .id = "DS3231", .driver_data = ds_3231 },
|
|
{ .id = "M41T0", .driver_data = m41t0 },
|
|
{ .id = "M41T00", .driver_data = m41t00 },
|
|
{ .id = "M41T11", .driver_data = m41t11 },
|
|
{ .id = "MCP7940X", .driver_data = mcp794xx },
|
|
{ .id = "MCP7941X", .driver_data = mcp794xx },
|
|
{ .id = "PT7C4338", .driver_data = ds_1307 },
|
|
{ .id = "RX8025", .driver_data = rx_8025 },
|
|
{ .id = "ISL12057", .driver_data = ds_1337 },
|
|
{ .id = "RX8130", .driver_data = rx_8130 },
|
|
{ }
|
|
};
|
|
MODULE_DEVICE_TABLE(acpi, ds1307_acpi_ids);
|
|
#endif
|
|
|
|
/*
|
|
* The ds1337 and ds1339 both have two alarms, but we only use the first
|
|
* one (with a "seconds" field). For ds1337 we expect nINTA is our alarm
|
|
* signal; ds1339 chips have only one alarm signal.
|
|
*/
|
|
static irqreturn_t ds1307_irq(int irq, void *dev_id)
|
|
{
|
|
struct ds1307 *ds1307 = dev_id;
|
|
struct mutex *lock = &ds1307->rtc->ops_lock;
|
|
int stat, ret;
|
|
|
|
mutex_lock(lock);
|
|
ret = regmap_read(ds1307->regmap, DS1337_REG_STATUS, &stat);
|
|
if (ret)
|
|
goto out;
|
|
|
|
if (stat & DS1337_BIT_A1I) {
|
|
stat &= ~DS1337_BIT_A1I;
|
|
regmap_write(ds1307->regmap, DS1337_REG_STATUS, stat);
|
|
|
|
ret = regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
|
|
DS1337_BIT_A1IE, 0);
|
|
if (ret)
|
|
goto out;
|
|
|
|
rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
|
|
}
|
|
|
|
out:
|
|
mutex_unlock(lock);
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
/*----------------------------------------------------------------------*/
|
|
|
|
static const struct rtc_class_ops ds13xx_rtc_ops = {
|
|
.read_time = ds1307_get_time,
|
|
.set_time = ds1307_set_time,
|
|
.read_alarm = ds1337_read_alarm,
|
|
.set_alarm = ds1337_set_alarm,
|
|
.alarm_irq_enable = ds1307_alarm_irq_enable,
|
|
};
|
|
|
|
static ssize_t frequency_test_store(struct device *dev,
|
|
struct device_attribute *attr,
|
|
const char *buf, size_t count)
|
|
{
|
|
struct ds1307 *ds1307 = dev_get_drvdata(dev->parent);
|
|
bool freq_test_en;
|
|
int ret;
|
|
|
|
ret = kstrtobool(buf, &freq_test_en);
|
|
if (ret) {
|
|
dev_err(dev, "Failed to store RTC Frequency Test attribute\n");
|
|
return ret;
|
|
}
|
|
|
|
regmap_update_bits(ds1307->regmap, M41TXX_REG_CONTROL, M41TXX_BIT_FT,
|
|
freq_test_en ? M41TXX_BIT_FT : 0);
|
|
|
|
return count;
|
|
}
|
|
|
|
static ssize_t frequency_test_show(struct device *dev,
|
|
struct device_attribute *attr,
|
|
char *buf)
|
|
{
|
|
struct ds1307 *ds1307 = dev_get_drvdata(dev->parent);
|
|
unsigned int ctrl_reg;
|
|
|
|
regmap_read(ds1307->regmap, M41TXX_REG_CONTROL, &ctrl_reg);
|
|
|
|
return scnprintf(buf, PAGE_SIZE, (ctrl_reg & M41TXX_BIT_FT) ? "on\n" :
|
|
"off\n");
|
|
}
|
|
|
|
static DEVICE_ATTR_RW(frequency_test);
|
|
|
|
static struct attribute *rtc_freq_test_attrs[] = {
|
|
&dev_attr_frequency_test.attr,
|
|
NULL,
|
|
};
|
|
|
|
static const struct attribute_group rtc_freq_test_attr_group = {
|
|
.attrs = rtc_freq_test_attrs,
|
|
};
|
|
|
|
static int ds1307_add_frequency_test(struct ds1307 *ds1307)
|
|
{
|
|
int err;
|
|
|
|
switch (ds1307->type) {
|
|
case m41t0:
|
|
case m41t00:
|
|
case m41t11:
|
|
err = rtc_add_group(ds1307->rtc, &rtc_freq_test_attr_group);
|
|
if (err)
|
|
return err;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*----------------------------------------------------------------------*/
|
|
|
|
static int ds1307_nvram_read(void *priv, unsigned int offset, void *val,
|
|
size_t bytes)
|
|
{
|
|
struct ds1307 *ds1307 = priv;
|
|
const struct chip_desc *chip = &chips[ds1307->type];
|
|
|
|
return regmap_bulk_read(ds1307->regmap, chip->nvram_offset + offset,
|
|
val, bytes);
|
|
}
|
|
|
|
static int ds1307_nvram_write(void *priv, unsigned int offset, void *val,
|
|
size_t bytes)
|
|
{
|
|
struct ds1307 *ds1307 = priv;
|
|
const struct chip_desc *chip = &chips[ds1307->type];
|
|
|
|
return regmap_bulk_write(ds1307->regmap, chip->nvram_offset + offset,
|
|
val, bytes);
|
|
}
|
|
|
|
/*----------------------------------------------------------------------*/
|
|
|
|
static u8 ds1307_trickle_init(struct ds1307 *ds1307,
|
|
const struct chip_desc *chip)
|
|
{
|
|
u32 ohms;
|
|
bool diode = true;
|
|
|
|
if (!chip->do_trickle_setup)
|
|
return 0;
|
|
|
|
if (device_property_read_u32(ds1307->dev, "trickle-resistor-ohms",
|
|
&ohms))
|
|
return 0;
|
|
|
|
if (device_property_read_bool(ds1307->dev, "trickle-diode-disable"))
|
|
diode = false;
|
|
|
|
return chip->do_trickle_setup(ds1307, ohms, diode);
|
|
}
|
|
|
|
/*----------------------------------------------------------------------*/
|
|
|
|
#if IS_REACHABLE(CONFIG_HWMON)
|
|
|
|
/*
|
|
* Temperature sensor support for ds3231 devices.
|
|
*/
|
|
|
|
#define DS3231_REG_TEMPERATURE 0x11
|
|
|
|
/*
|
|
* A user-initiated temperature conversion is not started by this function,
|
|
* so the temperature is updated once every 64 seconds.
|
|
*/
|
|
static int ds3231_hwmon_read_temp(struct device *dev, s32 *mC)
|
|
{
|
|
struct ds1307 *ds1307 = dev_get_drvdata(dev);
|
|
u8 temp_buf[2];
|
|
s16 temp;
|
|
int ret;
|
|
|
|
ret = regmap_bulk_read(ds1307->regmap, DS3231_REG_TEMPERATURE,
|
|
temp_buf, sizeof(temp_buf));
|
|
if (ret)
|
|
return ret;
|
|
/*
|
|
* Temperature is represented as a 10-bit code with a resolution of
|
|
* 0.25 degree celsius and encoded in two's complement format.
|
|
*/
|
|
temp = (temp_buf[0] << 8) | temp_buf[1];
|
|
temp >>= 6;
|
|
*mC = temp * 250;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static ssize_t ds3231_hwmon_show_temp(struct device *dev,
|
|
struct device_attribute *attr, char *buf)
|
|
{
|
|
int ret;
|
|
s32 temp;
|
|
|
|
ret = ds3231_hwmon_read_temp(dev, &temp);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return sprintf(buf, "%d\n", temp);
|
|
}
|
|
static SENSOR_DEVICE_ATTR(temp1_input, 0444, ds3231_hwmon_show_temp,
|
|
NULL, 0);
|
|
|
|
static struct attribute *ds3231_hwmon_attrs[] = {
|
|
&sensor_dev_attr_temp1_input.dev_attr.attr,
|
|
NULL,
|
|
};
|
|
ATTRIBUTE_GROUPS(ds3231_hwmon);
|
|
|
|
static void ds1307_hwmon_register(struct ds1307 *ds1307)
|
|
{
|
|
struct device *dev;
|
|
|
|
if (ds1307->type != ds_3231)
|
|
return;
|
|
|
|
dev = devm_hwmon_device_register_with_groups(ds1307->dev, ds1307->name,
|
|
ds1307,
|
|
ds3231_hwmon_groups);
|
|
if (IS_ERR(dev)) {
|
|
dev_warn(ds1307->dev, "unable to register hwmon device %ld\n",
|
|
PTR_ERR(dev));
|
|
}
|
|
}
|
|
|
|
#else
|
|
|
|
static void ds1307_hwmon_register(struct ds1307 *ds1307)
|
|
{
|
|
}
|
|
|
|
#endif /* CONFIG_RTC_DRV_DS1307_HWMON */
|
|
|
|
/*----------------------------------------------------------------------*/
|
|
|
|
/*
|
|
* Square-wave output support for DS3231
|
|
* Datasheet: https://datasheets.maximintegrated.com/en/ds/DS3231.pdf
|
|
*/
|
|
#ifdef CONFIG_COMMON_CLK
|
|
|
|
enum {
|
|
DS3231_CLK_SQW = 0,
|
|
DS3231_CLK_32KHZ,
|
|
};
|
|
|
|
#define clk_sqw_to_ds1307(clk) \
|
|
container_of(clk, struct ds1307, clks[DS3231_CLK_SQW])
|
|
#define clk_32khz_to_ds1307(clk) \
|
|
container_of(clk, struct ds1307, clks[DS3231_CLK_32KHZ])
|
|
|
|
static int ds3231_clk_sqw_rates[] = {
|
|
1,
|
|
1024,
|
|
4096,
|
|
8192,
|
|
};
|
|
|
|
static int ds1337_write_control(struct ds1307 *ds1307, u8 mask, u8 value)
|
|
{
|
|
struct mutex *lock = &ds1307->rtc->ops_lock;
|
|
int ret;
|
|
|
|
mutex_lock(lock);
|
|
ret = regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
|
|
mask, value);
|
|
mutex_unlock(lock);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static unsigned long ds3231_clk_sqw_recalc_rate(struct clk_hw *hw,
|
|
unsigned long parent_rate)
|
|
{
|
|
struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
|
|
int control, ret;
|
|
int rate_sel = 0;
|
|
|
|
ret = regmap_read(ds1307->regmap, DS1337_REG_CONTROL, &control);
|
|
if (ret)
|
|
return ret;
|
|
if (control & DS1337_BIT_RS1)
|
|
rate_sel += 1;
|
|
if (control & DS1337_BIT_RS2)
|
|
rate_sel += 2;
|
|
|
|
return ds3231_clk_sqw_rates[rate_sel];
|
|
}
|
|
|
|
static long ds3231_clk_sqw_round_rate(struct clk_hw *hw, unsigned long rate,
|
|
unsigned long *prate)
|
|
{
|
|
int i;
|
|
|
|
for (i = ARRAY_SIZE(ds3231_clk_sqw_rates) - 1; i >= 0; i--) {
|
|
if (ds3231_clk_sqw_rates[i] <= rate)
|
|
return ds3231_clk_sqw_rates[i];
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ds3231_clk_sqw_set_rate(struct clk_hw *hw, unsigned long rate,
|
|
unsigned long parent_rate)
|
|
{
|
|
struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
|
|
int control = 0;
|
|
int rate_sel;
|
|
|
|
for (rate_sel = 0; rate_sel < ARRAY_SIZE(ds3231_clk_sqw_rates);
|
|
rate_sel++) {
|
|
if (ds3231_clk_sqw_rates[rate_sel] == rate)
|
|
break;
|
|
}
|
|
|
|
if (rate_sel == ARRAY_SIZE(ds3231_clk_sqw_rates))
|
|
return -EINVAL;
|
|
|
|
if (rate_sel & 1)
|
|
control |= DS1337_BIT_RS1;
|
|
if (rate_sel & 2)
|
|
control |= DS1337_BIT_RS2;
|
|
|
|
return ds1337_write_control(ds1307, DS1337_BIT_RS1 | DS1337_BIT_RS2,
|
|
control);
|
|
}
|
|
|
|
static int ds3231_clk_sqw_prepare(struct clk_hw *hw)
|
|
{
|
|
struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
|
|
|
|
return ds1337_write_control(ds1307, DS1337_BIT_INTCN, 0);
|
|
}
|
|
|
|
static void ds3231_clk_sqw_unprepare(struct clk_hw *hw)
|
|
{
|
|
struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
|
|
|
|
ds1337_write_control(ds1307, DS1337_BIT_INTCN, DS1337_BIT_INTCN);
|
|
}
|
|
|
|
static int ds3231_clk_sqw_is_prepared(struct clk_hw *hw)
|
|
{
|
|
struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
|
|
int control, ret;
|
|
|
|
ret = regmap_read(ds1307->regmap, DS1337_REG_CONTROL, &control);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return !(control & DS1337_BIT_INTCN);
|
|
}
|
|
|
|
static const struct clk_ops ds3231_clk_sqw_ops = {
|
|
.prepare = ds3231_clk_sqw_prepare,
|
|
.unprepare = ds3231_clk_sqw_unprepare,
|
|
.is_prepared = ds3231_clk_sqw_is_prepared,
|
|
.recalc_rate = ds3231_clk_sqw_recalc_rate,
|
|
.round_rate = ds3231_clk_sqw_round_rate,
|
|
.set_rate = ds3231_clk_sqw_set_rate,
|
|
};
|
|
|
|
static unsigned long ds3231_clk_32khz_recalc_rate(struct clk_hw *hw,
|
|
unsigned long parent_rate)
|
|
{
|
|
return 32768;
|
|
}
|
|
|
|
static int ds3231_clk_32khz_control(struct ds1307 *ds1307, bool enable)
|
|
{
|
|
struct mutex *lock = &ds1307->rtc->ops_lock;
|
|
int ret;
|
|
|
|
mutex_lock(lock);
|
|
ret = regmap_update_bits(ds1307->regmap, DS1337_REG_STATUS,
|
|
DS3231_BIT_EN32KHZ,
|
|
enable ? DS3231_BIT_EN32KHZ : 0);
|
|
mutex_unlock(lock);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int ds3231_clk_32khz_prepare(struct clk_hw *hw)
|
|
{
|
|
struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
|
|
|
|
return ds3231_clk_32khz_control(ds1307, true);
|
|
}
|
|
|
|
static void ds3231_clk_32khz_unprepare(struct clk_hw *hw)
|
|
{
|
|
struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
|
|
|
|
ds3231_clk_32khz_control(ds1307, false);
|
|
}
|
|
|
|
static int ds3231_clk_32khz_is_prepared(struct clk_hw *hw)
|
|
{
|
|
struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
|
|
int status, ret;
|
|
|
|
ret = regmap_read(ds1307->regmap, DS1337_REG_STATUS, &status);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return !!(status & DS3231_BIT_EN32KHZ);
|
|
}
|
|
|
|
static const struct clk_ops ds3231_clk_32khz_ops = {
|
|
.prepare = ds3231_clk_32khz_prepare,
|
|
.unprepare = ds3231_clk_32khz_unprepare,
|
|
.is_prepared = ds3231_clk_32khz_is_prepared,
|
|
.recalc_rate = ds3231_clk_32khz_recalc_rate,
|
|
};
|
|
|
|
static struct clk_init_data ds3231_clks_init[] = {
|
|
[DS3231_CLK_SQW] = {
|
|
.name = "ds3231_clk_sqw",
|
|
.ops = &ds3231_clk_sqw_ops,
|
|
},
|
|
[DS3231_CLK_32KHZ] = {
|
|
.name = "ds3231_clk_32khz",
|
|
.ops = &ds3231_clk_32khz_ops,
|
|
},
|
|
};
|
|
|
|
static int ds3231_clks_register(struct ds1307 *ds1307)
|
|
{
|
|
struct device_node *node = ds1307->dev->of_node;
|
|
struct clk_onecell_data *onecell;
|
|
int i;
|
|
|
|
onecell = devm_kzalloc(ds1307->dev, sizeof(*onecell), GFP_KERNEL);
|
|
if (!onecell)
|
|
return -ENOMEM;
|
|
|
|
onecell->clk_num = ARRAY_SIZE(ds3231_clks_init);
|
|
onecell->clks = devm_kcalloc(ds1307->dev, onecell->clk_num,
|
|
sizeof(onecell->clks[0]), GFP_KERNEL);
|
|
if (!onecell->clks)
|
|
return -ENOMEM;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(ds3231_clks_init); i++) {
|
|
struct clk_init_data init = ds3231_clks_init[i];
|
|
|
|
/*
|
|
* Interrupt signal due to alarm conditions and square-wave
|
|
* output share same pin, so don't initialize both.
|
|
*/
|
|
if (i == DS3231_CLK_SQW && test_bit(HAS_ALARM, &ds1307->flags))
|
|
continue;
|
|
|
|
/* optional override of the clockname */
|
|
of_property_read_string_index(node, "clock-output-names", i,
|
|
&init.name);
|
|
ds1307->clks[i].init = &init;
|
|
|
|
onecell->clks[i] = devm_clk_register(ds1307->dev,
|
|
&ds1307->clks[i]);
|
|
if (IS_ERR(onecell->clks[i]))
|
|
return PTR_ERR(onecell->clks[i]);
|
|
}
|
|
|
|
if (!node)
|
|
return 0;
|
|
|
|
of_clk_add_provider(node, of_clk_src_onecell_get, onecell);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void ds1307_clks_register(struct ds1307 *ds1307)
|
|
{
|
|
int ret;
|
|
|
|
if (ds1307->type != ds_3231)
|
|
return;
|
|
|
|
ret = ds3231_clks_register(ds1307);
|
|
if (ret) {
|
|
dev_warn(ds1307->dev, "unable to register clock device %d\n",
|
|
ret);
|
|
}
|
|
}
|
|
|
|
#else
|
|
|
|
static void ds1307_clks_register(struct ds1307 *ds1307)
|
|
{
|
|
}
|
|
|
|
#endif /* CONFIG_COMMON_CLK */
|
|
|
|
static const struct regmap_config regmap_config = {
|
|
.reg_bits = 8,
|
|
.val_bits = 8,
|
|
};
|
|
|
|
static int ds1307_probe(struct i2c_client *client,
|
|
const struct i2c_device_id *id)
|
|
{
|
|
struct ds1307 *ds1307;
|
|
int err = -ENODEV;
|
|
int tmp;
|
|
const struct chip_desc *chip;
|
|
bool want_irq;
|
|
bool ds1307_can_wakeup_device = false;
|
|
unsigned char regs[8];
|
|
struct ds1307_platform_data *pdata = dev_get_platdata(&client->dev);
|
|
u8 trickle_charger_setup = 0;
|
|
|
|
ds1307 = devm_kzalloc(&client->dev, sizeof(struct ds1307), GFP_KERNEL);
|
|
if (!ds1307)
|
|
return -ENOMEM;
|
|
|
|
dev_set_drvdata(&client->dev, ds1307);
|
|
ds1307->dev = &client->dev;
|
|
ds1307->name = client->name;
|
|
|
|
ds1307->regmap = devm_regmap_init_i2c(client, ®map_config);
|
|
if (IS_ERR(ds1307->regmap)) {
|
|
dev_err(ds1307->dev, "regmap allocation failed\n");
|
|
return PTR_ERR(ds1307->regmap);
|
|
}
|
|
|
|
i2c_set_clientdata(client, ds1307);
|
|
|
|
if (client->dev.of_node) {
|
|
ds1307->type = (enum ds_type)
|
|
of_device_get_match_data(&client->dev);
|
|
chip = &chips[ds1307->type];
|
|
} else if (id) {
|
|
chip = &chips[id->driver_data];
|
|
ds1307->type = id->driver_data;
|
|
} else {
|
|
const struct acpi_device_id *acpi_id;
|
|
|
|
acpi_id = acpi_match_device(ACPI_PTR(ds1307_acpi_ids),
|
|
ds1307->dev);
|
|
if (!acpi_id)
|
|
return -ENODEV;
|
|
chip = &chips[acpi_id->driver_data];
|
|
ds1307->type = acpi_id->driver_data;
|
|
}
|
|
|
|
want_irq = client->irq > 0 && chip->alarm;
|
|
|
|
if (!pdata)
|
|
trickle_charger_setup = ds1307_trickle_init(ds1307, chip);
|
|
else if (pdata->trickle_charger_setup)
|
|
trickle_charger_setup = pdata->trickle_charger_setup;
|
|
|
|
if (trickle_charger_setup && chip->trickle_charger_reg) {
|
|
trickle_charger_setup |= DS13XX_TRICKLE_CHARGER_MAGIC;
|
|
dev_dbg(ds1307->dev,
|
|
"writing trickle charger info 0x%x to 0x%x\n",
|
|
trickle_charger_setup, chip->trickle_charger_reg);
|
|
regmap_write(ds1307->regmap, chip->trickle_charger_reg,
|
|
trickle_charger_setup);
|
|
}
|
|
|
|
#ifdef CONFIG_OF
|
|
/*
|
|
* For devices with no IRQ directly connected to the SoC, the RTC chip
|
|
* can be forced as a wakeup source by stating that explicitly in
|
|
* the device's .dts file using the "wakeup-source" boolean property.
|
|
* If the "wakeup-source" property is set, don't request an IRQ.
|
|
* This will guarantee the 'wakealarm' sysfs entry is available on the device,
|
|
* if supported by the RTC.
|
|
*/
|
|
if (chip->alarm && of_property_read_bool(client->dev.of_node,
|
|
"wakeup-source"))
|
|
ds1307_can_wakeup_device = true;
|
|
#endif
|
|
|
|
switch (ds1307->type) {
|
|
case ds_1337:
|
|
case ds_1339:
|
|
case ds_1341:
|
|
case ds_3231:
|
|
/* get registers that the "rtc" read below won't read... */
|
|
err = regmap_bulk_read(ds1307->regmap, DS1337_REG_CONTROL,
|
|
regs, 2);
|
|
if (err) {
|
|
dev_dbg(ds1307->dev, "read error %d\n", err);
|
|
goto exit;
|
|
}
|
|
|
|
/* oscillator off? turn it on, so clock can tick. */
|
|
if (regs[0] & DS1337_BIT_nEOSC)
|
|
regs[0] &= ~DS1337_BIT_nEOSC;
|
|
|
|
/*
|
|
* Using IRQ or defined as wakeup-source?
|
|
* Disable the square wave and both alarms.
|
|
* For some variants, be sure alarms can trigger when we're
|
|
* running on Vbackup (BBSQI/BBSQW)
|
|
*/
|
|
if (want_irq || ds1307_can_wakeup_device) {
|
|
regs[0] |= DS1337_BIT_INTCN | chip->bbsqi_bit;
|
|
regs[0] &= ~(DS1337_BIT_A2IE | DS1337_BIT_A1IE);
|
|
}
|
|
|
|
regmap_write(ds1307->regmap, DS1337_REG_CONTROL,
|
|
regs[0]);
|
|
|
|
/* oscillator fault? clear flag, and warn */
|
|
if (regs[1] & DS1337_BIT_OSF) {
|
|
regmap_write(ds1307->regmap, DS1337_REG_STATUS,
|
|
regs[1] & ~DS1337_BIT_OSF);
|
|
dev_warn(ds1307->dev, "SET TIME!\n");
|
|
}
|
|
break;
|
|
|
|
case rx_8025:
|
|
err = regmap_bulk_read(ds1307->regmap,
|
|
RX8025_REG_CTRL1 << 4 | 0x08, regs, 2);
|
|
if (err) {
|
|
dev_dbg(ds1307->dev, "read error %d\n", err);
|
|
goto exit;
|
|
}
|
|
|
|
/* oscillator off? turn it on, so clock can tick. */
|
|
if (!(regs[1] & RX8025_BIT_XST)) {
|
|
regs[1] |= RX8025_BIT_XST;
|
|
regmap_write(ds1307->regmap,
|
|
RX8025_REG_CTRL2 << 4 | 0x08,
|
|
regs[1]);
|
|
dev_warn(ds1307->dev,
|
|
"oscillator stop detected - SET TIME!\n");
|
|
}
|
|
|
|
if (regs[1] & RX8025_BIT_PON) {
|
|
regs[1] &= ~RX8025_BIT_PON;
|
|
regmap_write(ds1307->regmap,
|
|
RX8025_REG_CTRL2 << 4 | 0x08,
|
|
regs[1]);
|
|
dev_warn(ds1307->dev, "power-on detected\n");
|
|
}
|
|
|
|
if (regs[1] & RX8025_BIT_VDET) {
|
|
regs[1] &= ~RX8025_BIT_VDET;
|
|
regmap_write(ds1307->regmap,
|
|
RX8025_REG_CTRL2 << 4 | 0x08,
|
|
regs[1]);
|
|
dev_warn(ds1307->dev, "voltage drop detected\n");
|
|
}
|
|
|
|
/* make sure we are running in 24hour mode */
|
|
if (!(regs[0] & RX8025_BIT_2412)) {
|
|
u8 hour;
|
|
|
|
/* switch to 24 hour mode */
|
|
regmap_write(ds1307->regmap,
|
|
RX8025_REG_CTRL1 << 4 | 0x08,
|
|
regs[0] | RX8025_BIT_2412);
|
|
|
|
err = regmap_bulk_read(ds1307->regmap,
|
|
RX8025_REG_CTRL1 << 4 | 0x08,
|
|
regs, 2);
|
|
if (err) {
|
|
dev_dbg(ds1307->dev, "read error %d\n", err);
|
|
goto exit;
|
|
}
|
|
|
|
/* correct hour */
|
|
hour = bcd2bin(regs[DS1307_REG_HOUR]);
|
|
if (hour == 12)
|
|
hour = 0;
|
|
if (regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
|
|
hour += 12;
|
|
|
|
regmap_write(ds1307->regmap,
|
|
DS1307_REG_HOUR << 4 | 0x08, hour);
|
|
}
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
read_rtc:
|
|
/* read RTC registers */
|
|
err = regmap_bulk_read(ds1307->regmap, chip->offset, regs,
|
|
sizeof(regs));
|
|
if (err) {
|
|
dev_dbg(ds1307->dev, "read error %d\n", err);
|
|
goto exit;
|
|
}
|
|
|
|
/*
|
|
* minimal sanity checking; some chips (like DS1340) don't
|
|
* specify the extra bits as must-be-zero, but there are
|
|
* still a few values that are clearly out-of-range.
|
|
*/
|
|
tmp = regs[DS1307_REG_SECS];
|
|
switch (ds1307->type) {
|
|
case ds_1307:
|
|
case m41t0:
|
|
case m41t00:
|
|
case m41t11:
|
|
/* clock halted? turn it on, so clock can tick. */
|
|
if (tmp & DS1307_BIT_CH) {
|
|
regmap_write(ds1307->regmap, DS1307_REG_SECS, 0);
|
|
dev_warn(ds1307->dev, "SET TIME!\n");
|
|
goto read_rtc;
|
|
}
|
|
break;
|
|
case ds_1308:
|
|
case ds_1338:
|
|
/* clock halted? turn it on, so clock can tick. */
|
|
if (tmp & DS1307_BIT_CH)
|
|
regmap_write(ds1307->regmap, DS1307_REG_SECS, 0);
|
|
|
|
/* oscillator fault? clear flag, and warn */
|
|
if (regs[DS1307_REG_CONTROL] & DS1338_BIT_OSF) {
|
|
regmap_write(ds1307->regmap, DS1307_REG_CONTROL,
|
|
regs[DS1307_REG_CONTROL] &
|
|
~DS1338_BIT_OSF);
|
|
dev_warn(ds1307->dev, "SET TIME!\n");
|
|
goto read_rtc;
|
|
}
|
|
break;
|
|
case ds_1340:
|
|
/* clock halted? turn it on, so clock can tick. */
|
|
if (tmp & DS1340_BIT_nEOSC)
|
|
regmap_write(ds1307->regmap, DS1307_REG_SECS, 0);
|
|
|
|
err = regmap_read(ds1307->regmap, DS1340_REG_FLAG, &tmp);
|
|
if (err) {
|
|
dev_dbg(ds1307->dev, "read error %d\n", err);
|
|
goto exit;
|
|
}
|
|
|
|
/* oscillator fault? clear flag, and warn */
|
|
if (tmp & DS1340_BIT_OSF) {
|
|
regmap_write(ds1307->regmap, DS1340_REG_FLAG, 0);
|
|
dev_warn(ds1307->dev, "SET TIME!\n");
|
|
}
|
|
break;
|
|
case mcp794xx:
|
|
/* make sure that the backup battery is enabled */
|
|
if (!(regs[DS1307_REG_WDAY] & MCP794XX_BIT_VBATEN)) {
|
|
regmap_write(ds1307->regmap, DS1307_REG_WDAY,
|
|
regs[DS1307_REG_WDAY] |
|
|
MCP794XX_BIT_VBATEN);
|
|
}
|
|
|
|
/* clock halted? turn it on, so clock can tick. */
|
|
if (!(tmp & MCP794XX_BIT_ST)) {
|
|
regmap_write(ds1307->regmap, DS1307_REG_SECS,
|
|
MCP794XX_BIT_ST);
|
|
dev_warn(ds1307->dev, "SET TIME!\n");
|
|
goto read_rtc;
|
|
}
|
|
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
tmp = regs[DS1307_REG_HOUR];
|
|
switch (ds1307->type) {
|
|
case ds_1340:
|
|
case m41t0:
|
|
case m41t00:
|
|
case m41t11:
|
|
/*
|
|
* NOTE: ignores century bits; fix before deploying
|
|
* systems that will run through year 2100.
|
|
*/
|
|
break;
|
|
case rx_8025:
|
|
break;
|
|
default:
|
|
if (!(tmp & DS1307_BIT_12HR))
|
|
break;
|
|
|
|
/*
|
|
* Be sure we're in 24 hour mode. Multi-master systems
|
|
* take note...
|
|
*/
|
|
tmp = bcd2bin(tmp & 0x1f);
|
|
if (tmp == 12)
|
|
tmp = 0;
|
|
if (regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
|
|
tmp += 12;
|
|
regmap_write(ds1307->regmap, chip->offset + DS1307_REG_HOUR,
|
|
bin2bcd(tmp));
|
|
}
|
|
|
|
if (want_irq || ds1307_can_wakeup_device) {
|
|
device_set_wakeup_capable(ds1307->dev, true);
|
|
set_bit(HAS_ALARM, &ds1307->flags);
|
|
}
|
|
|
|
ds1307->rtc = devm_rtc_allocate_device(ds1307->dev);
|
|
if (IS_ERR(ds1307->rtc))
|
|
return PTR_ERR(ds1307->rtc);
|
|
|
|
if (ds1307_can_wakeup_device && !want_irq) {
|
|
dev_info(ds1307->dev,
|
|
"'wakeup-source' is set, request for an IRQ is disabled!\n");
|
|
/* We cannot support UIE mode if we do not have an IRQ line */
|
|
ds1307->rtc->uie_unsupported = 1;
|
|
}
|
|
|
|
if (want_irq) {
|
|
err = devm_request_threaded_irq(ds1307->dev, client->irq, NULL,
|
|
chip->irq_handler ?: ds1307_irq,
|
|
IRQF_SHARED | IRQF_ONESHOT,
|
|
ds1307->name, ds1307);
|
|
if (err) {
|
|
client->irq = 0;
|
|
device_set_wakeup_capable(ds1307->dev, false);
|
|
clear_bit(HAS_ALARM, &ds1307->flags);
|
|
dev_err(ds1307->dev, "unable to request IRQ!\n");
|
|
} else {
|
|
dev_dbg(ds1307->dev, "got IRQ %d\n", client->irq);
|
|
}
|
|
}
|
|
|
|
ds1307->rtc->ops = chip->rtc_ops ?: &ds13xx_rtc_ops;
|
|
err = ds1307_add_frequency_test(ds1307);
|
|
if (err)
|
|
return err;
|
|
|
|
err = rtc_register_device(ds1307->rtc);
|
|
if (err)
|
|
return err;
|
|
|
|
if (chip->nvram_size) {
|
|
struct nvmem_config nvmem_cfg = {
|
|
.name = "ds1307_nvram",
|
|
.word_size = 1,
|
|
.stride = 1,
|
|
.size = chip->nvram_size,
|
|
.reg_read = ds1307_nvram_read,
|
|
.reg_write = ds1307_nvram_write,
|
|
.priv = ds1307,
|
|
};
|
|
|
|
ds1307->rtc->nvram_old_abi = true;
|
|
rtc_nvmem_register(ds1307->rtc, &nvmem_cfg);
|
|
}
|
|
|
|
ds1307_hwmon_register(ds1307);
|
|
ds1307_clks_register(ds1307);
|
|
|
|
return 0;
|
|
|
|
exit:
|
|
return err;
|
|
}
|
|
|
|
static struct i2c_driver ds1307_driver = {
|
|
.driver = {
|
|
.name = "rtc-ds1307",
|
|
.of_match_table = of_match_ptr(ds1307_of_match),
|
|
.acpi_match_table = ACPI_PTR(ds1307_acpi_ids),
|
|
},
|
|
.probe = ds1307_probe,
|
|
.id_table = ds1307_id,
|
|
};
|
|
|
|
module_i2c_driver(ds1307_driver);
|
|
|
|
MODULE_DESCRIPTION("RTC driver for DS1307 and similar chips");
|
|
MODULE_LICENSE("GPL");
|