![Yevgeny Petrilin](/assets/img/avatar_default.png)
The Mellanox ConnectX can operate as an InfiniBand adapter, as an Ethernet NIC, or as a Fibre Channel (FC) HBA. The kernel has a low-level driver, mlx4_core, which handles multiplexing access to the device, and there is also already an InfiniBad driver, mlx4_ib. This patch adds a new driver, mlx4_en, which implements a standard Ethernet NIC driver. Signed-off-by: Liran Liss <liranl@mellanox.co.il> Signed-off-by: Yevgeny Petrilin <yevgenyp@mellanox.co.il> Signed-off-by: Roland Dreier <rolandd@cisco.com>
821 lines
23 KiB
C
821 lines
23 KiB
C
/*
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* Copyright (c) 2007 Mellanox Technologies. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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*/
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#include <asm/page.h>
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#include <linux/mlx4/cq.h>
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#include <linux/mlx4/qp.h>
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#include <linux/skbuff.h>
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#include <linux/if_vlan.h>
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#include <linux/vmalloc.h>
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#include "mlx4_en.h"
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enum {
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MAX_INLINE = 104, /* 128 - 16 - 4 - 4 */
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};
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static int inline_thold __read_mostly = MAX_INLINE;
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module_param_named(inline_thold, inline_thold, int, 0444);
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MODULE_PARM_DESC(inline_thold, "treshold for using inline data");
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int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv,
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struct mlx4_en_tx_ring *ring, u32 size,
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u16 stride)
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{
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struct mlx4_en_dev *mdev = priv->mdev;
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int tmp;
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int err;
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ring->size = size;
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ring->size_mask = size - 1;
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ring->stride = stride;
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inline_thold = min(inline_thold, MAX_INLINE);
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spin_lock_init(&ring->comp_lock);
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tmp = size * sizeof(struct mlx4_en_tx_info);
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ring->tx_info = vmalloc(tmp);
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if (!ring->tx_info) {
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mlx4_err(mdev, "Failed allocating tx_info ring\n");
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return -ENOMEM;
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}
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mlx4_dbg(DRV, priv, "Allocated tx_info ring at addr:%p size:%d\n",
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ring->tx_info, tmp);
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ring->bounce_buf = kmalloc(MAX_DESC_SIZE, GFP_KERNEL);
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if (!ring->bounce_buf) {
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mlx4_err(mdev, "Failed allocating bounce buffer\n");
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err = -ENOMEM;
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goto err_tx;
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}
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ring->buf_size = ALIGN(size * ring->stride, MLX4_EN_PAGE_SIZE);
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err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres, ring->buf_size,
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2 * PAGE_SIZE);
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if (err) {
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mlx4_err(mdev, "Failed allocating hwq resources\n");
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goto err_bounce;
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}
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err = mlx4_en_map_buffer(&ring->wqres.buf);
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if (err) {
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mlx4_err(mdev, "Failed to map TX buffer\n");
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goto err_hwq_res;
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}
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ring->buf = ring->wqres.buf.direct.buf;
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mlx4_dbg(DRV, priv, "Allocated TX ring (addr:%p) - buf:%p size:%d "
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"buf_size:%d dma:%llx\n", ring, ring->buf, ring->size,
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ring->buf_size, (unsigned long long) ring->wqres.buf.direct.map);
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err = mlx4_qp_reserve_range(mdev->dev, 1, 1, &ring->qpn);
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if (err) {
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mlx4_err(mdev, "Failed reserving qp for tx ring.\n");
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goto err_map;
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}
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err = mlx4_qp_alloc(mdev->dev, ring->qpn, &ring->qp);
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if (err) {
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mlx4_err(mdev, "Failed allocating qp %d\n", ring->qpn);
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goto err_reserve;
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}
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return 0;
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err_reserve:
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mlx4_qp_release_range(mdev->dev, ring->qpn, 1);
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err_map:
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mlx4_en_unmap_buffer(&ring->wqres.buf);
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err_hwq_res:
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mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size);
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err_bounce:
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kfree(ring->bounce_buf);
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ring->bounce_buf = NULL;
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err_tx:
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vfree(ring->tx_info);
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ring->tx_info = NULL;
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return err;
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}
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void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv,
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struct mlx4_en_tx_ring *ring)
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{
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struct mlx4_en_dev *mdev = priv->mdev;
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mlx4_dbg(DRV, priv, "Destroying tx ring, qpn: %d\n", ring->qpn);
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mlx4_qp_remove(mdev->dev, &ring->qp);
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mlx4_qp_free(mdev->dev, &ring->qp);
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mlx4_qp_release_range(mdev->dev, ring->qpn, 1);
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mlx4_en_unmap_buffer(&ring->wqres.buf);
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mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size);
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kfree(ring->bounce_buf);
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ring->bounce_buf = NULL;
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vfree(ring->tx_info);
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ring->tx_info = NULL;
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}
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int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,
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struct mlx4_en_tx_ring *ring,
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int cq, int srqn)
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{
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struct mlx4_en_dev *mdev = priv->mdev;
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int err;
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ring->cqn = cq;
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ring->prod = 0;
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ring->cons = 0xffffffff;
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ring->last_nr_txbb = 1;
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ring->poll_cnt = 0;
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ring->blocked = 0;
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memset(ring->tx_info, 0, ring->size * sizeof(struct mlx4_en_tx_info));
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memset(ring->buf, 0, ring->buf_size);
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ring->qp_state = MLX4_QP_STATE_RST;
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ring->doorbell_qpn = swab32(ring->qp.qpn << 8);
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mlx4_en_fill_qp_context(priv, ring->size, ring->stride, 1, 0, ring->qpn,
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ring->cqn, srqn, &ring->context);
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err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, &ring->context,
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&ring->qp, &ring->qp_state);
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return err;
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}
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void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,
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struct mlx4_en_tx_ring *ring)
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{
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struct mlx4_en_dev *mdev = priv->mdev;
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mlx4_qp_modify(mdev->dev, NULL, ring->qp_state,
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MLX4_QP_STATE_RST, NULL, 0, 0, &ring->qp);
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}
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static u32 mlx4_en_free_tx_desc(struct mlx4_en_priv *priv,
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struct mlx4_en_tx_ring *ring,
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int index, u8 owner)
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{
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struct mlx4_en_dev *mdev = priv->mdev;
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struct mlx4_en_tx_info *tx_info = &ring->tx_info[index];
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struct mlx4_en_tx_desc *tx_desc = ring->buf + index * TXBB_SIZE;
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struct mlx4_wqe_data_seg *data = (void *) tx_desc + tx_info->data_offset;
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struct sk_buff *skb = tx_info->skb;
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struct skb_frag_struct *frag;
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void *end = ring->buf + ring->buf_size;
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int frags = skb_shinfo(skb)->nr_frags;
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int i;
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__be32 *ptr = (__be32 *)tx_desc;
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__be32 stamp = cpu_to_be32(STAMP_VAL | (!!owner << STAMP_SHIFT));
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/* Optimize the common case when there are no wraparounds */
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if (likely((void *) tx_desc + tx_info->nr_txbb * TXBB_SIZE <= end)) {
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if (tx_info->linear) {
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pci_unmap_single(mdev->pdev,
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(dma_addr_t) be64_to_cpu(data->addr),
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be32_to_cpu(data->byte_count),
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PCI_DMA_TODEVICE);
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++data;
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}
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for (i = 0; i < frags; i++) {
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frag = &skb_shinfo(skb)->frags[i];
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pci_unmap_page(mdev->pdev,
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(dma_addr_t) be64_to_cpu(data[i].addr),
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frag->size, PCI_DMA_TODEVICE);
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}
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/* Stamp the freed descriptor */
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for (i = 0; i < tx_info->nr_txbb * TXBB_SIZE; i += STAMP_STRIDE) {
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*ptr = stamp;
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ptr += STAMP_DWORDS;
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}
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} else {
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if ((void *) data >= end) {
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data = (struct mlx4_wqe_data_seg *)
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(ring->buf + ((void *) data - end));
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}
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if (tx_info->linear) {
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pci_unmap_single(mdev->pdev,
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(dma_addr_t) be64_to_cpu(data->addr),
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be32_to_cpu(data->byte_count),
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PCI_DMA_TODEVICE);
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++data;
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}
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for (i = 0; i < frags; i++) {
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/* Check for wraparound before unmapping */
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if ((void *) data >= end)
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data = (struct mlx4_wqe_data_seg *) ring->buf;
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frag = &skb_shinfo(skb)->frags[i];
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pci_unmap_page(mdev->pdev,
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(dma_addr_t) be64_to_cpu(data->addr),
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frag->size, PCI_DMA_TODEVICE);
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}
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/* Stamp the freed descriptor */
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for (i = 0; i < tx_info->nr_txbb * TXBB_SIZE; i += STAMP_STRIDE) {
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*ptr = stamp;
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ptr += STAMP_DWORDS;
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if ((void *) ptr >= end) {
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ptr = ring->buf;
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stamp ^= cpu_to_be32(0x80000000);
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}
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}
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}
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dev_kfree_skb_any(skb);
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return tx_info->nr_txbb;
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}
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int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring)
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{
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struct mlx4_en_priv *priv = netdev_priv(dev);
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int cnt = 0;
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/* Skip last polled descriptor */
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ring->cons += ring->last_nr_txbb;
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mlx4_dbg(DRV, priv, "Freeing Tx buf - cons:0x%x prod:0x%x\n",
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ring->cons, ring->prod);
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if ((u32) (ring->prod - ring->cons) > ring->size) {
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if (netif_msg_tx_err(priv))
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mlx4_warn(priv->mdev, "Tx consumer passed producer!\n");
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return 0;
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}
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while (ring->cons != ring->prod) {
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ring->last_nr_txbb = mlx4_en_free_tx_desc(priv, ring,
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ring->cons & ring->size_mask,
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!!(ring->cons & ring->size));
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ring->cons += ring->last_nr_txbb;
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cnt++;
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}
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if (cnt)
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mlx4_dbg(DRV, priv, "Freed %d uncompleted tx descriptors\n", cnt);
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return cnt;
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}
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void mlx4_en_set_prio_map(struct mlx4_en_priv *priv, u16 *prio_map, u32 ring_num)
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{
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int block = 8 / ring_num;
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int extra = 8 - (block * ring_num);
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int num = 0;
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u16 ring = 1;
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int prio;
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if (ring_num == 1) {
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for (prio = 0; prio < 8; prio++)
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prio_map[prio] = 0;
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return;
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}
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for (prio = 0; prio < 8; prio++) {
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if (extra && (num == block + 1)) {
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ring++;
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num = 0;
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extra--;
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} else if (!extra && (num == block)) {
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ring++;
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num = 0;
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}
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prio_map[prio] = ring;
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mlx4_dbg(DRV, priv, " prio:%d --> ring:%d\n", prio, ring);
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num++;
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}
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}
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static void mlx4_en_process_tx_cq(struct net_device *dev, struct mlx4_en_cq *cq)
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{
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struct mlx4_en_priv *priv = netdev_priv(dev);
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struct mlx4_cq *mcq = &cq->mcq;
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struct mlx4_en_tx_ring *ring = &priv->tx_ring[cq->ring];
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struct mlx4_cqe *cqe = cq->buf;
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u16 index;
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u16 new_index;
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u32 txbbs_skipped = 0;
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u32 cq_last_sav;
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/* index always points to the first TXBB of the last polled descriptor */
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index = ring->cons & ring->size_mask;
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new_index = be16_to_cpu(cqe->wqe_index) & ring->size_mask;
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if (index == new_index)
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return;
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if (!priv->port_up)
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return;
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/*
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* We use a two-stage loop:
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* - the first samples the HW-updated CQE
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* - the second frees TXBBs until the last sample
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* This lets us amortize CQE cache misses, while still polling the CQ
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* until is quiescent.
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*/
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cq_last_sav = mcq->cons_index;
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do {
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do {
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/* Skip over last polled CQE */
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index = (index + ring->last_nr_txbb) & ring->size_mask;
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txbbs_skipped += ring->last_nr_txbb;
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/* Poll next CQE */
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ring->last_nr_txbb = mlx4_en_free_tx_desc(
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priv, ring, index,
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!!((ring->cons + txbbs_skipped) &
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ring->size));
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++mcq->cons_index;
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} while (index != new_index);
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new_index = be16_to_cpu(cqe->wqe_index) & ring->size_mask;
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} while (index != new_index);
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AVG_PERF_COUNTER(priv->pstats.tx_coal_avg,
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(u32) (mcq->cons_index - cq_last_sav));
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/*
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* To prevent CQ overflow we first update CQ consumer and only then
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* the ring consumer.
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*/
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mlx4_cq_set_ci(mcq);
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wmb();
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ring->cons += txbbs_skipped;
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/* Wakeup Tx queue if this ring stopped it */
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if (unlikely(ring->blocked)) {
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if (((u32) (ring->prod - ring->cons) <=
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ring->size - HEADROOM - MAX_DESC_TXBBS) && !cq->armed) {
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/* TODO: support multiqueue netdevs. Currently, we block
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* when *any* ring is full. Note that:
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* - 2 Tx rings can unblock at the same time and call
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* netif_wake_queue(), which is OK since this
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* operation is idempotent.
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* - We might wake the queue just after another ring
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* stopped it. This is no big deal because the next
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* transmission on that ring would stop the queue.
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*/
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ring->blocked = 0;
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netif_wake_queue(dev);
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priv->port_stats.wake_queue++;
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}
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}
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}
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void mlx4_en_tx_irq(struct mlx4_cq *mcq)
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{
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struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq);
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struct mlx4_en_priv *priv = netdev_priv(cq->dev);
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struct mlx4_en_tx_ring *ring = &priv->tx_ring[cq->ring];
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spin_lock_irq(&ring->comp_lock);
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cq->armed = 0;
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mlx4_en_process_tx_cq(cq->dev, cq);
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if (ring->blocked)
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mlx4_en_arm_cq(priv, cq);
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else
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mod_timer(&cq->timer, jiffies + 1);
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spin_unlock_irq(&ring->comp_lock);
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}
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void mlx4_en_poll_tx_cq(unsigned long data)
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{
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struct mlx4_en_cq *cq = (struct mlx4_en_cq *) data;
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struct mlx4_en_priv *priv = netdev_priv(cq->dev);
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struct mlx4_en_tx_ring *ring = &priv->tx_ring[cq->ring];
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u32 inflight;
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INC_PERF_COUNTER(priv->pstats.tx_poll);
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netif_tx_lock(priv->dev);
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spin_lock_irq(&ring->comp_lock);
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mlx4_en_process_tx_cq(cq->dev, cq);
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inflight = (u32) (ring->prod - ring->cons - ring->last_nr_txbb);
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/* If there are still packets in flight and the timer has not already
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* been scheduled by the Tx routine then schedule it here to guarantee
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* completion processing of these packets */
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if (inflight && priv->port_up)
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mod_timer(&cq->timer, jiffies + MLX4_EN_TX_POLL_TIMEOUT);
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spin_unlock_irq(&ring->comp_lock);
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netif_tx_unlock(priv->dev);
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}
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static struct mlx4_en_tx_desc *mlx4_en_bounce_to_desc(struct mlx4_en_priv *priv,
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struct mlx4_en_tx_ring *ring,
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u32 index,
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unsigned int desc_size)
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{
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u32 copy = (ring->size - index) * TXBB_SIZE;
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int i;
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for (i = desc_size - copy - 4; i >= 0; i -= 4) {
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if ((i & (TXBB_SIZE - 1)) == 0)
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wmb();
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*((u32 *) (ring->buf + i)) =
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*((u32 *) (ring->bounce_buf + copy + i));
|
|
}
|
|
|
|
for (i = copy - 4; i >= 4 ; i -= 4) {
|
|
if ((i & (TXBB_SIZE - 1)) == 0)
|
|
wmb();
|
|
|
|
*((u32 *) (ring->buf + index * TXBB_SIZE + i)) =
|
|
*((u32 *) (ring->bounce_buf + i));
|
|
}
|
|
|
|
/* Return real descriptor location */
|
|
return ring->buf + index * TXBB_SIZE;
|
|
}
|
|
|
|
static inline void mlx4_en_xmit_poll(struct mlx4_en_priv *priv, int tx_ind)
|
|
{
|
|
struct mlx4_en_cq *cq = &priv->tx_cq[tx_ind];
|
|
struct mlx4_en_tx_ring *ring = &priv->tx_ring[tx_ind];
|
|
|
|
/* If we don't have a pending timer, set one up to catch our recent
|
|
post in case the interface becomes idle */
|
|
if (!timer_pending(&cq->timer))
|
|
mod_timer(&cq->timer, jiffies + MLX4_EN_TX_POLL_TIMEOUT);
|
|
|
|
/* Poll the CQ every mlx4_en_TX_MODER_POLL packets */
|
|
if ((++ring->poll_cnt & (MLX4_EN_TX_POLL_MODER - 1)) == 0)
|
|
mlx4_en_process_tx_cq(priv->dev, cq);
|
|
}
|
|
|
|
static void *get_frag_ptr(struct sk_buff *skb)
|
|
{
|
|
struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
|
|
struct page *page = frag->page;
|
|
void *ptr;
|
|
|
|
ptr = page_address(page);
|
|
if (unlikely(!ptr))
|
|
return NULL;
|
|
|
|
return ptr + frag->page_offset;
|
|
}
|
|
|
|
static int is_inline(struct sk_buff *skb, void **pfrag)
|
|
{
|
|
void *ptr;
|
|
|
|
if (inline_thold && !skb_is_gso(skb) && skb->len <= inline_thold) {
|
|
if (skb_shinfo(skb)->nr_frags == 1) {
|
|
ptr = get_frag_ptr(skb);
|
|
if (unlikely(!ptr))
|
|
return 0;
|
|
|
|
if (pfrag)
|
|
*pfrag = ptr;
|
|
|
|
return 1;
|
|
} else if (unlikely(skb_shinfo(skb)->nr_frags))
|
|
return 0;
|
|
else
|
|
return 1;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int inline_size(struct sk_buff *skb)
|
|
{
|
|
if (skb->len + CTRL_SIZE + sizeof(struct mlx4_wqe_inline_seg)
|
|
<= MLX4_INLINE_ALIGN)
|
|
return ALIGN(skb->len + CTRL_SIZE +
|
|
sizeof(struct mlx4_wqe_inline_seg), 16);
|
|
else
|
|
return ALIGN(skb->len + CTRL_SIZE + 2 *
|
|
sizeof(struct mlx4_wqe_inline_seg), 16);
|
|
}
|
|
|
|
static int get_real_size(struct sk_buff *skb, struct net_device *dev,
|
|
int *lso_header_size)
|
|
{
|
|
struct mlx4_en_priv *priv = netdev_priv(dev);
|
|
struct mlx4_en_dev *mdev = priv->mdev;
|
|
int real_size;
|
|
|
|
if (skb_is_gso(skb)) {
|
|
*lso_header_size = skb_transport_offset(skb) + tcp_hdrlen(skb);
|
|
real_size = CTRL_SIZE + skb_shinfo(skb)->nr_frags * DS_SIZE +
|
|
ALIGN(*lso_header_size + 4, DS_SIZE);
|
|
if (unlikely(*lso_header_size != skb_headlen(skb))) {
|
|
/* We add a segment for the skb linear buffer only if
|
|
* it contains data */
|
|
if (*lso_header_size < skb_headlen(skb))
|
|
real_size += DS_SIZE;
|
|
else {
|
|
if (netif_msg_tx_err(priv))
|
|
mlx4_warn(mdev, "Non-linear headers\n");
|
|
dev_kfree_skb_any(skb);
|
|
return 0;
|
|
}
|
|
}
|
|
if (unlikely(*lso_header_size > MAX_LSO_HDR_SIZE)) {
|
|
if (netif_msg_tx_err(priv))
|
|
mlx4_warn(mdev, "LSO header size too big\n");
|
|
dev_kfree_skb_any(skb);
|
|
return 0;
|
|
}
|
|
} else {
|
|
*lso_header_size = 0;
|
|
if (!is_inline(skb, NULL))
|
|
real_size = CTRL_SIZE + (skb_shinfo(skb)->nr_frags + 1) * DS_SIZE;
|
|
else
|
|
real_size = inline_size(skb);
|
|
}
|
|
|
|
return real_size;
|
|
}
|
|
|
|
static void build_inline_wqe(struct mlx4_en_tx_desc *tx_desc, struct sk_buff *skb,
|
|
int real_size, u16 *vlan_tag, int tx_ind, void *fragptr)
|
|
{
|
|
struct mlx4_wqe_inline_seg *inl = &tx_desc->inl;
|
|
int spc = MLX4_INLINE_ALIGN - CTRL_SIZE - sizeof *inl;
|
|
|
|
if (skb->len <= spc) {
|
|
inl->byte_count = cpu_to_be32(1 << 31 | skb->len);
|
|
skb_copy_from_linear_data(skb, inl + 1, skb_headlen(skb));
|
|
if (skb_shinfo(skb)->nr_frags)
|
|
memcpy(((void *)(inl + 1)) + skb_headlen(skb), fragptr,
|
|
skb_shinfo(skb)->frags[0].size);
|
|
|
|
} else {
|
|
inl->byte_count = cpu_to_be32(1 << 31 | spc);
|
|
if (skb_headlen(skb) <= spc) {
|
|
skb_copy_from_linear_data(skb, inl + 1, skb_headlen(skb));
|
|
if (skb_headlen(skb) < spc) {
|
|
memcpy(((void *)(inl + 1)) + skb_headlen(skb),
|
|
fragptr, spc - skb_headlen(skb));
|
|
fragptr += spc - skb_headlen(skb);
|
|
}
|
|
inl = (void *) (inl + 1) + spc;
|
|
memcpy(((void *)(inl + 1)), fragptr, skb->len - spc);
|
|
} else {
|
|
skb_copy_from_linear_data(skb, inl + 1, spc);
|
|
inl = (void *) (inl + 1) + spc;
|
|
skb_copy_from_linear_data_offset(skb, spc, inl + 1,
|
|
skb_headlen(skb) - spc);
|
|
if (skb_shinfo(skb)->nr_frags)
|
|
memcpy(((void *)(inl + 1)) + skb_headlen(skb) - spc,
|
|
fragptr, skb_shinfo(skb)->frags[0].size);
|
|
}
|
|
|
|
wmb();
|
|
inl->byte_count = cpu_to_be32(1 << 31 | (skb->len - spc));
|
|
}
|
|
tx_desc->ctrl.vlan_tag = cpu_to_be16(*vlan_tag);
|
|
tx_desc->ctrl.ins_vlan = MLX4_WQE_CTRL_INS_VLAN * !!(*vlan_tag);
|
|
tx_desc->ctrl.fence_size = (real_size / 16) & 0x3f;
|
|
}
|
|
|
|
static int get_vlan_info(struct mlx4_en_priv *priv, struct sk_buff *skb,
|
|
u16 *vlan_tag)
|
|
{
|
|
int tx_ind;
|
|
|
|
/* Obtain VLAN information if present */
|
|
if (priv->vlgrp && vlan_tx_tag_present(skb)) {
|
|
*vlan_tag = vlan_tx_tag_get(skb);
|
|
/* Set the Tx ring to use according to vlan priority */
|
|
tx_ind = priv->tx_prio_map[*vlan_tag >> 13];
|
|
} else {
|
|
*vlan_tag = 0;
|
|
tx_ind = 0;
|
|
}
|
|
return tx_ind;
|
|
}
|
|
|
|
int mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev)
|
|
{
|
|
struct mlx4_en_priv *priv = netdev_priv(dev);
|
|
struct mlx4_en_dev *mdev = priv->mdev;
|
|
struct mlx4_en_tx_ring *ring;
|
|
struct mlx4_en_cq *cq;
|
|
struct mlx4_en_tx_desc *tx_desc;
|
|
struct mlx4_wqe_data_seg *data;
|
|
struct skb_frag_struct *frag;
|
|
struct mlx4_en_tx_info *tx_info;
|
|
int tx_ind = 0;
|
|
int nr_txbb;
|
|
int desc_size;
|
|
int real_size;
|
|
dma_addr_t dma;
|
|
u32 index;
|
|
__be32 op_own;
|
|
u16 vlan_tag;
|
|
int i;
|
|
int lso_header_size;
|
|
void *fragptr;
|
|
|
|
if (unlikely(!skb->len)) {
|
|
dev_kfree_skb_any(skb);
|
|
return NETDEV_TX_OK;
|
|
}
|
|
real_size = get_real_size(skb, dev, &lso_header_size);
|
|
if (unlikely(!real_size))
|
|
return NETDEV_TX_OK;
|
|
|
|
/* Allign descriptor to TXBB size */
|
|
desc_size = ALIGN(real_size, TXBB_SIZE);
|
|
nr_txbb = desc_size / TXBB_SIZE;
|
|
if (unlikely(nr_txbb > MAX_DESC_TXBBS)) {
|
|
if (netif_msg_tx_err(priv))
|
|
mlx4_warn(mdev, "Oversized header or SG list\n");
|
|
dev_kfree_skb_any(skb);
|
|
return NETDEV_TX_OK;
|
|
}
|
|
|
|
tx_ind = get_vlan_info(priv, skb, &vlan_tag);
|
|
ring = &priv->tx_ring[tx_ind];
|
|
|
|
/* Check available TXBBs And 2K spare for prefetch */
|
|
if (unlikely(((int)(ring->prod - ring->cons)) >
|
|
ring->size - HEADROOM - MAX_DESC_TXBBS)) {
|
|
/* every full Tx ring stops queue.
|
|
* TODO: implement multi-queue support (per-queue stop) */
|
|
netif_stop_queue(dev);
|
|
ring->blocked = 1;
|
|
priv->port_stats.queue_stopped++;
|
|
|
|
/* Use interrupts to find out when queue opened */
|
|
cq = &priv->tx_cq[tx_ind];
|
|
mlx4_en_arm_cq(priv, cq);
|
|
return NETDEV_TX_BUSY;
|
|
}
|
|
|
|
/* Now that we know what Tx ring to use */
|
|
if (unlikely(!priv->port_up)) {
|
|
if (netif_msg_tx_err(priv))
|
|
mlx4_warn(mdev, "xmit: port down!\n");
|
|
dev_kfree_skb_any(skb);
|
|
return NETDEV_TX_OK;
|
|
}
|
|
|
|
/* Track current inflight packets for performance analysis */
|
|
AVG_PERF_COUNTER(priv->pstats.inflight_avg,
|
|
(u32) (ring->prod - ring->cons - 1));
|
|
|
|
/* Packet is good - grab an index and transmit it */
|
|
index = ring->prod & ring->size_mask;
|
|
|
|
/* See if we have enough space for whole descriptor TXBB for setting
|
|
* SW ownership on next descriptor; if not, use a bounce buffer. */
|
|
if (likely(index + nr_txbb <= ring->size))
|
|
tx_desc = ring->buf + index * TXBB_SIZE;
|
|
else
|
|
tx_desc = (struct mlx4_en_tx_desc *) ring->bounce_buf;
|
|
|
|
/* Save skb in tx_info ring */
|
|
tx_info = &ring->tx_info[index];
|
|
tx_info->skb = skb;
|
|
tx_info->nr_txbb = nr_txbb;
|
|
|
|
/* Prepare ctrl segement apart opcode+ownership, which depends on
|
|
* whether LSO is used */
|
|
tx_desc->ctrl.vlan_tag = cpu_to_be16(vlan_tag);
|
|
tx_desc->ctrl.ins_vlan = MLX4_WQE_CTRL_INS_VLAN * !!vlan_tag;
|
|
tx_desc->ctrl.fence_size = (real_size / 16) & 0x3f;
|
|
tx_desc->ctrl.srcrb_flags = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE |
|
|
MLX4_WQE_CTRL_SOLICITED);
|
|
if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
|
|
tx_desc->ctrl.srcrb_flags |= cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM |
|
|
MLX4_WQE_CTRL_TCP_UDP_CSUM);
|
|
priv->port_stats.tx_chksum_offload++;
|
|
}
|
|
|
|
/* Handle LSO (TSO) packets */
|
|
if (lso_header_size) {
|
|
/* Mark opcode as LSO */
|
|
op_own = cpu_to_be32(MLX4_OPCODE_LSO | (1 << 6)) |
|
|
((ring->prod & ring->size) ?
|
|
cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0);
|
|
|
|
/* Fill in the LSO prefix */
|
|
tx_desc->lso.mss_hdr_size = cpu_to_be32(
|
|
skb_shinfo(skb)->gso_size << 16 | lso_header_size);
|
|
|
|
/* Copy headers;
|
|
* note that we already verified that it is linear */
|
|
memcpy(tx_desc->lso.header, skb->data, lso_header_size);
|
|
data = ((void *) &tx_desc->lso +
|
|
ALIGN(lso_header_size + 4, DS_SIZE));
|
|
|
|
priv->port_stats.tso_packets++;
|
|
i = ((skb->len - lso_header_size) / skb_shinfo(skb)->gso_size) +
|
|
!!((skb->len - lso_header_size) % skb_shinfo(skb)->gso_size);
|
|
ring->bytes += skb->len + (i - 1) * lso_header_size;
|
|
ring->packets += i;
|
|
} else {
|
|
/* Normal (Non LSO) packet */
|
|
op_own = cpu_to_be32(MLX4_OPCODE_SEND) |
|
|
((ring->prod & ring->size) ?
|
|
cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0);
|
|
data = &tx_desc->data;
|
|
ring->bytes += max(skb->len, (unsigned int) ETH_ZLEN);
|
|
ring->packets++;
|
|
|
|
}
|
|
AVG_PERF_COUNTER(priv->pstats.tx_pktsz_avg, skb->len);
|
|
|
|
|
|
/* valid only for none inline segments */
|
|
tx_info->data_offset = (void *) data - (void *) tx_desc;
|
|
|
|
tx_info->linear = (lso_header_size < skb_headlen(skb) && !is_inline(skb, NULL)) ? 1 : 0;
|
|
data += skb_shinfo(skb)->nr_frags + tx_info->linear - 1;
|
|
|
|
if (!is_inline(skb, &fragptr)) {
|
|
/* Map fragments */
|
|
for (i = skb_shinfo(skb)->nr_frags - 1; i >= 0; i--) {
|
|
frag = &skb_shinfo(skb)->frags[i];
|
|
dma = pci_map_page(mdev->dev->pdev, frag->page, frag->page_offset,
|
|
frag->size, PCI_DMA_TODEVICE);
|
|
data->addr = cpu_to_be64(dma);
|
|
data->lkey = cpu_to_be32(mdev->mr.key);
|
|
wmb();
|
|
data->byte_count = cpu_to_be32(frag->size);
|
|
--data;
|
|
}
|
|
|
|
/* Map linear part */
|
|
if (tx_info->linear) {
|
|
dma = pci_map_single(mdev->dev->pdev, skb->data + lso_header_size,
|
|
skb_headlen(skb) - lso_header_size, PCI_DMA_TODEVICE);
|
|
data->addr = cpu_to_be64(dma);
|
|
data->lkey = cpu_to_be32(mdev->mr.key);
|
|
wmb();
|
|
data->byte_count = cpu_to_be32(skb_headlen(skb) - lso_header_size);
|
|
}
|
|
} else
|
|
build_inline_wqe(tx_desc, skb, real_size, &vlan_tag, tx_ind, fragptr);
|
|
|
|
ring->prod += nr_txbb;
|
|
|
|
/* If we used a bounce buffer then copy descriptor back into place */
|
|
if (tx_desc == (struct mlx4_en_tx_desc *) ring->bounce_buf)
|
|
tx_desc = mlx4_en_bounce_to_desc(priv, ring, index, desc_size);
|
|
|
|
/* Run destructor before passing skb to HW */
|
|
if (likely(!skb_shared(skb)))
|
|
skb_orphan(skb);
|
|
|
|
/* Ensure new descirptor hits memory
|
|
* before setting ownership of this descriptor to HW */
|
|
wmb();
|
|
tx_desc->ctrl.owner_opcode = op_own;
|
|
|
|
/* Ring doorbell! */
|
|
wmb();
|
|
writel(ring->doorbell_qpn, mdev->uar_map + MLX4_SEND_DOORBELL);
|
|
dev->trans_start = jiffies;
|
|
|
|
/* Poll CQ here */
|
|
mlx4_en_xmit_poll(priv, tx_ind);
|
|
|
|
return 0;
|
|
}
|
|
|