558 lines
15 KiB
C
558 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright 2011-2013 Freescale Semiconductor, Inc.
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* Copyright 2011 Linaro Ltd.
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*/
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/irqchip.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/irqchip/arm-gic.h>
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#include "common.h"
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#include "hardware.h"
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#define GPC_CNTR 0x000
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#define GPC_CNTR_L2_PGE 22
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#define GPC_IMR1 0x008
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#define GPC_PGC_MF_PDN 0x220
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#define GPC_PGC_CPU_PDN 0x2a0
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#define GPC_PGC_CPU_PUPSCR 0x2a4
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#define GPC_PGC_CPU_PDNSCR 0x2a8
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#define GPC_PGC_SW2ISO_SHIFT 0x8
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#define GPC_PGC_SW_SHIFT 0x0
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#define GPC_M4_LPSR 0x2c
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#define GPC_M4_LPSR_M4_SLEEPING_SHIFT 4
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#define GPC_M4_LPSR_M4_SLEEPING_MASK 0x1
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#define GPC_M4_LPSR_M4_SLEEP_HOLD_REQ_MASK 0x1
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#define GPC_M4_LPSR_M4_SLEEP_HOLD_REQ_SHIFT 0
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#define GPC_M4_LPSR_M4_SLEEP_HOLD_ACK_MASK 0x1
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#define GPC_M4_LPSR_M4_SLEEP_HOLD_ACK_SHIFT 1
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#define GPC_PGC_CPU_SW_SHIFT 0
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#define GPC_PGC_CPU_SW_MASK 0x3f
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#define GPC_PGC_CPU_SW2ISO_SHIFT 8
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#define GPC_PGC_CPU_SW2ISO_MASK 0x3f
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#define IMR_NUM 4
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#define GPC_MAX_IRQS (IMR_NUM * 32)
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/* for irq #74 and #75 */
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#define GPC_USB_VBUS_WAKEUP_IRQ_MASK 0xc00
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/* for irq #150 and #151 */
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#define GPC_ENET_WAKEUP_IRQ_MASK 0xC00000
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static void __iomem *gpc_base;
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static u32 gpc_wake_irqs[IMR_NUM];
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static u32 gpc_saved_imrs[IMR_NUM];
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static u32 gpc_mf_irqs[IMR_NUM];
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static u32 gpc_mf_request_on[IMR_NUM];
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static DEFINE_SPINLOCK(gpc_lock);
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void imx_gpc_add_m4_wake_up_irq(u32 hwirq, bool enable)
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{
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unsigned int idx = hwirq / 32;
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unsigned long flags;
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u32 mask;
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/* Sanity check for SPI irq */
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if (hwirq < 32)
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return;
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mask = 1 << hwirq % 32;
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spin_lock_irqsave(&gpc_lock, flags);
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gpc_wake_irqs[idx] = enable ? gpc_wake_irqs[idx] | mask :
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gpc_wake_irqs[idx] & ~mask;
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spin_unlock_irqrestore(&gpc_lock, flags);
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}
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void imx_gpc_hold_m4_in_sleep(void)
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{
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int val;
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unsigned long timeout = jiffies + msecs_to_jiffies(500);
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printk("%s - %d\n", __func__, __LINE__);
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/* wait M4 in wfi before asserting hold request */
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while (!imx_gpc_is_m4_sleeping())
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if (time_after(jiffies, timeout))
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pr_err("M4 is NOT in expected sleep!\n");
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val = readl_relaxed(gpc_base + GPC_M4_LPSR);
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val &= ~(GPC_M4_LPSR_M4_SLEEP_HOLD_REQ_MASK <<
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GPC_M4_LPSR_M4_SLEEP_HOLD_REQ_SHIFT);
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writel_relaxed(val, gpc_base + GPC_M4_LPSR);
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timeout = jiffies + msecs_to_jiffies(500);
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while (readl_relaxed(gpc_base + GPC_M4_LPSR)
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& (GPC_M4_LPSR_M4_SLEEP_HOLD_ACK_MASK <<
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GPC_M4_LPSR_M4_SLEEP_HOLD_ACK_SHIFT))
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if (time_after(jiffies, timeout))
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pr_err("Wait M4 hold ack timeout!\n");
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}
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void imx_gpc_release_m4_in_sleep(void)
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{
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int val;
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val = readl_relaxed(gpc_base + GPC_M4_LPSR);
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val |= GPC_M4_LPSR_M4_SLEEP_HOLD_REQ_MASK <<
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GPC_M4_LPSR_M4_SLEEP_HOLD_REQ_SHIFT;
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writel_relaxed(val, gpc_base + GPC_M4_LPSR);
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}
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unsigned int imx_gpc_is_m4_sleeping(void)
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{
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if (readl_relaxed(gpc_base + GPC_M4_LPSR) &
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(GPC_M4_LPSR_M4_SLEEPING_MASK <<
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GPC_M4_LPSR_M4_SLEEPING_SHIFT))
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return 1;
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return 0;
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}
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bool imx_gpc_usb_wakeup_enabled(void)
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{
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if (!(cpu_is_imx6sx() || cpu_is_imx6ul() || cpu_is_imx6ull() ||
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cpu_is_imx6ulz() || cpu_is_imx6sll()))
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return false;
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/*
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* for SoC later than i.MX6SX, USB vbus wakeup
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* only needs weak 2P5 on, stop_mode_config is
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* NOT needed, so we check if is USB vbus wakeup
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* is enabled(assume irq #74 and #75) to decide
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* if to keep weak 2P5 on.
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*/
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if (gpc_wake_irqs[1] & GPC_USB_VBUS_WAKEUP_IRQ_MASK)
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return true;
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return false;
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}
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bool imx_gpc_enet_wakeup_enabled(void)
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{
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if (!cpu_is_imx6q())
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return false;
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if (gpc_wake_irqs[3] & GPC_ENET_WAKEUP_IRQ_MASK)
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return true;
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return false;
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}
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unsigned int imx_gpc_is_mf_mix_off(void)
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{
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return readl_relaxed(gpc_base + GPC_PGC_MF_PDN);
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}
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static void imx_gpc_mf_mix_off(void)
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{
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int i;
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for (i = 0; i < IMR_NUM; i++)
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if (((gpc_wake_irqs[i] | gpc_mf_request_on[i]) &
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gpc_mf_irqs[i]) != 0)
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return;
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pr_info("Turn off M/F mix!\n");
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/* turn off mega/fast mix */
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writel_relaxed(0x1, gpc_base + GPC_PGC_MF_PDN);
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}
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void imx_gpc_set_arm_power_up_timing(u32 sw2iso, u32 sw)
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{
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writel_relaxed((sw2iso << GPC_PGC_SW2ISO_SHIFT) |
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(sw << GPC_PGC_SW_SHIFT), gpc_base + GPC_PGC_CPU_PUPSCR);
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}
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void imx_gpc_set_arm_power_down_timing(u32 sw2iso, u32 sw)
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{
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writel_relaxed((sw2iso << GPC_PGC_SW2ISO_SHIFT) |
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(sw << GPC_PGC_SW_SHIFT), gpc_base + GPC_PGC_CPU_PDNSCR);
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}
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void imx_gpc_set_arm_power_in_lpm(bool power_off)
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{
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writel_relaxed(power_off, gpc_base + GPC_PGC_CPU_PDN);
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}
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void imx_gpc_set_l2_mem_power_in_lpm(bool power_off)
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{
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u32 val;
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val = readl_relaxed(gpc_base + GPC_CNTR);
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val &= ~(1 << GPC_CNTR_L2_PGE);
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if (power_off)
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val |= 1 << GPC_CNTR_L2_PGE;
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writel_relaxed(val, gpc_base + GPC_CNTR);
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}
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void imx_gpc_pre_suspend(bool arm_power_off)
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{
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void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
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int i;
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/* power down the mega-fast power domain */
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if ((cpu_is_imx6sx() || cpu_is_imx6ul() || cpu_is_imx6ull() ||
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cpu_is_imx6ulz() || cpu_is_imx6sll()) && arm_power_off)
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imx_gpc_mf_mix_off();
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/* Tell GPC to power off ARM core when suspend */
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if (arm_power_off)
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imx_gpc_set_arm_power_in_lpm(arm_power_off);
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for (i = 0; i < IMR_NUM; i++) {
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gpc_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4);
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writel_relaxed(~gpc_wake_irqs[i], reg_imr1 + i * 4);
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}
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}
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void imx_gpc_post_resume(void)
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{
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void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
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int i;
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/* Keep ARM core powered on for other low-power modes */
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imx_gpc_set_arm_power_in_lpm(false);
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/* Keep M/F mix powered on for other low-power modes */
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if (cpu_is_imx6sx() || cpu_is_imx6ul() || cpu_is_imx6ull() ||
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cpu_is_imx6ulz() || cpu_is_imx6sll())
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writel_relaxed(0x0, gpc_base + GPC_PGC_MF_PDN);
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for (i = 0; i < IMR_NUM; i++)
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writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4);
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}
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static int imx_gpc_irq_set_wake(struct irq_data *d, unsigned int on)
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{
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unsigned int idx = d->hwirq / 32;
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unsigned long flags;
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u32 mask;
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printk("%s - %d\n", __func__, __LINE__);
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mask = 1 << d->hwirq % 32;
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spin_lock_irqsave(&gpc_lock, flags);
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gpc_wake_irqs[idx] = on ? gpc_wake_irqs[idx] | mask :
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gpc_wake_irqs[idx] & ~mask;
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spin_unlock_irqrestore(&gpc_lock, flags);
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/*
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* Do *not* call into the parent, as the GIC doesn't have any
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* wake-up facility...
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*/
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return 0;
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}
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void imx_gpc_mask_all(void)
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{
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void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
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int i;
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for (i = 0; i < IMR_NUM; i++) {
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gpc_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4);
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writel_relaxed(~0, reg_imr1 + i * 4);
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}
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}
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void imx_gpc_restore_all(void)
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{
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void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
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int i;
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for (i = 0; i < IMR_NUM; i++)
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writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4);
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}
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void imx_gpc_hwirq_unmask(unsigned int hwirq)
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{
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void __iomem *reg;
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u32 val;
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reg = gpc_base + GPC_IMR1 + hwirq / 32 * 4;
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val = readl_relaxed(reg);
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val &= ~(1 << hwirq % 32);
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writel_relaxed(val, reg);
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}
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void imx_gpc_hwirq_mask(unsigned int hwirq)
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{
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void __iomem *reg;
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u32 val;
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reg = gpc_base + GPC_IMR1 + hwirq / 32 * 4;
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val = readl_relaxed(reg);
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val |= 1 << (hwirq % 32);
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writel_relaxed(val, reg);
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}
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static void imx_gpc_irq_unmask(struct irq_data *d)
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{
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imx_gpc_hwirq_unmask(d->hwirq);
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irq_chip_unmask_parent(d);
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}
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static void imx_gpc_irq_mask(struct irq_data *d)
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{
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imx_gpc_hwirq_mask(d->hwirq);
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irq_chip_mask_parent(d);
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}
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static struct irq_chip imx_gpc_chip = {
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.name = "GPC",
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.irq_eoi = irq_chip_eoi_parent,
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.irq_mask = imx_gpc_irq_mask,
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.irq_unmask = imx_gpc_irq_unmask,
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.irq_retrigger = irq_chip_retrigger_hierarchy,
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.irq_set_wake = imx_gpc_irq_set_wake,
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.irq_set_type = irq_chip_set_type_parent,
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#ifdef CONFIG_SMP
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.irq_set_affinity = irq_chip_set_affinity_parent,
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#endif
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};
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static int imx_gpc_domain_translate(struct irq_domain *d,
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struct irq_fwspec *fwspec,
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unsigned long *hwirq,
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unsigned int *type)
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{
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if (is_of_node(fwspec->fwnode)) {
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if (fwspec->param_count != 3)
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return -EINVAL;
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/* No PPI should point to this domain */
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if (fwspec->param[0] != 0)
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return -EINVAL;
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*hwirq = fwspec->param[1];
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*type = fwspec->param[2];
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return 0;
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}
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return -EINVAL;
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}
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static int imx_gpc_domain_alloc(struct irq_domain *domain,
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unsigned int irq,
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unsigned int nr_irqs, void *data)
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{
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struct irq_fwspec *fwspec = data;
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struct irq_fwspec parent_fwspec;
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irq_hw_number_t hwirq;
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int i;
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if (fwspec->param_count != 3)
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return -EINVAL; /* Not GIC compliant */
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if (fwspec->param[0] != 0)
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return -EINVAL; /* No PPI should point to this domain */
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hwirq = fwspec->param[1];
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if (hwirq >= GPC_MAX_IRQS)
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return -EINVAL; /* Can't deal with this */
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for (i = 0; i < nr_irqs; i++)
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irq_domain_set_hwirq_and_chip(domain, irq + i, hwirq + i,
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&imx_gpc_chip, NULL);
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parent_fwspec = *fwspec;
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parent_fwspec.fwnode = domain->parent->fwnode;
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return irq_domain_alloc_irqs_parent(domain, irq, nr_irqs,
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&parent_fwspec);
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}
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static const struct irq_domain_ops imx_gpc_domain_ops = {
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.translate = imx_gpc_domain_translate,
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.alloc = imx_gpc_domain_alloc,
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.free = irq_domain_free_irqs_common,
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};
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int imx_gpc_mf_power_on(unsigned int irq, unsigned int on)
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{
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struct irq_desc *d = irq_to_desc(irq);
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unsigned int idx = d->irq_data.hwirq / 32;
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unsigned long flags;
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u32 mask;
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mask = 1 << (d->irq_data.hwirq % 32);
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spin_lock_irqsave(&gpc_lock, flags);
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gpc_mf_request_on[idx] = on ? gpc_mf_request_on[idx] | mask :
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gpc_mf_request_on[idx] & ~mask;
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spin_unlock_irqrestore(&gpc_lock, flags);
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return 0;
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}
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int imx_gpc_mf_request_on(unsigned int irq, unsigned int on)
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{
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if (cpu_is_imx6sx() || cpu_is_imx6ul() || cpu_is_imx6ull() ||
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cpu_is_imx6ulz() || cpu_is_imx6sll())
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return imx_gpc_mf_power_on(irq, on);
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else if (cpu_is_imx7d())
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return imx_gpcv2_mf_power_on(irq, on);
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else
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return 0;
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}
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EXPORT_SYMBOL_GPL(imx_gpc_mf_request_on);
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void imx_gpc_switch_pupscr_clk(bool flag)
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{
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static u32 pupscr_sw2iso, pupscr_sw;
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u32 ratio, pupscr = readl_relaxed(gpc_base + GPC_PGC_CPU_PUPSCR);
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if (flag) {
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/* save the init clock setting IPG/2048 for IPG@66Mhz */
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pupscr_sw2iso = (pupscr >> GPC_PGC_CPU_SW2ISO_SHIFT) &
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GPC_PGC_CPU_SW2ISO_MASK;
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pupscr_sw = (pupscr >> GPC_PGC_CPU_SW_SHIFT) &
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GPC_PGC_CPU_SW_MASK;
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/*
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* i.MX6UL TO1.0 ARM power up uses IPG/2048 as clock source,
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* from TO1.1, PGC_CPU_PUPSCR bit [5] is re-defined to switch
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* clock to IPG/32, enable this bit to speed up the ARM power
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* up process in low power idle case(IPG@1.5Mhz). So the sw and
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* sw2iso need to be adjusted as below:
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* sw_new(sw2iso_new) = (2048 * 1.5 / 66 * 32) * sw(sw2iso)
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*/
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ratio = 3072 / (66 * 32);
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pupscr &= ~(GPC_PGC_CPU_SW_MASK << GPC_PGC_CPU_SW_SHIFT |
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GPC_PGC_CPU_SW2ISO_MASK << GPC_PGC_CPU_SW2ISO_SHIFT);
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pupscr |= (ratio * pupscr_sw + 1) << GPC_PGC_CPU_SW_SHIFT |
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1 << 5 | (ratio * pupscr_sw2iso + 1) <<
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GPC_PGC_CPU_SW2ISO_SHIFT;
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writel_relaxed(pupscr, gpc_base + GPC_PGC_CPU_PUPSCR);
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} else {
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/* restore back after exit from low power idle */
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pupscr &= ~(GPC_PGC_CPU_SW_MASK << GPC_PGC_CPU_SW_SHIFT |
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GPC_PGC_CPU_SW2ISO_MASK << GPC_PGC_CPU_SW2ISO_SHIFT);
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pupscr |= pupscr_sw << GPC_PGC_CPU_SW_SHIFT |
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pupscr_sw2iso << GPC_PGC_CPU_SW2ISO_SHIFT;
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writel_relaxed(pupscr, gpc_base + GPC_PGC_CPU_PUPSCR);
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}
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}
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static int __init imx_gpc_init(struct device_node *node,
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struct device_node *parent)
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{
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struct irq_domain *parent_domain, *domain;
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int i;
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u32 val;
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u32 cpu_pupscr_sw2iso, cpu_pupscr_sw;
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u32 cpu_pdnscr_iso2sw, cpu_pdnscr_iso;
|
|
|
|
if (!parent) {
|
|
pr_err("%pOF: no parent, giving up\n", node);
|
|
return -ENODEV;
|
|
}
|
|
|
|
parent_domain = irq_find_host(parent);
|
|
if (!parent_domain) {
|
|
pr_err("%pOF: unable to obtain parent domain\n", node);
|
|
return -ENXIO;
|
|
}
|
|
|
|
gpc_base = of_iomap(node, 0);
|
|
if (WARN_ON(!gpc_base))
|
|
return -ENOMEM;
|
|
|
|
domain = irq_domain_add_hierarchy(parent_domain, 0, GPC_MAX_IRQS,
|
|
node, &imx_gpc_domain_ops,
|
|
NULL);
|
|
if (!domain) {
|
|
iounmap(gpc_base);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
/* Initially mask all interrupts */
|
|
for (i = 0; i < IMR_NUM; i++)
|
|
writel_relaxed(~0, gpc_base + GPC_IMR1 + i * 4);
|
|
|
|
/* Read supported wakeup source in M/F domain */
|
|
if (cpu_is_imx6sx() || cpu_is_imx6ul() || cpu_is_imx6ull() ||
|
|
cpu_is_imx6ulz() || cpu_is_imx6sll()) {
|
|
of_property_read_u32_index(node, "fsl,mf-mix-wakeup-irq", 0,
|
|
&gpc_mf_irqs[0]);
|
|
of_property_read_u32_index(node, "fsl,mf-mix-wakeup-irq", 1,
|
|
&gpc_mf_irqs[1]);
|
|
of_property_read_u32_index(node, "fsl,mf-mix-wakeup-irq", 2,
|
|
&gpc_mf_irqs[2]);
|
|
of_property_read_u32_index(node, "fsl,mf-mix-wakeup-irq", 3,
|
|
&gpc_mf_irqs[3]);
|
|
if (!(gpc_mf_irqs[0] | gpc_mf_irqs[1] |
|
|
gpc_mf_irqs[2] | gpc_mf_irqs[3]))
|
|
pr_info("No wakeup source in Mega/Fast domain found!\n");
|
|
}
|
|
|
|
/* clear the L2_PGE bit on i.MX6SLL */
|
|
if (cpu_is_imx6sll()) {
|
|
val = readl_relaxed(gpc_base + GPC_CNTR);
|
|
val &= ~(1 << GPC_CNTR_L2_PGE);
|
|
writel_relaxed(val, gpc_base + GPC_CNTR);
|
|
}
|
|
|
|
/*
|
|
* Clear the OF_POPULATED flag set in of_irq_init so that
|
|
* later the GPC power domain driver will not be skipped.
|
|
*/
|
|
of_node_clear_flag(node, OF_POPULATED);
|
|
|
|
/*
|
|
* If there are CPU isolation timing settings in dts,
|
|
* update them according to dts, otherwise, keep them
|
|
* with default value in registers.
|
|
*/
|
|
cpu_pupscr_sw2iso = cpu_pupscr_sw =
|
|
cpu_pdnscr_iso2sw = cpu_pdnscr_iso = 0;
|
|
|
|
/* Read CPU isolation setting for GPC */
|
|
of_property_read_u32(node, "fsl,cpu_pupscr_sw2iso", &cpu_pupscr_sw2iso);
|
|
of_property_read_u32(node, "fsl,cpu_pupscr_sw", &cpu_pupscr_sw);
|
|
of_property_read_u32(node, "fsl,cpu_pdnscr_iso2sw", &cpu_pdnscr_iso2sw);
|
|
of_property_read_u32(node, "fsl,cpu_pdnscr_iso", &cpu_pdnscr_iso);
|
|
|
|
/* Return if no property found in dtb */
|
|
if ((cpu_pupscr_sw2iso | cpu_pupscr_sw
|
|
| cpu_pdnscr_iso2sw | cpu_pdnscr_iso) == 0)
|
|
return 0;
|
|
|
|
/* Update CPU PUPSCR timing if it is defined in dts */
|
|
val = readl_relaxed(gpc_base + GPC_PGC_CPU_PUPSCR);
|
|
val &= ~(GPC_PGC_CPU_SW2ISO_MASK << GPC_PGC_CPU_SW2ISO_SHIFT);
|
|
val &= ~(GPC_PGC_CPU_SW_MASK << GPC_PGC_CPU_SW_SHIFT);
|
|
val |= cpu_pupscr_sw2iso << GPC_PGC_CPU_SW2ISO_SHIFT;
|
|
val |= cpu_pupscr_sw << GPC_PGC_CPU_SW_SHIFT;
|
|
writel_relaxed(val, gpc_base + GPC_PGC_CPU_PUPSCR);
|
|
|
|
/* Update CPU PDNSCR timing if it is defined in dts */
|
|
val = readl_relaxed(gpc_base + GPC_PGC_CPU_PDNSCR);
|
|
val &= ~(GPC_PGC_CPU_SW2ISO_MASK << GPC_PGC_CPU_SW2ISO_SHIFT);
|
|
val &= ~(GPC_PGC_CPU_SW_MASK << GPC_PGC_CPU_SW_SHIFT);
|
|
val |= cpu_pdnscr_iso2sw << GPC_PGC_CPU_SW2ISO_SHIFT;
|
|
val |= cpu_pdnscr_iso << GPC_PGC_CPU_SW_SHIFT;
|
|
writel_relaxed(val, gpc_base + GPC_PGC_CPU_PDNSCR);
|
|
|
|
return 0;
|
|
}
|
|
IRQCHIP_DECLARE(imx_gpc, "fsl,imx6q-gpc", imx_gpc_init);
|
|
|
|
void __init imx_gpc_check_dt(void)
|
|
{
|
|
struct device_node *np;
|
|
|
|
np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpc");
|
|
if (WARN_ON(!np))
|
|
return;
|
|
|
|
if (WARN_ON(!of_find_property(np, "interrupt-controller", NULL))) {
|
|
pr_warn("Outdated DT detected, suspend/resume will NOT work\n");
|
|
|
|
/* map GPC, so that at least CPUidle and WARs keep working */
|
|
gpc_base = of_iomap(np, 0);
|
|
}
|
|
}
|