852 lines
23 KiB
C
852 lines
23 KiB
C
/*
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* Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/irqchip/arm-gic.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/platform_device.h>
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#include <linux/pm_domain.h>
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#include <linux/regulator/consumer.h>
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#include "common.h"
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#include "hardware.h"
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#define IMR_NUM 4
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#define GPC_MAX_IRQS (IMR_NUM * 32)
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#define GPC_LPCR_A7_BSC 0x0
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#define GPC_LPCR_A7_AD 0x4
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#define GPC_LPCR_M4 0x8
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#define GPC_SLPCR 0x14
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#define GPC_MLPCR 0x20
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#define GPC_PGC_ACK_SEL_A7 0x24
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#define GPC_MISC 0x2c
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#define GPC_IMR1_CORE0 0x30
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#define GPC_IMR1_CORE1 0x40
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#define GPC_IMR1_M4 0x50
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#define GPC_SLOT0_CFG 0xb0
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#define GPC_PGC_CPU_MAPPING 0xec
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#define GPC_CPU_PGC_SW_PUP_REQ 0xf0
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#define GPC_PU_PGC_SW_PUP_REQ 0xf8
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#define GPC_CPU_PGC_SW_PDN_REQ 0xfc
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#define GPC_PU_PGC_SW_PDN_REQ 0x104
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#define GPC_GTOR 0x124
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#define GPC_PGC_C0 0x800
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#define GPC_PGC_C0_PUPSCR 0x804
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#define GPC_PGC_SCU_TIMING 0x890
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#define GPC_PGC_C1 0x840
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#define GPC_PGC_C1_PUPSCR 0x844
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#define GPC_PGC_SCU 0x880
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#define GPC_PGC_FM 0xa00
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#define BM_LPCR_A7_BSC_IRQ_SRC_A7_WAKEUP 0x70000000
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#define BM_LPCR_A7_BSC_CPU_CLK_ON_LPM 0x4000
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#define BM_LPCR_A7_BSC_LPM1 0xc
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#define BM_LPCR_A7_BSC_LPM0 0x3
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#define BP_LPCR_A7_BSC_LPM1 2
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#define BP_LPCR_A7_BSC_LPM0 0
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#define BM_LPCR_M4_MASK_DSM_TRIGGER 0x80000000
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#define BM_SLPCR_EN_DSM 0x80000000
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#define BM_SLPCR_RBC_EN 0x40000000
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#define BM_SLPCR_REG_BYPASS_COUNT 0x3f000000
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#define BM_SLPCR_VSTBY 0x4
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#define BM_SLPCR_SBYOS 0x2
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#define BM_SLPCR_BYPASS_PMIC_READY 0x1
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#define BM_SLPCR_EN_A7_FASTWUP_WAIT_MODE 0x10000
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#define BM_LPCR_A7_AD_L2PGE 0x10000
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#define BM_LPCR_A7_AD_EN_C1_PUP 0x800
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#define BM_LPCR_A7_AD_EN_C1_IRQ_PUP 0x400
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#define BM_LPCR_A7_AD_EN_C0_PUP 0x200
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#define BM_LPCR_A7_AD_EN_C0_IRQ_PUP 0x100
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#define BM_LPCR_A7_AD_EN_PLAT_PDN 0x10
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#define BM_LPCR_A7_AD_EN_C1_PDN 0x8
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#define BM_LPCR_A7_AD_EN_C1_WFI_PDN 0x4
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#define BM_LPCR_A7_AD_EN_C0_PDN 0x2
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#define BM_LPCR_A7_AD_EN_C0_WFI_PDN 0x1
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#define BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7 0x2
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#define BM_GPC_PGC_PCG 0x1
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#define BM_GPC_PGC_CORE_PUPSCR 0x7fff80
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#define BM_GPC_PGC_ACK_SEL_A7_DUMMY_PUP_ACK 0x80000000
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#define BM_GPC_PGC_ACK_SEL_A7_DUMMY_PDN_ACK 0x8000
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#define BM_GPC_MLPCR_MEMLP_CTL_DIS 0x1
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#define BP_LPCR_A7_BSC_IRQ_SRC 28
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#define MAX_SLOT_NUMBER 10
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#define A7_LPM_WAIT 0x5
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#define A7_LPM_STOP 0xa
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enum imx_gpc_slot {
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CORE0_A7,
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CORE1_A7,
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SCU_A7,
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FAST_MEGA_MIX,
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MIPI_PHY,
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PCIE_PHY,
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USB_OTG1_PHY,
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USB_OTG2_PHY,
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USB_HSIC_PHY,
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CORE0_M4,
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};
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static void __iomem *gpc_base;
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static u32 gpcv2_wake_irqs[IMR_NUM];
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static u32 gpcv2_saved_imrs[IMR_NUM];
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static u32 gpcv2_saved_imrs_m4[IMR_NUM];
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static u32 gpcv2_mf_irqs[IMR_NUM];
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static u32 gpcv2_mf_request_on[IMR_NUM];
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static DEFINE_SPINLOCK(gpcv2_lock);
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void imx_gpcv2_add_m4_wake_up_irq(u32 hwirq, bool enable)
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{
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unsigned int idx = hwirq / 32;
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unsigned long flags;
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u32 mask;
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/* Sanity check for SPI irq */
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if (hwirq < 32)
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return;
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mask = 1 << hwirq % 32;
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spin_lock_irqsave(&gpcv2_lock, flags);
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gpcv2_wake_irqs[idx] = enable ? gpcv2_wake_irqs[idx] | mask :
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gpcv2_wake_irqs[idx] & ~mask;
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spin_unlock_irqrestore(&gpcv2_lock, flags);
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}
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static int imx_gpcv2_irq_set_wake(struct irq_data *d, unsigned int on)
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{
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unsigned int idx = d->hwirq / 32;
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unsigned long flags;
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u32 mask;
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BUG_ON(idx >= IMR_NUM);
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mask = 1 << d->hwirq % 32;
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spin_lock_irqsave(&gpcv2_lock, flags);
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gpcv2_wake_irqs[idx] = on ? gpcv2_wake_irqs[idx] | mask :
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gpcv2_wake_irqs[idx] & ~mask;
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spin_unlock_irqrestore(&gpcv2_lock, flags);
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return 0;
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}
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void imx_gpcv2_mask_all(void)
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{
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void __iomem *reg_imr1 = gpc_base + GPC_IMR1_CORE0;
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int i;
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for (i = 0; i < IMR_NUM; i++) {
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gpcv2_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4);
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writel_relaxed(~0, reg_imr1 + i * 4);
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}
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}
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void imx_gpcv2_restore_all(void)
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{
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void __iomem *reg_imr1 = gpc_base + GPC_IMR1_CORE0;
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int i;
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for (i = 0; i < IMR_NUM; i++)
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writel_relaxed(gpcv2_saved_imrs[i], reg_imr1 + i * 4);
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}
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void imx_gpcv2_hwirq_unmask(unsigned int hwirq)
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{
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void __iomem *reg;
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u32 val;
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reg = gpc_base + GPC_IMR1_CORE0 + (hwirq / 32) * 4;
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val = readl_relaxed(reg);
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val &= ~(1 << hwirq % 32);
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writel_relaxed(val, reg);
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}
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void imx_gpcv2_hwirq_mask(unsigned int hwirq)
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{
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void __iomem *reg;
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u32 val;
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reg = gpc_base + GPC_IMR1_CORE0 + (hwirq / 32) * 4;
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val = readl_relaxed(reg);
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val |= 1 << (hwirq % 32);
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writel_relaxed(val, reg);
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}
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static void imx_gpcv2_irq_unmask(struct irq_data *d)
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{
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imx_gpcv2_hwirq_unmask(d->hwirq);
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irq_chip_unmask_parent(d);
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}
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static void imx_gpcv2_irq_mask(struct irq_data *d)
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{
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imx_gpcv2_hwirq_mask(d->hwirq);
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irq_chip_mask_parent(d);
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}
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void imx_gpcv2_set_slot_ack(u32 index, enum imx_gpc_slot m_core,
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bool mode, bool ack)
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{
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u32 val;
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if (index >= MAX_SLOT_NUMBER)
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pr_err("Invalid slot index!\n");
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/* set slot */
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writel_relaxed(readl_relaxed(gpc_base + GPC_SLOT0_CFG + index * 4) |
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((mode + 1) << (m_core * 2)),
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gpc_base + GPC_SLOT0_CFG + index * 4);
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if (ack) {
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/* set ack */
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val = readl_relaxed(gpc_base + GPC_PGC_ACK_SEL_A7);
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/* clear dummy ack */
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val &= ~(1 << (15 + (mode ? 16 : 0)));
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val |= 1 << (m_core + (mode ? 16 : 0));
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writel_relaxed(val, gpc_base + GPC_PGC_ACK_SEL_A7);
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}
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}
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void imx_gpcv2_set_lpm_mode(enum mxc_cpu_pwr_mode mode)
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{
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unsigned long flags;
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u32 val1, val2;
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spin_lock_irqsave(&gpcv2_lock, flags);
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val1 = readl_relaxed(gpc_base + GPC_LPCR_A7_BSC);
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val2 = readl_relaxed(gpc_base + GPC_SLPCR);
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/* all cores' LPM settings must be same */
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val1 &= ~(BM_LPCR_A7_BSC_LPM0 | BM_LPCR_A7_BSC_LPM1);
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val1 |= BM_LPCR_A7_BSC_CPU_CLK_ON_LPM;
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val2 &= ~(BM_SLPCR_EN_DSM | BM_SLPCR_VSTBY | BM_SLPCR_RBC_EN |
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BM_SLPCR_SBYOS | BM_SLPCR_BYPASS_PMIC_READY);
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/*
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* GPC: When improper low-power sequence is used,
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* the SoC enters low power mode before the ARM core executes WFI.
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*
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* Software workaround:
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* 1) Software should trigger IRQ #32 (IOMUX) to be always pending
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* by setting IOMUX_GPR1_IRQ.
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* 2) Software should then unmask IRQ #32 in GPC before setting GPC
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* Low-Power mode.
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* 3) Software should mask IRQ #32 right after GPC Low-Power mode
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* is set.
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*/
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switch (mode) {
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case WAIT_CLOCKED:
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imx_gpcv2_hwirq_unmask(0);
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break;
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case WAIT_UNCLOCKED:
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val1 |= A7_LPM_WAIT << BP_LPCR_A7_BSC_LPM0;
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val1 &= ~BM_LPCR_A7_BSC_CPU_CLK_ON_LPM;
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imx_gpcv2_hwirq_mask(0);
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break;
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case STOP_POWER_ON:
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val1 |= A7_LPM_STOP << BP_LPCR_A7_BSC_LPM0;
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val1 &= ~BM_LPCR_A7_BSC_CPU_CLK_ON_LPM;
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val2 |= BM_SLPCR_EN_DSM;
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val2 |= BM_SLPCR_RBC_EN;
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val2 |= BM_SLPCR_BYPASS_PMIC_READY;
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imx_gpcv2_hwirq_mask(0);
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break;
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case STOP_POWER_OFF:
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val1 |= A7_LPM_STOP << BP_LPCR_A7_BSC_LPM0;
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val1 &= ~BM_LPCR_A7_BSC_CPU_CLK_ON_LPM;
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val2 |= BM_SLPCR_EN_DSM;
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val2 |= BM_SLPCR_RBC_EN;
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val2 |= BM_SLPCR_SBYOS;
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val2 |= BM_SLPCR_VSTBY;
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val2 |= BM_SLPCR_BYPASS_PMIC_READY;
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imx_gpcv2_hwirq_mask(0);
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break;
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default:
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return;
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}
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writel_relaxed(val1, gpc_base + GPC_LPCR_A7_BSC);
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writel_relaxed(val2, gpc_base + GPC_SLPCR);
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spin_unlock_irqrestore(&gpcv2_lock, flags);
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}
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void imx_gpcv2_set_plat_power_gate_by_lpm(bool pdn)
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{
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u32 val = readl_relaxed(gpc_base + GPC_LPCR_A7_AD);
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val &= ~(BM_LPCR_A7_AD_EN_PLAT_PDN | BM_LPCR_A7_AD_L2PGE);
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if (pdn)
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val |= BM_LPCR_A7_AD_EN_PLAT_PDN | BM_LPCR_A7_AD_L2PGE;
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writel_relaxed(val, gpc_base + GPC_LPCR_A7_AD);
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}
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void imx_gpcv2_set_m_core_pgc(bool enable, u32 offset)
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{
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u32 val = readl_relaxed(gpc_base + offset) & (~BM_GPC_PGC_PCG);
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if (enable)
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val |= BM_GPC_PGC_PCG;
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writel_relaxed(val, gpc_base + offset);
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}
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void imx_gpcv2_set_core1_pdn_pup_by_software(bool pdn)
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{
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u32 val = readl_relaxed(gpc_base + (pdn ?
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GPC_CPU_PGC_SW_PDN_REQ : GPC_CPU_PGC_SW_PUP_REQ));
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imx_gpcv2_set_m_core_pgc(true, GPC_PGC_C1);
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val |= BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7;
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writel_relaxed(val, gpc_base + (pdn ?
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GPC_CPU_PGC_SW_PDN_REQ : GPC_CPU_PGC_SW_PUP_REQ));
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while ((readl_relaxed(gpc_base + (pdn ?
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GPC_CPU_PGC_SW_PDN_REQ : GPC_CPU_PGC_SW_PUP_REQ)) &
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BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7) != 0)
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;
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imx_gpcv2_set_m_core_pgc(false, GPC_PGC_C1);
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}
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void imx_gpcv2_set_cpu_power_gate_by_wfi(u32 cpu, bool pdn)
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{
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unsigned long flags;
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u32 val;
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spin_lock_irqsave(&gpcv2_lock, flags);
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val = readl_relaxed(gpc_base + GPC_LPCR_A7_AD);
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if (cpu == 0) {
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if (pdn) {
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imx_gpcv2_set_m_core_pgc(true, GPC_PGC_C0);
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val |= BM_LPCR_A7_AD_EN_C0_WFI_PDN |
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BM_LPCR_A7_AD_EN_C0_IRQ_PUP;
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} else {
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imx_gpcv2_set_m_core_pgc(false, GPC_PGC_C0);
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val &= ~(BM_LPCR_A7_AD_EN_C0_WFI_PDN |
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BM_LPCR_A7_AD_EN_C0_IRQ_PUP);
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}
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}
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if (cpu == 1) {
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if (pdn) {
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imx_gpcv2_set_m_core_pgc(true, GPC_PGC_C1);
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val |= BM_LPCR_A7_AD_EN_C1_WFI_PDN |
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BM_LPCR_A7_AD_EN_C1_IRQ_PUP;
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} else {
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imx_gpcv2_set_m_core_pgc(false, GPC_PGC_C1);
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val &= ~(BM_LPCR_A7_AD_EN_C1_WFI_PDN |
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BM_LPCR_A7_AD_EN_C1_IRQ_PUP);
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}
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}
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writel_relaxed(val, gpc_base + GPC_LPCR_A7_AD);
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spin_unlock_irqrestore(&gpcv2_lock, flags);
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}
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void imx_gpcv2_set_cpu_power_gate_by_lpm(u32 cpu, bool pdn)
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{
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unsigned long flags;
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u32 val;
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spin_lock_irqsave(&gpcv2_lock, flags);
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val = readl_relaxed(gpc_base + GPC_LPCR_A7_AD);
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if (cpu == 0) {
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if (pdn)
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val |= BM_LPCR_A7_AD_EN_C0_PDN |
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BM_LPCR_A7_AD_EN_C0_PUP;
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else
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val &= ~(BM_LPCR_A7_AD_EN_C0_PDN |
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BM_LPCR_A7_AD_EN_C0_PUP);
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}
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if (cpu == 1) {
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if (pdn)
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val |= BM_LPCR_A7_AD_EN_C1_PDN |
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BM_LPCR_A7_AD_EN_C1_PUP;
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else
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val &= ~(BM_LPCR_A7_AD_EN_C1_PDN |
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BM_LPCR_A7_AD_EN_C1_PUP);
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}
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writel_relaxed(val, gpc_base + GPC_LPCR_A7_AD);
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spin_unlock_irqrestore(&gpcv2_lock, flags);
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}
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void imx_gpcv2_set_cpu_power_gate_in_idle(bool pdn)
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{
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unsigned long flags;
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u32 cpu;
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for_each_possible_cpu(cpu)
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imx_gpcv2_set_cpu_power_gate_by_lpm(cpu, pdn);
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spin_lock_irqsave(&gpcv2_lock, flags);
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imx_gpcv2_set_m_core_pgc(pdn, GPC_PGC_C0);
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if (num_online_cpus() > 1)
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imx_gpcv2_set_m_core_pgc(pdn, GPC_PGC_C1);
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imx_gpcv2_set_m_core_pgc(pdn, GPC_PGC_SCU);
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imx_gpcv2_set_plat_power_gate_by_lpm(pdn);
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if (pdn) {
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imx_gpcv2_set_slot_ack(0, CORE0_A7, false, false);
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if (num_online_cpus() > 1)
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imx_gpcv2_set_slot_ack(2, CORE1_A7, false, false);
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imx_gpcv2_set_slot_ack(3, SCU_A7, false, true);
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imx_gpcv2_set_slot_ack(6, SCU_A7, true, false);
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if (num_online_cpus() > 1)
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imx_gpcv2_set_slot_ack(6, CORE1_A7, true, false);
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imx_gpcv2_set_slot_ack(6, CORE0_A7, true, true);
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} else {
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writel_relaxed(0x0, gpc_base + GPC_SLOT0_CFG + 0 * 0x4);
|
|
writel_relaxed(0x0, gpc_base + GPC_SLOT0_CFG + 2 * 0x4);
|
|
writel_relaxed(0x0, gpc_base + GPC_SLOT0_CFG + 3 * 0x4);
|
|
writel_relaxed(0x0, gpc_base + GPC_SLOT0_CFG + 6 * 0x4);
|
|
writel_relaxed(0x0, gpc_base + GPC_SLOT0_CFG + 7 * 0x4);
|
|
writel_relaxed(0x0, gpc_base + GPC_SLOT0_CFG + 8 * 0x4);
|
|
writel_relaxed(BM_GPC_PGC_ACK_SEL_A7_DUMMY_PUP_ACK |
|
|
BM_GPC_PGC_ACK_SEL_A7_DUMMY_PDN_ACK,
|
|
gpc_base + GPC_PGC_ACK_SEL_A7);
|
|
imx_gpcv2_enable_rbc(false);
|
|
}
|
|
spin_unlock_irqrestore(&gpcv2_lock, flags);
|
|
}
|
|
|
|
void imx_gpcv2_set_mix_phy_gate_by_lpm(u32 pdn_index, u32 pup_index)
|
|
{
|
|
/* set power down slot */
|
|
writel_relaxed(1 << (FAST_MEGA_MIX * 2),
|
|
gpc_base + GPC_SLOT0_CFG + pdn_index * 4);
|
|
|
|
/* set power up slot */
|
|
writel_relaxed(1 << (FAST_MEGA_MIX * 2 + 1),
|
|
gpc_base + GPC_SLOT0_CFG + pup_index * 4);
|
|
}
|
|
|
|
unsigned int imx_gpcv2_is_mf_mix_off(void)
|
|
{
|
|
return readl_relaxed(gpc_base + GPC_PGC_FM);
|
|
}
|
|
|
|
static void imx_gpcv2_mf_mix_off(void)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < IMR_NUM; i++)
|
|
if (((gpcv2_wake_irqs[i] | gpcv2_mf_request_on[i]) &
|
|
gpcv2_mf_irqs[i]) != 0)
|
|
return;
|
|
|
|
pr_info("Turn off Mega/Fast mix in DSM\n");
|
|
imx_gpcv2_set_slot_ack(1, FAST_MEGA_MIX, false, false);
|
|
imx_gpcv2_set_slot_ack(5, FAST_MEGA_MIX, true, false);
|
|
imx_gpcv2_set_m_core_pgc(true, GPC_PGC_FM);
|
|
}
|
|
|
|
int imx_gpcv2_mf_power_on(unsigned int irq, unsigned int on)
|
|
{
|
|
struct irq_desc *desc = irq_to_desc(irq);
|
|
unsigned long hwirq = desc->irq_data.hwirq;
|
|
unsigned int idx = hwirq / 32;
|
|
unsigned long flags;
|
|
u32 mask = 1 << (hwirq % 32);
|
|
|
|
BUG_ON(idx >= IMR_NUM);
|
|
|
|
spin_lock_irqsave(&gpcv2_lock, flags);
|
|
gpcv2_mf_request_on[idx] = on ? gpcv2_mf_request_on[idx] | mask :
|
|
gpcv2_mf_request_on[idx] & ~mask;
|
|
spin_unlock_irqrestore(&gpcv2_lock, flags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
void imx_gpcv2_enable_rbc(bool enable)
|
|
{
|
|
u32 val;
|
|
|
|
/*
|
|
* need to mask all interrupts in GPC before
|
|
* operating RBC configurations
|
|
*/
|
|
imx_gpcv2_mask_all();
|
|
|
|
/* configure RBC enable bit */
|
|
val = readl_relaxed(gpc_base + GPC_SLPCR);
|
|
val &= ~BM_SLPCR_RBC_EN;
|
|
val |= enable ? BM_SLPCR_RBC_EN : 0;
|
|
writel_relaxed(val, gpc_base + GPC_SLPCR);
|
|
|
|
/* configure RBC count */
|
|
val = readl_relaxed(gpc_base + GPC_SLPCR);
|
|
val &= ~BM_SLPCR_REG_BYPASS_COUNT;
|
|
val |= enable ? BM_SLPCR_REG_BYPASS_COUNT : 0;
|
|
writel(val, gpc_base + GPC_SLPCR);
|
|
|
|
/*
|
|
* need to delay at least 2 cycles of CKIL(32K)
|
|
* due to hardware design requirement, which is
|
|
* ~61us, here we use 65us for safe
|
|
*/
|
|
udelay(65);
|
|
|
|
/* restore GPC interrupt mask settings */
|
|
imx_gpcv2_restore_all();
|
|
}
|
|
|
|
|
|
void imx_gpcv2_pre_suspend(bool arm_power_off)
|
|
{
|
|
void __iomem *reg_imr1 = gpc_base + GPC_IMR1_CORE0;
|
|
int i;
|
|
|
|
if (arm_power_off) {
|
|
imx_gpcv2_set_lpm_mode(STOP_POWER_OFF);
|
|
/* enable core0 power down/up with low power mode */
|
|
imx_gpcv2_set_cpu_power_gate_by_lpm(0, true);
|
|
/* enable plat power down with low power mode */
|
|
imx_gpcv2_set_plat_power_gate_by_lpm(true);
|
|
|
|
/*
|
|
* To avoid confuse, we use slot 0~4 for power down,
|
|
* slot 5~9 for power up.
|
|
*
|
|
* Power down slot sequence:
|
|
* Slot0 -> CORE0
|
|
* Slot1 -> Mega/Fast MIX
|
|
* Slot2 -> SCU
|
|
*
|
|
* Power up slot sequence:
|
|
* Slot5 -> Mega/Fast MIX
|
|
* Slot6 -> SCU
|
|
* Slot7 -> CORE0
|
|
*/
|
|
imx_gpcv2_set_slot_ack(0, CORE0_A7, false, false);
|
|
imx_gpcv2_set_slot_ack(2, SCU_A7, false, true);
|
|
|
|
if ((!imx_src_is_m4_enabled()) ||
|
|
(imx_src_is_m4_enabled() && imx_mu_is_m4_in_stop()))
|
|
imx_gpcv2_mf_mix_off();;
|
|
|
|
imx_gpcv2_set_slot_ack(6, SCU_A7, true, false);
|
|
imx_gpcv2_set_slot_ack(6, CORE0_A7, true, true);
|
|
|
|
/* enable core0, scu */
|
|
imx_gpcv2_set_m_core_pgc(true, GPC_PGC_C0);
|
|
imx_gpcv2_set_m_core_pgc(true, GPC_PGC_SCU);
|
|
} else {
|
|
imx_gpcv2_set_lpm_mode(STOP_POWER_ON);
|
|
}
|
|
|
|
for (i = 0; i < IMR_NUM; i++) {
|
|
gpcv2_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4);
|
|
writel_relaxed(~gpcv2_wake_irqs[i], reg_imr1 + i * 4);
|
|
}
|
|
}
|
|
|
|
void imx_gpcv2_enable_wakeup_for_m4(void)
|
|
{
|
|
void __iomem *reg_imr2 = gpc_base + GPC_IMR1_M4;
|
|
u32 i;
|
|
|
|
for (i = 0; i < IMR_NUM; i++) {
|
|
gpcv2_saved_imrs_m4[i] = readl_relaxed(reg_imr2 + i * 4);
|
|
writel_relaxed(~gpcv2_wake_irqs[i], reg_imr2 + i * 4);
|
|
}
|
|
}
|
|
|
|
void imx_gpcv2_disable_wakeup_for_m4(void)
|
|
{
|
|
void __iomem *reg_imr2 = gpc_base + GPC_IMR1_M4;
|
|
u32 i;
|
|
|
|
for (i = 0; i < IMR_NUM; i++)
|
|
writel_relaxed(gpcv2_saved_imrs_m4[i], reg_imr2 + i * 4);
|
|
}
|
|
|
|
void imx_gpcv2_post_resume(void)
|
|
{
|
|
void __iomem *reg_imr1 = gpc_base + GPC_IMR1_CORE0;
|
|
int i, val;
|
|
|
|
/* only external IRQs to wake up LPM and core 0/1 */
|
|
val = readl_relaxed(gpc_base + GPC_LPCR_A7_BSC);
|
|
val |= BM_LPCR_A7_BSC_IRQ_SRC_A7_WAKEUP;
|
|
writel_relaxed(val, gpc_base + GPC_LPCR_A7_BSC);
|
|
/* mask m4 dsm trigger if M4 NOT enabled */
|
|
if (!imx_src_is_m4_enabled())
|
|
writel_relaxed(readl_relaxed(gpc_base + GPC_LPCR_M4) |
|
|
BM_LPCR_M4_MASK_DSM_TRIGGER, gpc_base + GPC_LPCR_M4);
|
|
/* set mega/fast mix in A7 domain */
|
|
writel_relaxed(0x1, gpc_base + GPC_PGC_CPU_MAPPING);
|
|
/* set SCU timing */
|
|
writel_relaxed((0x59 << 10) | 0x5B | (0x2 << 20),
|
|
gpc_base + GPC_PGC_SCU_TIMING);
|
|
|
|
/* set C0/C1 power up timming per design requirement */
|
|
val = readl_relaxed(gpc_base + GPC_PGC_C0_PUPSCR);
|
|
val &= ~BM_GPC_PGC_CORE_PUPSCR;
|
|
val |= (0x1A << 7);
|
|
writel_relaxed(val, gpc_base + GPC_PGC_C0_PUPSCR);
|
|
|
|
val = readl_relaxed(gpc_base + GPC_PGC_C1_PUPSCR);
|
|
val &= ~BM_GPC_PGC_CORE_PUPSCR;
|
|
val |= (0x1A << 7);
|
|
writel_relaxed(val, gpc_base + GPC_PGC_C1_PUPSCR);
|
|
|
|
val = readl_relaxed(gpc_base + GPC_SLPCR);
|
|
val &= ~(BM_SLPCR_EN_DSM);
|
|
if (!imx_src_is_m4_enabled())
|
|
val &= ~(BM_SLPCR_VSTBY | BM_SLPCR_RBC_EN |
|
|
BM_SLPCR_SBYOS | BM_SLPCR_BYPASS_PMIC_READY);
|
|
val |= BM_SLPCR_EN_A7_FASTWUP_WAIT_MODE;
|
|
writel_relaxed(val, gpc_base + GPC_SLPCR);
|
|
|
|
if (imx_get_soc_revision() == IMX_CHIP_REVISION_1_0) {
|
|
/* disable memory low power mode */
|
|
val = readl_relaxed(gpc_base + GPC_MLPCR);
|
|
val |= BM_GPC_MLPCR_MEMLP_CTL_DIS;
|
|
writel_relaxed(val, gpc_base + GPC_MLPCR);
|
|
}
|
|
|
|
for (i = 0; i < IMR_NUM; i++)
|
|
writel_relaxed(gpcv2_saved_imrs[i], reg_imr1 + i * 4);
|
|
|
|
imx_gpcv2_set_lpm_mode(WAIT_CLOCKED);
|
|
imx_gpcv2_set_cpu_power_gate_by_lpm(0, false);
|
|
imx_gpcv2_set_plat_power_gate_by_lpm(false);
|
|
|
|
imx_gpcv2_set_m_core_pgc(false, GPC_PGC_C0);
|
|
imx_gpcv2_set_m_core_pgc(false, GPC_PGC_SCU);
|
|
imx_gpcv2_set_m_core_pgc(false, GPC_PGC_FM);
|
|
for (i = 0; i < MAX_SLOT_NUMBER; i++){
|
|
if (i == 1 || i == 5) /* skip slts m4 uses */
|
|
continue;
|
|
writel_relaxed(0x0, gpc_base + GPC_SLOT0_CFG + i * 0x4);
|
|
}
|
|
writel_relaxed(BM_GPC_PGC_ACK_SEL_A7_DUMMY_PUP_ACK |
|
|
BM_GPC_PGC_ACK_SEL_A7_DUMMY_PDN_ACK,
|
|
gpc_base + GPC_PGC_ACK_SEL_A7);
|
|
|
|
/* disable RBC */
|
|
imx_gpcv2_enable_rbc(false);
|
|
}
|
|
|
|
static struct irq_chip imx_gpcv2_chip = {
|
|
.name = "GPCV2",
|
|
.irq_eoi = irq_chip_eoi_parent,
|
|
.irq_mask = imx_gpcv2_irq_mask,
|
|
.irq_unmask = imx_gpcv2_irq_unmask,
|
|
.irq_retrigger = irq_chip_retrigger_hierarchy,
|
|
.irq_set_wake = imx_gpcv2_irq_set_wake,
|
|
#ifdef CONFIG_SMP
|
|
.irq_set_affinity = irq_chip_set_affinity_parent,
|
|
#endif
|
|
};
|
|
|
|
static int imx_gpcv2_domain_xlate(struct irq_domain *domain,
|
|
struct device_node *controller,
|
|
const u32 *intspec,
|
|
unsigned int intsize,
|
|
unsigned long *out_hwirq,
|
|
unsigned int *out_type)
|
|
{
|
|
if (irq_domain_get_of_node(domain) != controller)
|
|
return -EINVAL; /* Shouldn't happen, really... */
|
|
if (intsize != 3)
|
|
return -EINVAL; /* Not GIC compliant */
|
|
if (intspec[0] != 0)
|
|
return -EINVAL; /* No PPI should point to this domain */
|
|
|
|
*out_hwirq = intspec[1];
|
|
*out_type = intspec[2];
|
|
return 0;
|
|
}
|
|
|
|
static int imx_gpcv2_domain_alloc(struct irq_domain *domain,
|
|
unsigned int irq,
|
|
unsigned int nr_irqs, void *data)
|
|
{
|
|
struct irq_fwspec *fwspec = data;
|
|
struct irq_fwspec parent_fwspec;
|
|
irq_hw_number_t hwirq;
|
|
int i;
|
|
|
|
if (fwspec->param_count != 3)
|
|
return -EINVAL; /* Not GIC compliant */
|
|
if (fwspec->param[0] != 0)
|
|
return -EINVAL; /* No PPI should point to this domain */
|
|
|
|
hwirq = fwspec->param[1];
|
|
if (hwirq >= GPC_MAX_IRQS)
|
|
return -EINVAL; /* Can't deal with this */
|
|
|
|
for (i = 0; i < nr_irqs; i++)
|
|
irq_domain_set_hwirq_and_chip(domain, irq + i, hwirq + i,
|
|
&imx_gpcv2_chip, NULL);
|
|
|
|
parent_fwspec.fwnode = domain->parent->fwnode;
|
|
parent_fwspec.param_count = 3;
|
|
parent_fwspec.param[0] = 0;
|
|
parent_fwspec.param[1] = hwirq;
|
|
parent_fwspec.param[2] = fwspec->param[2];
|
|
|
|
return irq_domain_alloc_irqs_parent(domain, irq, nr_irqs,
|
|
&parent_fwspec);
|
|
}
|
|
|
|
static struct irq_domain_ops imx_gpcv2_domain_ops = {
|
|
.xlate = imx_gpcv2_domain_xlate,
|
|
.alloc = imx_gpcv2_domain_alloc,
|
|
.free = irq_domain_free_irqs_common,
|
|
};
|
|
|
|
static int __init imx_gpcv2_init(struct device_node *node,
|
|
struct device_node *parent)
|
|
{
|
|
struct irq_domain *parent_domain, *domain;
|
|
int i, val;
|
|
|
|
if (!parent) {
|
|
pr_err("%s: no parent, giving up\n", node->full_name);
|
|
return -ENODEV;
|
|
}
|
|
|
|
parent_domain = irq_find_host(parent);
|
|
if (!parent_domain) {
|
|
pr_err("%s: unable to obtain parent domain\n", node->full_name);
|
|
return -ENXIO;
|
|
}
|
|
|
|
gpc_base = of_iomap(node, 0);
|
|
if (WARN_ON(!gpc_base))
|
|
return -ENOMEM;
|
|
|
|
domain = irq_domain_add_hierarchy(parent_domain, 0, GPC_MAX_IRQS,
|
|
node, &imx_gpcv2_domain_ops,
|
|
NULL);
|
|
if (!domain) {
|
|
iounmap(gpc_base);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
/* Initially mask all interrupts */
|
|
for (i = 0; i < IMR_NUM; i++) {
|
|
writel_relaxed(~0, gpc_base + GPC_IMR1_CORE0 + i * 4);
|
|
writel_relaxed(~0, gpc_base + GPC_IMR1_CORE1 + i * 4);
|
|
}
|
|
/*
|
|
* Due to hardware design requirement, need to make sure GPR
|
|
* interrupt(#32) is unmasked during RUN mode to avoid entering
|
|
* DSM by mistake.
|
|
*/
|
|
writel_relaxed(~0x1, gpc_base + GPC_IMR1_CORE0);
|
|
|
|
/* Read supported wakeup source in M/F domain */
|
|
if (cpu_is_imx7d()) {
|
|
of_property_read_u32_index(node, "fsl,mf-mix-wakeup-irq", 0,
|
|
&gpcv2_mf_irqs[0]);
|
|
of_property_read_u32_index(node, "fsl,mf-mix-wakeup-irq", 1,
|
|
&gpcv2_mf_irqs[1]);
|
|
of_property_read_u32_index(node, "fsl,mf-mix-wakeup-irq", 2,
|
|
&gpcv2_mf_irqs[2]);
|
|
of_property_read_u32_index(node, "fsl,mf-mix-wakeup-irq", 3,
|
|
&gpcv2_mf_irqs[3]);
|
|
if (!(gpcv2_mf_irqs[0] | gpcv2_mf_irqs[1] |
|
|
gpcv2_mf_irqs[2] | gpcv2_mf_irqs[3]))
|
|
pr_info("No wakeup source in Mega/Fast domain found!\n");
|
|
}
|
|
|
|
/* only external IRQs to wake up LPM and core 0/1 */
|
|
val = readl_relaxed(gpc_base + GPC_LPCR_A7_BSC);
|
|
val |= BM_LPCR_A7_BSC_IRQ_SRC_A7_WAKEUP;
|
|
writel_relaxed(val, gpc_base + GPC_LPCR_A7_BSC);
|
|
/* mask m4 dsm trigger if M4 NOT enabled */
|
|
if (!imx_src_is_m4_enabled())
|
|
writel_relaxed(readl_relaxed(gpc_base + GPC_LPCR_M4) |
|
|
BM_LPCR_M4_MASK_DSM_TRIGGER, gpc_base + GPC_LPCR_M4);
|
|
/* set mega/fast mix in A7 domain */
|
|
writel_relaxed(0x1, gpc_base + GPC_PGC_CPU_MAPPING);
|
|
/* set SCU timing */
|
|
writel_relaxed((0x59 << 10) | 0x5B | (0x2 << 20),
|
|
gpc_base + GPC_PGC_SCU_TIMING);
|
|
|
|
/* set C0/C1 power up timming per design requirement */
|
|
val = readl_relaxed(gpc_base + GPC_PGC_C0_PUPSCR);
|
|
val &= ~BM_GPC_PGC_CORE_PUPSCR;
|
|
val |= (0x1A << 7);
|
|
writel_relaxed(val, gpc_base + GPC_PGC_C0_PUPSCR);
|
|
|
|
val = readl_relaxed(gpc_base + GPC_PGC_C1_PUPSCR);
|
|
val &= ~BM_GPC_PGC_CORE_PUPSCR;
|
|
val |= (0x1A << 7);
|
|
writel_relaxed(val, gpc_base + GPC_PGC_C1_PUPSCR);
|
|
|
|
writel_relaxed(BM_GPC_PGC_ACK_SEL_A7_DUMMY_PUP_ACK |
|
|
BM_GPC_PGC_ACK_SEL_A7_DUMMY_PDN_ACK,
|
|
gpc_base + GPC_PGC_ACK_SEL_A7);
|
|
|
|
val = readl_relaxed(gpc_base + GPC_SLPCR);
|
|
val &= ~(BM_SLPCR_EN_DSM);
|
|
if (!imx_src_is_m4_enabled())
|
|
val &= ~(BM_SLPCR_VSTBY | BM_SLPCR_RBC_EN |
|
|
BM_SLPCR_SBYOS | BM_SLPCR_BYPASS_PMIC_READY);
|
|
val |= BM_SLPCR_EN_A7_FASTWUP_WAIT_MODE;
|
|
writel_relaxed(val, gpc_base + GPC_SLPCR);
|
|
|
|
if (imx_get_soc_revision() == IMX_CHIP_REVISION_1_0) {
|
|
/* disable memory low power mode */
|
|
val = readl_relaxed(gpc_base + GPC_MLPCR);
|
|
val |= BM_GPC_MLPCR_MEMLP_CTL_DIS;
|
|
writel_relaxed(val, gpc_base + GPC_MLPCR);
|
|
}
|
|
|
|
/* disable RBC */
|
|
imx_gpcv2_enable_rbc(false);
|
|
|
|
/*
|
|
* Clear the OF_POPULATED flag set in of_irq_init so that
|
|
* later the GPC power domain driver will not be skipped.
|
|
*/
|
|
of_node_clear_flag(node, OF_POPULATED);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* We cannot use the IRQCHIP_DECLARE macro that lives in
|
|
* drivers/irqchip, so we're forced to roll our own. Not very nice.
|
|
*/
|
|
OF_DECLARE_2(irqchip, imx_gpcv2, "fsl,imx7d-gpc", imx_gpcv2_init);
|
|
|
|
void __init imx_gpcv2_check_dt(void)
|
|
{
|
|
struct device_node *np;
|
|
|
|
np = of_find_compatible_node(NULL, NULL, "fsl,imx7d-gpc");
|
|
if (WARN_ON(!np))
|
|
return;
|
|
|
|
if (WARN_ON(!of_find_property(np, "interrupt-controller", NULL))) {
|
|
pr_warn("Outdated DT detected, suspend/resume will NOT work\n");
|
|
|
|
/* map GPC, so that at least CPUidle and WARs keep working */
|
|
gpc_base = of_iomap(np, 0);
|
|
}
|
|
}
|