c8a64268d1
Commit 9bef3d4197
"serial: group all the 8250 related code together"
inadvertently swept up the m32r driver in the move, because
it had comments mentioning 8250 registers within it. However
these are only there by nature of the driver being based off
the 8250 source code -- the hardware itself does not actually
have any relation to the original 8250 style UARTs.
Reported-by: Jiri Slaby <jirislaby@gmail.com>
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
153 lines
5.3 KiB
C
153 lines
5.3 KiB
C
/*
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* m32r_sio_reg.h
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*
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* Copyright (C) 1992, 1994 by Theodore Ts'o.
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* Copyright (C) 2004 Hirokazu Takata <takata at linux-m32r.org>
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*
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* Redistribution of this file is permitted under the terms of the GNU
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* Public License (GPL)
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*
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* These are the UART port assignments, expressed as offsets from the base
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* register. These assignments should hold for any serial port based on
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* a 8250, 16450, or 16550(A).
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*/
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#ifndef _M32R_SIO_REG_H
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#define _M32R_SIO_REG_H
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#ifdef CONFIG_SERIAL_M32R_PLDSIO
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#define SIOCR 0x000
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#define SIOMOD0 0x002
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#define SIOMOD1 0x004
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#define SIOSTS 0x006
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#define SIOTRCR 0x008
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#define SIOBAUR 0x00a
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// #define SIORBAUR 0x018
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#define SIOTXB 0x00c
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#define SIORXB 0x00e
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#define UART_RX ((unsigned long) PLD_ESIO0RXB)
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/* In: Receive buffer (DLAB=0) */
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#define UART_TX ((unsigned long) PLD_ESIO0TXB)
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/* Out: Transmit buffer (DLAB=0) */
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#define UART_DLL 0 /* Out: Divisor Latch Low (DLAB=1) */
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#define UART_TRG 0 /* (LCR=BF) FCTR bit 7 selects Rx or Tx
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* In: Fifo count
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* Out: Fifo custom trigger levels
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* XR16C85x only */
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#define UART_DLM 0 /* Out: Divisor Latch High (DLAB=1) */
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#define UART_IER ((unsigned long) PLD_ESIO0INTCR)
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/* Out: Interrupt Enable Register */
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#define UART_FCTR 0 /* (LCR=BF) Feature Control Register
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* XR16C85x only */
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#define UART_IIR 0 /* In: Interrupt ID Register */
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#define UART_FCR 0 /* Out: FIFO Control Register */
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#define UART_EFR 0 /* I/O: Extended Features Register */
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/* (DLAB=1, 16C660 only) */
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#define UART_LCR 0 /* Out: Line Control Register */
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#define UART_MCR 0 /* Out: Modem Control Register */
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#define UART_LSR ((unsigned long) PLD_ESIO0STS)
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/* In: Line Status Register */
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#define UART_MSR 0 /* In: Modem Status Register */
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#define UART_SCR 0 /* I/O: Scratch Register */
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#define UART_EMSR 0 /* (LCR=BF) Extended Mode Select Register
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* FCTR bit 6 selects SCR or EMSR
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* XR16c85x only */
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#else /* not CONFIG_SERIAL_M32R_PLDSIO */
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#define SIOCR 0x000
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#define SIOMOD0 0x004
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#define SIOMOD1 0x008
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#define SIOSTS 0x00c
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#define SIOTRCR 0x010
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#define SIOBAUR 0x014
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#define SIORBAUR 0x018
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#define SIOTXB 0x01c
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#define SIORXB 0x020
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#define UART_RX M32R_SIO0_RXB_PORTL /* In: Receive buffer (DLAB=0) */
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#define UART_TX M32R_SIO0_TXB_PORTL /* Out: Transmit buffer (DLAB=0) */
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#define UART_DLL 0 /* Out: Divisor Latch Low (DLAB=1) */
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#define UART_TRG 0 /* (LCR=BF) FCTR bit 7 selects Rx or Tx
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* In: Fifo count
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* Out: Fifo custom trigger levels
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* XR16C85x only */
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#define UART_DLM 0 /* Out: Divisor Latch High (DLAB=1) */
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#define UART_IER M32R_SIO0_TRCR_PORTL /* Out: Interrupt Enable Register */
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#define UART_FCTR 0 /* (LCR=BF) Feature Control Register
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* XR16C85x only */
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#define UART_IIR 0 /* In: Interrupt ID Register */
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#define UART_FCR 0 /* Out: FIFO Control Register */
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#define UART_EFR 0 /* I/O: Extended Features Register */
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/* (DLAB=1, 16C660 only) */
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#define UART_LCR 0 /* Out: Line Control Register */
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#define UART_MCR 0 /* Out: Modem Control Register */
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#define UART_LSR M32R_SIO0_STS_PORTL /* In: Line Status Register */
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#define UART_MSR 0 /* In: Modem Status Register */
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#define UART_SCR 0 /* I/O: Scratch Register */
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#define UART_EMSR 0 /* (LCR=BF) Extended Mode Select Register
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* FCTR bit 6 selects SCR or EMSR
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* XR16c85x only */
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#endif /* CONFIG_SERIAL_M32R_PLDSIO */
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#define UART_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
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/*
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* These are the definitions for the Line Control Register
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*
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* Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting
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* UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
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*/
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#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
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#define UART_LCR_SBC 0x40 /* Set break control */
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#define UART_LCR_SPAR 0x20 /* Stick parity (?) */
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#define UART_LCR_EPAR 0x10 /* Even parity select */
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#define UART_LCR_PARITY 0x08 /* Parity Enable */
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#define UART_LCR_STOP 0x04 /* Stop bits: 0=1 stop bit, 1= 2 stop bits */
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#define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */
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#define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */
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#define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */
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#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
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/*
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* These are the definitions for the Line Status Register
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*/
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#define UART_LSR_TEMT 0x02 /* Transmitter empty */
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#define UART_LSR_THRE 0x01 /* Transmit-hold-register empty */
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#define UART_LSR_BI 0x00 /* Break interrupt indicator */
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#define UART_LSR_FE 0x80 /* Frame error indicator */
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#define UART_LSR_PE 0x40 /* Parity error indicator */
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#define UART_LSR_OE 0x20 /* Overrun error indicator */
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#define UART_LSR_DR 0x04 /* Receiver data ready */
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/*
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* These are the definitions for the Interrupt Identification Register
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*/
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#define UART_IIR_NO_INT 0x01 /* No interrupts pending */
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#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
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#define UART_IIR_MSI 0x00 /* Modem status interrupt */
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#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
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#define UART_IIR_RDI 0x04 /* Receiver data interrupt */
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#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
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/*
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* These are the definitions for the Interrupt Enable Register
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*/
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#define UART_IER_MSI 0x00 /* Enable Modem status interrupt */
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#define UART_IER_RLSI 0x08 /* Enable receiver line status interrupt */
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#define UART_IER_THRI 0x03 /* Enable Transmitter holding register int. */
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#define UART_IER_RDI 0x04 /* Enable receiver data interrupt */
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#endif /* _M32R_SIO_REG_H */
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