6a00a4221a
The H3 ES1.x exhibits dot clock duty cycle stability issues. We can work around them by configuring the DPLL to twice the desired frequency, coupled with a /2 post-divider. This isn't needed on other SoCs and breaks HDMI output on M3-W for a currently unknown reason, so restrict the workaround to H3 ES1.x. From an implementation point of view, move work around handling outside of the rcar_du_dpll_divider() function by requesting a x2 DPLL output frequency explicitly. The existing post-divider calculation mechanism will then take care of dividing the clock by two automatically. While at it, print a more useful debugging message to ease debugging clock rate issues. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> |
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.. | ||
Kconfig | ||
Makefile | ||
rcar_du_crtc.c | ||
rcar_du_crtc.h | ||
rcar_du_drv.c | ||
rcar_du_drv.h | ||
rcar_du_encoder.c | ||
rcar_du_encoder.h | ||
rcar_du_group.c | ||
rcar_du_group.h | ||
rcar_du_kms.c | ||
rcar_du_kms.h | ||
rcar_du_lvdscon.c | ||
rcar_du_lvdscon.h | ||
rcar_du_lvdsenc.c | ||
rcar_du_lvdsenc.h | ||
rcar_du_plane.c | ||
rcar_du_plane.h | ||
rcar_du_regs.h | ||
rcar_du_vsp.c | ||
rcar_du_vsp.h | ||
rcar_dw_hdmi.c | ||
rcar_lvds_regs.h |