![Arnd Bergmann](/assets/img/avatar_default.png)
MULTI_IRQ_HANDLER and SPARSE_IRQ are now required everywhere because mach/irqs.h and mach/entry-macros.S are gone but the symbols are only selected for AT91SAM9, not for the NOMMU parts. A few files now need to include linux/io.h directly, which used to be included through other headers that have changed. The new at91_aic_irq_priorities variable is only used with CONFIG_OF enabled and should not be visible otherwise. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Ludovic Desroches <ludovic.desroches@atmel.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
547 lines
13 KiB
C
547 lines
13 KiB
C
/*
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* linux/arch/arm/mach-at91/irq.c
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*
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* Copyright (C) 2004 SAN People
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* Copyright (C) 2004 ATMEL
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* Copyright (C) Rick Bronson
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/mm.h>
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#include <linux/bitmap.h>
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#include <linux/types.h>
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#include <linux/irq.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/irqdomain.h>
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#include <linux/err.h>
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#include <linux/slab.h>
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#include <mach/hardware.h>
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#include <asm/irq.h>
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#include <asm/setup.h>
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#include <asm/exception.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/irq.h>
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#include <asm/mach/map.h>
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#include <mach/at91_aic.h>
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void __iomem *at91_aic_base;
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static struct irq_domain *at91_aic_domain;
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static struct device_node *at91_aic_np;
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static unsigned int n_irqs = NR_AIC_IRQS;
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static unsigned long at91_aic_caps = 0;
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/* AIC5 introduces a Source Select Register */
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#define AT91_AIC_CAP_AIC5 (1 << 0)
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#define has_aic5() (at91_aic_caps & AT91_AIC_CAP_AIC5)
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#ifdef CONFIG_PM
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static unsigned long *wakeups;
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static unsigned long *backups;
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#define set_backup(bit) set_bit(bit, backups)
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#define clear_backup(bit) clear_bit(bit, backups)
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static int at91_aic_pm_init(void)
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{
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backups = kzalloc(BITS_TO_LONGS(n_irqs) * sizeof(*backups), GFP_KERNEL);
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if (!backups)
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return -ENOMEM;
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wakeups = kzalloc(BITS_TO_LONGS(n_irqs) * sizeof(*backups), GFP_KERNEL);
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if (!wakeups) {
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kfree(backups);
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return -ENOMEM;
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}
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return 0;
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}
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static int at91_aic_set_wake(struct irq_data *d, unsigned value)
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{
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if (unlikely(d->hwirq >= n_irqs))
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return -EINVAL;
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if (value)
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set_bit(d->hwirq, wakeups);
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else
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clear_bit(d->hwirq, wakeups);
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return 0;
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}
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void at91_irq_suspend(void)
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{
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int i = 0, bit;
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if (has_aic5()) {
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/* disable enabled irqs */
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while ((bit = find_next_bit(backups, n_irqs, i)) < n_irqs) {
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at91_aic_write(AT91_AIC5_SSR,
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bit & AT91_AIC5_INTSEL_MSK);
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at91_aic_write(AT91_AIC5_IDCR, 1);
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i = bit;
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}
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/* enable wakeup irqs */
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i = 0;
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while ((bit = find_next_bit(wakeups, n_irqs, i)) < n_irqs) {
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at91_aic_write(AT91_AIC5_SSR,
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bit & AT91_AIC5_INTSEL_MSK);
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at91_aic_write(AT91_AIC5_IECR, 1);
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i = bit;
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}
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} else {
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at91_aic_write(AT91_AIC_IDCR, *backups);
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at91_aic_write(AT91_AIC_IECR, *wakeups);
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}
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}
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void at91_irq_resume(void)
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{
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int i = 0, bit;
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if (has_aic5()) {
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/* disable wakeup irqs */
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while ((bit = find_next_bit(wakeups, n_irqs, i)) < n_irqs) {
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at91_aic_write(AT91_AIC5_SSR,
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bit & AT91_AIC5_INTSEL_MSK);
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at91_aic_write(AT91_AIC5_IDCR, 1);
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i = bit;
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}
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/* enable irqs disabled for suspend */
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i = 0;
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while ((bit = find_next_bit(backups, n_irqs, i)) < n_irqs) {
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at91_aic_write(AT91_AIC5_SSR,
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bit & AT91_AIC5_INTSEL_MSK);
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at91_aic_write(AT91_AIC5_IECR, 1);
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i = bit;
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}
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} else {
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at91_aic_write(AT91_AIC_IDCR, *wakeups);
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at91_aic_write(AT91_AIC_IECR, *backups);
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}
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}
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#else
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static inline int at91_aic_pm_init(void)
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{
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return 0;
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}
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#define set_backup(bit)
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#define clear_backup(bit)
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#define at91_aic_set_wake NULL
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#endif /* CONFIG_PM */
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asmlinkage void __exception_irq_entry
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at91_aic_handle_irq(struct pt_regs *regs)
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{
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u32 irqnr;
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u32 irqstat;
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irqnr = at91_aic_read(AT91_AIC_IVR);
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irqstat = at91_aic_read(AT91_AIC_ISR);
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/*
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* ISR value is 0 when there is no current interrupt or when there is
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* a spurious interrupt
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*/
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if (!irqstat)
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at91_aic_write(AT91_AIC_EOICR, 0);
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else
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handle_IRQ(irqnr, regs);
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}
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asmlinkage void __exception_irq_entry
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at91_aic5_handle_irq(struct pt_regs *regs)
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{
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u32 irqnr;
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u32 irqstat;
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irqnr = at91_aic_read(AT91_AIC5_IVR);
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irqstat = at91_aic_read(AT91_AIC5_ISR);
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if (!irqstat)
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at91_aic_write(AT91_AIC5_EOICR, 0);
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else
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handle_IRQ(irqnr, regs);
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}
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static void at91_aic_mask_irq(struct irq_data *d)
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{
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/* Disable interrupt on AIC */
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at91_aic_write(AT91_AIC_IDCR, 1 << d->hwirq);
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/* Update ISR cache */
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clear_backup(d->hwirq);
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}
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static void __maybe_unused at91_aic5_mask_irq(struct irq_data *d)
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{
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/* Disable interrupt on AIC5 */
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at91_aic_write(AT91_AIC5_SSR, d->hwirq & AT91_AIC5_INTSEL_MSK);
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at91_aic_write(AT91_AIC5_IDCR, 1);
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/* Update ISR cache */
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clear_backup(d->hwirq);
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}
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static void at91_aic_unmask_irq(struct irq_data *d)
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{
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/* Enable interrupt on AIC */
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at91_aic_write(AT91_AIC_IECR, 1 << d->hwirq);
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/* Update ISR cache */
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set_backup(d->hwirq);
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}
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static void __maybe_unused at91_aic5_unmask_irq(struct irq_data *d)
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{
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/* Enable interrupt on AIC5 */
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at91_aic_write(AT91_AIC5_SSR, d->hwirq & AT91_AIC5_INTSEL_MSK);
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at91_aic_write(AT91_AIC5_IECR, 1);
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/* Update ISR cache */
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set_backup(d->hwirq);
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}
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static void at91_aic_eoi(struct irq_data *d)
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{
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/*
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* Mark end-of-interrupt on AIC, the controller doesn't care about
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* the value written. Moreover it's a write-only register.
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*/
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at91_aic_write(AT91_AIC_EOICR, 0);
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}
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static void __maybe_unused at91_aic5_eoi(struct irq_data *d)
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{
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at91_aic_write(AT91_AIC5_EOICR, 0);
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}
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unsigned long *at91_extern_irq;
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#define is_extern_irq(hwirq) test_bit(hwirq, at91_extern_irq)
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static int at91_aic_compute_srctype(struct irq_data *d, unsigned type)
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{
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int srctype;
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switch (type) {
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case IRQ_TYPE_LEVEL_HIGH:
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srctype = AT91_AIC_SRCTYPE_HIGH;
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break;
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case IRQ_TYPE_EDGE_RISING:
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srctype = AT91_AIC_SRCTYPE_RISING;
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break;
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case IRQ_TYPE_LEVEL_LOW:
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if ((d->hwirq == AT91_ID_FIQ) || is_extern_irq(d->hwirq)) /* only supported on external interrupts */
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srctype = AT91_AIC_SRCTYPE_LOW;
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else
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srctype = -EINVAL;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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if ((d->hwirq == AT91_ID_FIQ) || is_extern_irq(d->hwirq)) /* only supported on external interrupts */
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srctype = AT91_AIC_SRCTYPE_FALLING;
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else
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srctype = -EINVAL;
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break;
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default:
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srctype = -EINVAL;
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}
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return srctype;
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}
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static int at91_aic_set_type(struct irq_data *d, unsigned type)
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{
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unsigned int smr;
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int srctype;
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srctype = at91_aic_compute_srctype(d, type);
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if (srctype < 0)
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return srctype;
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if (has_aic5()) {
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at91_aic_write(AT91_AIC5_SSR,
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d->hwirq & AT91_AIC5_INTSEL_MSK);
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smr = at91_aic_read(AT91_AIC5_SMR) & ~AT91_AIC_SRCTYPE;
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at91_aic_write(AT91_AIC5_SMR, smr | srctype);
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} else {
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smr = at91_aic_read(AT91_AIC_SMR(d->hwirq))
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& ~AT91_AIC_SRCTYPE;
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at91_aic_write(AT91_AIC_SMR(d->hwirq), smr | srctype);
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}
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return 0;
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}
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static struct irq_chip at91_aic_chip = {
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.name = "AIC",
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.irq_mask = at91_aic_mask_irq,
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.irq_unmask = at91_aic_unmask_irq,
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.irq_set_type = at91_aic_set_type,
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.irq_set_wake = at91_aic_set_wake,
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.irq_eoi = at91_aic_eoi,
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};
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static void __init at91_aic_hw_init(unsigned int spu_vector)
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{
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int i;
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/*
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* Perform 8 End Of Interrupt Command to make sure AIC
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* will not Lock out nIRQ
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*/
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for (i = 0; i < 8; i++)
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at91_aic_write(AT91_AIC_EOICR, 0);
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/*
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* Spurious Interrupt ID in Spurious Vector Register.
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* When there is no current interrupt, the IRQ Vector Register
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* reads the value stored in AIC_SPU
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*/
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at91_aic_write(AT91_AIC_SPU, spu_vector);
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/* No debugging in AIC: Debug (Protect) Control Register */
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at91_aic_write(AT91_AIC_DCR, 0);
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/* Disable and clear all interrupts initially */
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at91_aic_write(AT91_AIC_IDCR, 0xFFFFFFFF);
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at91_aic_write(AT91_AIC_ICCR, 0xFFFFFFFF);
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}
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static void __init __maybe_unused at91_aic5_hw_init(unsigned int spu_vector)
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{
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int i;
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/*
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* Perform 8 End Of Interrupt Command to make sure AIC
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* will not Lock out nIRQ
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*/
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for (i = 0; i < 8; i++)
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at91_aic_write(AT91_AIC5_EOICR, 0);
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/*
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* Spurious Interrupt ID in Spurious Vector Register.
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* When there is no current interrupt, the IRQ Vector Register
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* reads the value stored in AIC_SPU
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*/
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at91_aic_write(AT91_AIC5_SPU, spu_vector);
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/* No debugging in AIC: Debug (Protect) Control Register */
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at91_aic_write(AT91_AIC5_DCR, 0);
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/* Disable and clear all interrupts initially */
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for (i = 0; i < n_irqs; i++) {
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at91_aic_write(AT91_AIC5_SSR, i & AT91_AIC5_INTSEL_MSK);
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at91_aic_write(AT91_AIC5_IDCR, 1);
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at91_aic_write(AT91_AIC5_ICCR, 1);
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}
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}
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#if defined(CONFIG_OF)
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static unsigned int *at91_aic_irq_priorities;
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static int at91_aic_irq_map(struct irq_domain *h, unsigned int virq,
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irq_hw_number_t hw)
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{
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/* Put virq number in Source Vector Register */
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at91_aic_write(AT91_AIC_SVR(hw), virq);
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/* Active Low interrupt, with priority */
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at91_aic_write(AT91_AIC_SMR(hw),
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AT91_AIC_SRCTYPE_LOW | at91_aic_irq_priorities[hw]);
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irq_set_chip_and_handler(virq, &at91_aic_chip, handle_fasteoi_irq);
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set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
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return 0;
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}
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static int at91_aic5_irq_map(struct irq_domain *h, unsigned int virq,
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irq_hw_number_t hw)
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{
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at91_aic_write(AT91_AIC5_SSR, hw & AT91_AIC5_INTSEL_MSK);
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/* Put virq number in Source Vector Register */
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at91_aic_write(AT91_AIC5_SVR, virq);
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/* Active Low interrupt, with priority */
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at91_aic_write(AT91_AIC5_SMR,
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AT91_AIC_SRCTYPE_LOW | at91_aic_irq_priorities[hw]);
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irq_set_chip_and_handler(virq, &at91_aic_chip, handle_fasteoi_irq);
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set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
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return 0;
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}
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static int at91_aic_irq_domain_xlate(struct irq_domain *d, struct device_node *ctrlr,
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const u32 *intspec, unsigned int intsize,
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irq_hw_number_t *out_hwirq, unsigned int *out_type)
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{
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if (WARN_ON(intsize < 3))
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return -EINVAL;
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if (WARN_ON(intspec[0] >= n_irqs))
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return -EINVAL;
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if (WARN_ON((intspec[2] < AT91_AIC_IRQ_MIN_PRIORITY)
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|| (intspec[2] > AT91_AIC_IRQ_MAX_PRIORITY)))
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return -EINVAL;
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*out_hwirq = intspec[0];
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*out_type = intspec[1] & IRQ_TYPE_SENSE_MASK;
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at91_aic_irq_priorities[*out_hwirq] = intspec[2];
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return 0;
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}
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static struct irq_domain_ops at91_aic_irq_ops = {
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.map = at91_aic_irq_map,
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.xlate = at91_aic_irq_domain_xlate,
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};
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int __init at91_aic_of_common_init(struct device_node *node,
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struct device_node *parent)
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{
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struct property *prop;
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const __be32 *p;
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u32 val;
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at91_extern_irq = kzalloc(BITS_TO_LONGS(n_irqs)
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* sizeof(*at91_extern_irq), GFP_KERNEL);
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if (!at91_extern_irq)
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return -ENOMEM;
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if (at91_aic_pm_init()) {
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kfree(at91_extern_irq);
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return -ENOMEM;
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}
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at91_aic_irq_priorities = kzalloc(n_irqs
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* sizeof(*at91_aic_irq_priorities),
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GFP_KERNEL);
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if (!at91_aic_irq_priorities)
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return -ENOMEM;
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at91_aic_base = of_iomap(node, 0);
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at91_aic_np = node;
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at91_aic_domain = irq_domain_add_linear(at91_aic_np, n_irqs,
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&at91_aic_irq_ops, NULL);
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if (!at91_aic_domain)
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panic("Unable to add AIC irq domain (DT)\n");
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of_property_for_each_u32(node, "atmel,external-irqs", prop, p, val) {
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if (val >= n_irqs)
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pr_warn("AIC: external irq %d >= %d skip it\n",
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val, n_irqs);
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else
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set_bit(val, at91_extern_irq);
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}
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irq_set_default_host(at91_aic_domain);
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return 0;
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}
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int __init at91_aic_of_init(struct device_node *node,
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struct device_node *parent)
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{
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int err;
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err = at91_aic_of_common_init(node, parent);
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if (err)
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return err;
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at91_aic_hw_init(n_irqs);
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return 0;
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}
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int __init at91_aic5_of_init(struct device_node *node,
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struct device_node *parent)
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{
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int err;
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at91_aic_caps |= AT91_AIC_CAP_AIC5;
|
|
n_irqs = NR_AIC5_IRQS;
|
|
at91_aic_chip.irq_ack = at91_aic5_mask_irq;
|
|
at91_aic_chip.irq_mask = at91_aic5_mask_irq;
|
|
at91_aic_chip.irq_unmask = at91_aic5_unmask_irq;
|
|
at91_aic_chip.irq_eoi = at91_aic5_eoi;
|
|
at91_aic_irq_ops.map = at91_aic5_irq_map;
|
|
|
|
err = at91_aic_of_common_init(node, parent);
|
|
if (err)
|
|
return err;
|
|
|
|
at91_aic5_hw_init(n_irqs);
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
/*
|
|
* Initialize the AIC interrupt controller.
|
|
*/
|
|
void __init at91_aic_init(unsigned int *priority)
|
|
{
|
|
unsigned int i;
|
|
int irq_base;
|
|
|
|
if (at91_aic_pm_init())
|
|
panic("Unable to allocate bit maps\n");
|
|
|
|
at91_aic_base = ioremap(AT91_AIC, 512);
|
|
if (!at91_aic_base)
|
|
panic("Unable to ioremap AIC registers\n");
|
|
|
|
/* Add irq domain for AIC */
|
|
irq_base = irq_alloc_descs(-1, 0, n_irqs, 0);
|
|
if (irq_base < 0) {
|
|
WARN(1, "Cannot allocate irq_descs, assuming pre-allocated\n");
|
|
irq_base = 0;
|
|
}
|
|
at91_aic_domain = irq_domain_add_legacy(at91_aic_np, n_irqs,
|
|
irq_base, 0,
|
|
&irq_domain_simple_ops, NULL);
|
|
|
|
if (!at91_aic_domain)
|
|
panic("Unable to add AIC irq domain\n");
|
|
|
|
irq_set_default_host(at91_aic_domain);
|
|
|
|
/*
|
|
* The IVR is used by macro get_irqnr_and_base to read and verify.
|
|
* The irq number is NR_AIC_IRQS when a spurious interrupt has occurred.
|
|
*/
|
|
for (i = 0; i < n_irqs; i++) {
|
|
/* Put hardware irq number in Source Vector Register: */
|
|
at91_aic_write(AT91_AIC_SVR(i), NR_IRQS_LEGACY + i);
|
|
/* Active Low interrupt, with the specified priority */
|
|
at91_aic_write(AT91_AIC_SMR(i), AT91_AIC_SRCTYPE_LOW | priority[i]);
|
|
irq_set_chip_and_handler(NR_IRQS_LEGACY + i, &at91_aic_chip, handle_fasteoi_irq);
|
|
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
|
|
}
|
|
|
|
at91_aic_hw_init(n_irqs);
|
|
}
|