![Paul Walmsley](/assets/img/avatar_default.png)
Conflicts: arch/arm/mach-omap2/clkt34xx_dpll3m2.c arch/arm/mach-omap2/clkt_clksel.c arch/arm/mach-omap2/clock.c
524 lines
14 KiB
C
524 lines
14 KiB
C
/*
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* linux/arch/arm/mach-omap2/clock.c
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*
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* Copyright (C) 2005-2008 Texas Instruments, Inc.
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* Copyright (C) 2004-2010 Nokia Corporation
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*
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* Contacts:
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* Richard Woodruff <r-woodruff2@ti.com>
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* Paul Walmsley
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#undef DEBUG
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#include <linux/kernel.h>
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#include <linux/list.h>
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/delay.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/bitops.h>
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#include <asm/cpu.h>
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#include <plat/clock.h>
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#include <plat/prcm.h>
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#include <trace/events/power.h>
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#include "soc.h"
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#include "clockdomain.h"
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#include "clock.h"
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#include "cm2xxx_3xxx.h"
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#include "cm-regbits-24xx.h"
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#include "cm-regbits-34xx.h"
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u16 cpu_mask;
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/*
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* clkdm_control: if true, then when a clock is enabled in the
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* hardware, its clockdomain will first be enabled; and when a clock
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* is disabled in the hardware, its clockdomain will be disabled
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* afterwards.
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*/
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static bool clkdm_control = true;
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/*
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* OMAP2+ specific clock functions
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*/
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/* Private functions */
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/**
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* _omap2_module_wait_ready - wait for an OMAP module to leave IDLE
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* @clk: struct clk * belonging to the module
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*
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* If the necessary clocks for the OMAP hardware IP block that
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* corresponds to clock @clk are enabled, then wait for the module to
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* indicate readiness (i.e., to leave IDLE). This code does not
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* belong in the clock code and will be moved in the medium term to
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* module-dependent code. No return value.
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*/
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static void _omap2_module_wait_ready(struct clk *clk)
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{
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void __iomem *companion_reg, *idlest_reg;
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u8 other_bit, idlest_bit, idlest_val;
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/* Not all modules have multiple clocks that their IDLEST depends on */
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if (clk->ops->find_companion) {
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clk->ops->find_companion(clk, &companion_reg, &other_bit);
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if (!(__raw_readl(companion_reg) & (1 << other_bit)))
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return;
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}
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clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit, &idlest_val);
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omap2_cm_wait_idlest(idlest_reg, (1 << idlest_bit), idlest_val,
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__clk_get_name(clk));
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}
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/* Public functions */
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/**
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* omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk
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* @clk: OMAP clock struct ptr to use
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*
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* Convert a clockdomain name stored in a struct clk 'clk' into a
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* clockdomain pointer, and save it into the struct clk. Intended to be
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* called during clk_register(). No return value.
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*/
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void omap2_init_clk_clkdm(struct clk *clk)
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{
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struct clockdomain *clkdm;
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const char *clk_name;
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if (!clk->clkdm_name)
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return;
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clk_name = __clk_get_name(clk);
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clkdm = clkdm_lookup(clk->clkdm_name);
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if (clkdm) {
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pr_debug("clock: associated clk %s to clkdm %s\n",
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clk_name, clk->clkdm_name);
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clk->clkdm = clkdm;
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} else {
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pr_debug("clock: could not associate clk %s to clkdm %s\n",
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clk_name, clk->clkdm_name);
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}
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}
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/**
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* omap2_clk_disable_clkdm_control - disable clkdm control on clk enable/disable
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*
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* Prevent the OMAP clock code from calling into the clockdomain code
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* when a hardware clock in that clockdomain is enabled or disabled.
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* Intended to be called at init time from omap*_clk_init(). No
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* return value.
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*/
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void __init omap2_clk_disable_clkdm_control(void)
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{
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clkdm_control = false;
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}
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/**
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* omap2_clk_dflt_find_companion - find companion clock to @clk
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* @clk: struct clk * to find the companion clock of
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* @other_reg: void __iomem ** to return the companion clock CM_*CLKEN va in
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* @other_bit: u8 ** to return the companion clock bit shift in
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*
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* Note: We don't need special code here for INVERT_ENABLE for the
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* time being since INVERT_ENABLE only applies to clocks enabled by
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* CM_CLKEN_PLL
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*
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* Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes it's
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* just a matter of XORing the bits.
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*
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* Some clocks don't have companion clocks. For example, modules with
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* only an interface clock (such as MAILBOXES) don't have a companion
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* clock. Right now, this code relies on the hardware exporting a bit
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* in the correct companion register that indicates that the
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* nonexistent 'companion clock' is active. Future patches will
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* associate this type of code with per-module data structures to
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* avoid this issue, and remove the casts. No return value.
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*/
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void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg,
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u8 *other_bit)
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{
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u32 r;
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/*
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* Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes
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* it's just a matter of XORing the bits.
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*/
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r = ((__force u32)clk->enable_reg ^ (CM_FCLKEN ^ CM_ICLKEN));
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*other_reg = (__force void __iomem *)r;
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*other_bit = clk->enable_bit;
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}
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/**
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* omap2_clk_dflt_find_idlest - find CM_IDLEST reg va, bit shift for @clk
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* @clk: struct clk * to find IDLEST info for
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* @idlest_reg: void __iomem ** to return the CM_IDLEST va in
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* @idlest_bit: u8 * to return the CM_IDLEST bit shift in
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* @idlest_val: u8 * to return the idle status indicator
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*
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* Return the CM_IDLEST register address and bit shift corresponding
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* to the module that "owns" this clock. This default code assumes
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* that the CM_IDLEST bit shift is the CM_*CLKEN bit shift, and that
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* the IDLEST register address ID corresponds to the CM_*CLKEN
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* register address ID (e.g., that CM_FCLKEN2 corresponds to
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* CM_IDLEST2). This is not true for all modules. No return value.
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*/
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void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg,
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u8 *idlest_bit, u8 *idlest_val)
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{
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u32 r;
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r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
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*idlest_reg = (__force void __iomem *)r;
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*idlest_bit = clk->enable_bit;
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/*
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* 24xx uses 0 to indicate not ready, and 1 to indicate ready.
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* 34xx reverses this, just to keep us on our toes
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* AM35xx uses both, depending on the module.
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*/
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if (cpu_is_omap24xx())
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*idlest_val = OMAP24XX_CM_IDLEST_VAL;
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else if (cpu_is_omap34xx())
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*idlest_val = OMAP34XX_CM_IDLEST_VAL;
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else
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BUG();
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}
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int omap2_dflt_clk_enable(struct clk *clk)
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{
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u32 v;
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if (unlikely(clk->enable_reg == NULL)) {
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pr_err("clock.c: Enable for %s without enable code\n",
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clk->name);
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return 0; /* REVISIT: -EINVAL */
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}
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v = __raw_readl(clk->enable_reg);
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if (clk->flags & INVERT_ENABLE)
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v &= ~(1 << clk->enable_bit);
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else
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v |= (1 << clk->enable_bit);
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__raw_writel(v, clk->enable_reg);
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v = __raw_readl(clk->enable_reg); /* OCP barrier */
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if (clk->ops->find_idlest)
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_omap2_module_wait_ready(clk);
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return 0;
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}
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void omap2_dflt_clk_disable(struct clk *clk)
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{
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u32 v;
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if (!clk->enable_reg) {
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/*
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* 'Independent' here refers to a clock which is not
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* controlled by its parent.
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*/
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pr_err("clock: clk_disable called on independent clock %s which has no enable_reg\n", clk->name);
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return;
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}
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v = __raw_readl(clk->enable_reg);
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if (clk->flags & INVERT_ENABLE)
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v |= (1 << clk->enable_bit);
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else
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v &= ~(1 << clk->enable_bit);
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__raw_writel(v, clk->enable_reg);
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/* No OCP barrier needed here since it is a disable operation */
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}
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const struct clkops clkops_omap2_dflt_wait = {
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.enable = omap2_dflt_clk_enable,
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.disable = omap2_dflt_clk_disable,
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.find_companion = omap2_clk_dflt_find_companion,
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.find_idlest = omap2_clk_dflt_find_idlest,
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};
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const struct clkops clkops_omap2_dflt = {
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.enable = omap2_dflt_clk_enable,
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.disable = omap2_dflt_clk_disable,
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};
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/**
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* omap2_clk_disable - disable a clock, if the system is not using it
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* @clk: struct clk * to disable
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*
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* Decrements the usecount on struct clk @clk. If there are no users
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* left, call the clkops-specific clock disable function to disable it
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* in hardware. If the clock is part of a clockdomain (which they all
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* should be), request that the clockdomain be disabled. (It too has
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* a usecount, and so will not be disabled in the hardware until it no
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* longer has any users.) If the clock has a parent clock (most of
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* them do), then call ourselves, recursing on the parent clock. This
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* can cause an entire branch of the clock tree to be powered off by
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* simply disabling one clock. Intended to be called with the clockfw_lock
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* spinlock held. No return value.
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*/
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void omap2_clk_disable(struct clk *clk)
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{
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if (clk->usecount == 0) {
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WARN(1, "clock: %s: omap2_clk_disable() called, but usecount already 0?", clk->name);
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return;
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}
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pr_debug("clock: %s: decrementing usecount\n", clk->name);
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clk->usecount--;
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if (clk->usecount > 0)
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return;
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pr_debug("clock: %s: disabling in hardware\n", clk->name);
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if (clk->ops && clk->ops->disable) {
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trace_clock_disable(clk->name, 0, smp_processor_id());
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clk->ops->disable(clk);
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}
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if (clkdm_control && clk->clkdm)
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clkdm_clk_disable(clk->clkdm, clk);
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if (clk->parent)
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omap2_clk_disable(clk->parent);
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}
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/**
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* omap2_clk_enable - request that the system enable a clock
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* @clk: struct clk * to enable
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*
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* Increments the usecount on struct clk @clk. If there were no users
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* previously, then recurse up the clock tree, enabling all of the
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* clock's parents and all of the parent clockdomains, and finally,
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* enabling @clk's clockdomain, and @clk itself. Intended to be
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* called with the clockfw_lock spinlock held. Returns 0 upon success
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* or a negative error code upon failure.
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*/
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int omap2_clk_enable(struct clk *clk)
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{
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int ret;
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pr_debug("clock: %s: incrementing usecount\n", clk->name);
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clk->usecount++;
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if (clk->usecount > 1)
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return 0;
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pr_debug("clock: %s: enabling in hardware\n", clk->name);
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if (clk->parent) {
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ret = omap2_clk_enable(clk->parent);
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if (ret) {
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WARN(1, "clock: %s: could not enable parent %s: %d\n",
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clk->name, clk->parent->name, ret);
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goto oce_err1;
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}
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}
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if (clkdm_control && clk->clkdm) {
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ret = clkdm_clk_enable(clk->clkdm, clk);
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if (ret) {
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WARN(1, "clock: %s: could not enable clockdomain %s: %d\n",
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clk->name, clk->clkdm->name, ret);
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goto oce_err2;
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}
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}
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if (clk->ops && clk->ops->enable) {
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trace_clock_enable(clk->name, 1, smp_processor_id());
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ret = clk->ops->enable(clk);
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if (ret) {
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WARN(1, "clock: %s: could not enable: %d\n",
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clk->name, ret);
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goto oce_err3;
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}
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}
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return 0;
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oce_err3:
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if (clkdm_control && clk->clkdm)
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clkdm_clk_disable(clk->clkdm, clk);
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oce_err2:
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if (clk->parent)
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omap2_clk_disable(clk->parent);
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oce_err1:
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clk->usecount--;
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return ret;
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}
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/* Given a clock and a rate apply a clock specific rounding function */
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long omap2_clk_round_rate(struct clk *clk, unsigned long rate)
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{
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if (clk->round_rate)
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return clk->round_rate(clk, rate);
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return clk->rate;
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}
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/* Set the clock rate for a clock source */
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int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
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{
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int ret = -EINVAL;
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pr_debug("clock: set_rate for clock %s to rate %ld\n", clk->name, rate);
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/* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */
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if (clk->set_rate) {
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trace_clock_set_rate(clk->name, rate, smp_processor_id());
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ret = clk->set_rate(clk, rate);
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}
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return ret;
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}
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int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
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{
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if (!clk->clksel)
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return -EINVAL;
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if (clk->parent == new_parent)
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return 0;
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return omap2_clksel_set_parent(clk, new_parent);
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}
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/*
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* OMAP2+ clock reset and init functions
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*/
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#ifdef CONFIG_OMAP_RESET_CLOCKS
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void omap2_clk_disable_unused(struct clk *clk)
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{
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u32 regval32, v;
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v = (clk->flags & INVERT_ENABLE) ? (1 << clk->enable_bit) : 0;
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regval32 = __raw_readl(clk->enable_reg);
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if ((regval32 & (1 << clk->enable_bit)) == v)
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return;
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pr_debug("Disabling unused clock \"%s\"\n", clk->name);
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if (cpu_is_omap34xx()) {
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omap2_clk_enable(clk);
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omap2_clk_disable(clk);
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} else {
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clk->ops->disable(clk);
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}
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if (clk->clkdm != NULL)
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pwrdm_state_switch(clk->clkdm->pwrdm.ptr);
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}
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#endif
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/**
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* omap2_clk_switch_mpurate_at_boot - switch ARM MPU rate by boot-time argument
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* @mpurate_ck_name: clk name of the clock to change rate
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*
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* Change the ARM MPU clock rate to the rate specified on the command
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* line, if one was specified. @mpurate_ck_name should be
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* "virt_prcm_set" on OMAP2xxx and "dpll1_ck" on OMAP34xx/OMAP36xx.
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* XXX Does not handle voltage scaling - on OMAP2xxx this is currently
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* handled by the virt_prcm_set clock, but this should be handled by
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* the OPP layer. XXX This is intended to be handled by the OPP layer
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* code in the near future and should be removed from the clock code.
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* Returns -EINVAL if 'mpurate' is zero or if clk_set_rate() rejects
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* the rate, -ENOENT if the struct clk referred to by @mpurate_ck_name
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* cannot be found, or 0 upon success.
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*/
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int __init omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name)
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{
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struct clk *mpurate_ck;
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int r;
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if (!mpurate)
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return -EINVAL;
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mpurate_ck = clk_get(NULL, mpurate_ck_name);
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if (WARN(IS_ERR(mpurate_ck), "Failed to get %s.\n", mpurate_ck_name))
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return -ENOENT;
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r = clk_set_rate(mpurate_ck, mpurate);
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if (IS_ERR_VALUE(r)) {
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WARN(1, "clock: %s: unable to set MPU rate to %d: %d\n",
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mpurate_ck->name, mpurate, r);
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clk_put(mpurate_ck);
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return -EINVAL;
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}
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calibrate_delay();
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recalculate_root_clocks();
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clk_put(mpurate_ck);
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return 0;
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}
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/**
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* omap2_clk_print_new_rates - print summary of current clock tree rates
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* @hfclkin_ck_name: clk name for the off-chip HF oscillator
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* @core_ck_name: clk name for the on-chip CORE_CLK
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* @mpu_ck_name: clk name for the ARM MPU clock
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*
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* Prints a short message to the console with the HFCLKIN oscillator
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* rate, the rate of the CORE clock, and the rate of the ARM MPU clock.
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* Called by the boot-time MPU rate switching code. XXX This is intended
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* to be handled by the OPP layer code in the near future and should be
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* removed from the clock code. No return value.
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*/
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void __init omap2_clk_print_new_rates(const char *hfclkin_ck_name,
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const char *core_ck_name,
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const char *mpu_ck_name)
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{
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struct clk *hfclkin_ck, *core_ck, *mpu_ck;
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unsigned long hfclkin_rate;
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|
|
|
mpu_ck = clk_get(NULL, mpu_ck_name);
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if (WARN(IS_ERR(mpu_ck), "clock: failed to get %s.\n", mpu_ck_name))
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|
return;
|
|
|
|
core_ck = clk_get(NULL, core_ck_name);
|
|
if (WARN(IS_ERR(core_ck), "clock: failed to get %s.\n", core_ck_name))
|
|
return;
|
|
|
|
hfclkin_ck = clk_get(NULL, hfclkin_ck_name);
|
|
if (WARN(IS_ERR(hfclkin_ck), "Failed to get %s.\n", hfclkin_ck_name))
|
|
return;
|
|
|
|
hfclkin_rate = clk_get_rate(hfclkin_ck);
|
|
|
|
pr_info("Switched to new clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n",
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|
(hfclkin_rate / 1000000), ((hfclkin_rate / 100000) % 10),
|
|
(clk_get_rate(core_ck) / 1000000),
|
|
(clk_get_rate(mpu_ck) / 1000000));
|
|
}
|
|
|
|
/* Common data */
|
|
|
|
struct clk_functions omap2_clk_functions = {
|
|
.clk_enable = omap2_clk_enable,
|
|
.clk_disable = omap2_clk_disable,
|
|
.clk_round_rate = omap2_clk_round_rate,
|
|
.clk_set_rate = omap2_clk_set_rate,
|
|
.clk_set_parent = omap2_clk_set_parent,
|
|
.clk_disable_unused = omap2_clk_disable_unused,
|
|
};
|
|
|