![Linus Torvalds](/assets/img/avatar_default.png)
It includes: - large updates for OMAP - basic OMAP5 DSS support for DPI and DSI outputs - large cleanups and restructuring - some update to Exynos and da8xx-fb - removal of the pnx4008 driver (arch removed) - various other small patches -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.12 (GNU/Linux) iQIcBAABAgAGBQJQdz+EAAoJECSVL5KnPj1PyiMP/R84rSfGUbDIh0Cr6g1Snk76 h2/1i19TuEgJAWH1q0lnwhqMC3yYmkA1Hz3ulT35KS+/L3IEgUosOESrxZIJhxHI f55pk3v8dueN0rx3OhCknLT7hGpVsI4vSN+3yf9LetDp3qt8UVwKLFzVij1VF/MS b1wA+RBe1IYMR0bB6pK0AgMZZiBkQMta5rKs5IfDDi8kMgMT4+V8l/iFmt2Ue833 VxdPw+3reKshBXKTkQt1Usv4JRtG7OgwpRmFhxOo+ag0dxPLeUe/3wZG54qfOywF 7jK+mnxmW8oZxLkGBvygrmzd40MH6H09N7i/IKVQ0GZoHgAqWWe7VvWahpg8LzwB ynktwWZ3Va98p5u/BIafBr0ZOU30mPL8N0aqR3HU7H12Wq21HtwcF+ewiT4vnMc8 CKzt6VL0qY1tOOdzJzmICzvXGkbBGfj9YOUptJALCIa3bLwZodyQ/bKq8V/bHdTg 2yyUmVhVf/r5qLermjQN8TjFMpRf2SNwTUUYvhUNwZ4yZMVWZgjjhtAlGGFCA/Bs qMRuNpbHMedhzNV4py418Xe3Hwg6TLPuWSWGJ67SG8hxsYy2hq7GebSsXXdC7xG9 N5DMpA88IQR2nLwkr/pslFqjRsUI6ULvIfxibHEoNjQ0GOY9f+hEWbdHBZPI+0Gv Ea9d7nyhmYTZgvRcd9U0 =EJUS -----END PGP SIGNATURE----- Merge tag 'fbdev-updates-for-3.7' of git://github.com/schandinat/linux-2.6 Pull fbdev updates from Florian Tobias Schandinat: "This includes: - large updates for OMAP - basic OMAP5 DSS support for DPI and DSI outputs - large cleanups and restructuring - some update to Exynos and da8xx-fb - removal of the pnx4008 driver (arch removed) - various other small patches" Fix up some trivial conflicts (mostly just include line changes, but also some due to the renaming of the deferred work functions by Tejun). * tag 'fbdev-updates-for-3.7' of git://github.com/schandinat/linux-2.6: (193 commits) gbefb: fix compile error video: mark nuc900fb_map_video_memory as __devinit video/mx3fb: set .owner to prevent module unloading while being used video: exynos_dp: use clk_prepare_enable and clk_disable_unprepare drivers/video/exynos/exynos_mipi_dsi.c: fix error return code drivers/video/savage/savagefb_driver.c: fix error return code video: s3c-fb: use clk_prepare_enable and clk_disable_unprepare da8xx-fb: save and restore LCDC context across suspend/resume cycle da8xx-fb: add pm_runtime support video/udlfb: fix line counting in fb_write OMAPDSS: add missing include for string.h OMAPDSS: DISPC: Configure color conversion coefficients for writeback OMAPDSS: DISPC: Add manager like functions for writeback OMAPDSS: DISPC: Configure writeback FIFOs OMAPDSS: DISPC: Configure writeback specific parameters in dispc_wb_setup() OMAPDSS: DISPC: Configure overlay-like parameters in dispc_wb_setup OMAPDSS: DISPC: Add function to set channel in for writeback OMAPDSS: DISPC: Don't set chroma resampling bit for writeback OMAPDSS: DISPC: Downscale chroma if plane is writeback OMAPDSS: DISPC: Configure input and output sizes for writeback ...
523 lines
13 KiB
C
523 lines
13 KiB
C
/*
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* OMAP2plus display device setup / initialization.
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*
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* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
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* Senthilvadivu Guruswamy
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* Sumit Semwal
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/string.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/delay.h>
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#include <video/omapdss.h>
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#include <plat/omap_hwmod.h>
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#include <plat/omap_device.h>
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#include <plat/omap-pm.h>
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#include "common.h"
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#include "iomap.h"
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#include "mux.h"
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#include "control.h"
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#include "display.h"
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#define DISPC_CONTROL 0x0040
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#define DISPC_CONTROL2 0x0238
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#define DISPC_CONTROL3 0x0848
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#define DISPC_IRQSTATUS 0x0018
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#define DSS_SYSCONFIG 0x10
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#define DSS_SYSSTATUS 0x14
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#define DSS_CONTROL 0x40
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#define DSS_SDI_CONTROL 0x44
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#define DSS_PLL_CONTROL 0x48
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#define LCD_EN_MASK (0x1 << 0)
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#define DIGIT_EN_MASK (0x1 << 1)
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#define FRAMEDONE_IRQ_SHIFT 0
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#define EVSYNC_EVEN_IRQ_SHIFT 2
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#define EVSYNC_ODD_IRQ_SHIFT 3
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#define FRAMEDONE2_IRQ_SHIFT 22
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#define FRAMEDONE3_IRQ_SHIFT 30
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#define FRAMEDONETV_IRQ_SHIFT 24
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/*
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* FRAMEDONE_IRQ_TIMEOUT: how long (in milliseconds) to wait during DISPC
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* reset before deciding that something has gone wrong
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*/
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#define FRAMEDONE_IRQ_TIMEOUT 100
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static struct platform_device omap_display_device = {
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.name = "omapdss",
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.id = -1,
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.dev = {
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.platform_data = NULL,
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},
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};
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struct omap_dss_hwmod_data {
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const char *oh_name;
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const char *dev_name;
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const int id;
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};
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static const struct omap_dss_hwmod_data omap2_dss_hwmod_data[] __initconst = {
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{ "dss_core", "omapdss_dss", -1 },
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{ "dss_dispc", "omapdss_dispc", -1 },
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{ "dss_rfbi", "omapdss_rfbi", -1 },
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{ "dss_venc", "omapdss_venc", -1 },
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};
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static const struct omap_dss_hwmod_data omap3_dss_hwmod_data[] __initconst = {
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{ "dss_core", "omapdss_dss", -1 },
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{ "dss_dispc", "omapdss_dispc", -1 },
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{ "dss_rfbi", "omapdss_rfbi", -1 },
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{ "dss_venc", "omapdss_venc", -1 },
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{ "dss_dsi1", "omapdss_dsi", 0 },
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};
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static const struct omap_dss_hwmod_data omap4_dss_hwmod_data[] __initconst = {
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{ "dss_core", "omapdss_dss", -1 },
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{ "dss_dispc", "omapdss_dispc", -1 },
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{ "dss_rfbi", "omapdss_rfbi", -1 },
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{ "dss_dsi1", "omapdss_dsi", 0 },
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{ "dss_dsi2", "omapdss_dsi", 1 },
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{ "dss_hdmi", "omapdss_hdmi", -1 },
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};
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static void __init omap4_hdmi_mux_pads(enum omap_hdmi_flags flags)
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{
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u32 reg;
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u16 control_i2c_1;
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omap_mux_init_signal("hdmi_cec",
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OMAP_PIN_INPUT_PULLUP);
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omap_mux_init_signal("hdmi_ddc_scl",
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OMAP_PIN_INPUT_PULLUP);
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omap_mux_init_signal("hdmi_ddc_sda",
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OMAP_PIN_INPUT_PULLUP);
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/*
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* CONTROL_I2C_1: HDMI_DDC_SDA_PULLUPRESX (bit 28) and
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* HDMI_DDC_SCL_PULLUPRESX (bit 24) are set to disable
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* internal pull up resistor.
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*/
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if (flags & OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP) {
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control_i2c_1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_1;
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reg = omap4_ctrl_pad_readl(control_i2c_1);
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reg |= (OMAP4_HDMI_DDC_SDA_PULLUPRESX_MASK |
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OMAP4_HDMI_DDC_SCL_PULLUPRESX_MASK);
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omap4_ctrl_pad_writel(reg, control_i2c_1);
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}
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}
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static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes)
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{
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u32 enable_mask, enable_shift;
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u32 pipd_mask, pipd_shift;
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u32 reg;
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if (dsi_id == 0) {
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enable_mask = OMAP4_DSI1_LANEENABLE_MASK;
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enable_shift = OMAP4_DSI1_LANEENABLE_SHIFT;
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pipd_mask = OMAP4_DSI1_PIPD_MASK;
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pipd_shift = OMAP4_DSI1_PIPD_SHIFT;
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} else if (dsi_id == 1) {
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enable_mask = OMAP4_DSI2_LANEENABLE_MASK;
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enable_shift = OMAP4_DSI2_LANEENABLE_SHIFT;
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pipd_mask = OMAP4_DSI2_PIPD_MASK;
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pipd_shift = OMAP4_DSI2_PIPD_SHIFT;
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} else {
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return -ENODEV;
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}
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reg = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY);
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reg &= ~enable_mask;
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reg &= ~pipd_mask;
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reg |= (lanes << enable_shift) & enable_mask;
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reg |= (lanes << pipd_shift) & pipd_mask;
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omap4_ctrl_pad_writel(reg, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY);
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return 0;
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}
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int __init omap_hdmi_init(enum omap_hdmi_flags flags)
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{
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if (cpu_is_omap44xx())
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omap4_hdmi_mux_pads(flags);
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return 0;
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}
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static int omap_dsi_enable_pads(int dsi_id, unsigned lane_mask)
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{
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if (cpu_is_omap44xx())
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return omap4_dsi_mux_pads(dsi_id, lane_mask);
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return 0;
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}
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static void omap_dsi_disable_pads(int dsi_id, unsigned lane_mask)
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{
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if (cpu_is_omap44xx())
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omap4_dsi_mux_pads(dsi_id, 0);
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}
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static int omap_dss_set_min_bus_tput(struct device *dev, unsigned long tput)
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{
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return omap_pm_set_min_bus_tput(dev, OCP_INITIATOR_AGENT, tput);
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}
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static struct platform_device *create_dss_pdev(const char *pdev_name,
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int pdev_id, const char *oh_name, void *pdata, int pdata_len,
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struct platform_device *parent)
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{
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struct platform_device *pdev;
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struct omap_device *od;
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struct omap_hwmod *ohs[1];
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struct omap_hwmod *oh;
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int r;
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oh = omap_hwmod_lookup(oh_name);
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if (!oh) {
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pr_err("Could not look up %s\n", oh_name);
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r = -ENODEV;
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goto err;
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}
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pdev = platform_device_alloc(pdev_name, pdev_id);
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if (!pdev) {
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pr_err("Could not create pdev for %s\n", pdev_name);
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r = -ENOMEM;
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goto err;
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}
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if (parent != NULL)
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pdev->dev.parent = &parent->dev;
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if (pdev->id != -1)
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dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id);
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else
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dev_set_name(&pdev->dev, "%s", pdev->name);
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ohs[0] = oh;
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od = omap_device_alloc(pdev, ohs, 1, NULL, 0);
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if (IS_ERR(od)) {
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pr_err("Could not alloc omap_device for %s\n", pdev_name);
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r = -ENOMEM;
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goto err;
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}
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r = platform_device_add_data(pdev, pdata, pdata_len);
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if (r) {
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pr_err("Could not set pdata for %s\n", pdev_name);
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goto err;
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}
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r = omap_device_register(pdev);
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if (r) {
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pr_err("Could not register omap_device for %s\n", pdev_name);
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goto err;
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}
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return pdev;
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err:
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return ERR_PTR(r);
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}
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static struct platform_device *create_simple_dss_pdev(const char *pdev_name,
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int pdev_id, void *pdata, int pdata_len,
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struct platform_device *parent)
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{
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struct platform_device *pdev;
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int r;
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pdev = platform_device_alloc(pdev_name, pdev_id);
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if (!pdev) {
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pr_err("Could not create pdev for %s\n", pdev_name);
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r = -ENOMEM;
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goto err;
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}
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if (parent != NULL)
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pdev->dev.parent = &parent->dev;
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if (pdev->id != -1)
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dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id);
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else
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dev_set_name(&pdev->dev, "%s", pdev->name);
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r = platform_device_add_data(pdev, pdata, pdata_len);
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if (r) {
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pr_err("Could not set pdata for %s\n", pdev_name);
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goto err;
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}
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r = platform_device_add(pdev);
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if (r) {
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pr_err("Could not register platform_device for %s\n", pdev_name);
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goto err;
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}
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return pdev;
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err:
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return ERR_PTR(r);
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}
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int __init omap_display_init(struct omap_dss_board_info *board_data)
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{
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int r = 0;
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struct platform_device *pdev;
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int i, oh_count;
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const struct omap_dss_hwmod_data *curr_dss_hwmod;
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struct platform_device *dss_pdev;
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/* create omapdss device */
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board_data->dsi_enable_pads = omap_dsi_enable_pads;
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board_data->dsi_disable_pads = omap_dsi_disable_pads;
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board_data->get_context_loss_count = omap_pm_get_dev_context_loss_count;
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board_data->set_min_bus_tput = omap_dss_set_min_bus_tput;
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omap_display_device.dev.platform_data = board_data;
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r = platform_device_register(&omap_display_device);
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if (r < 0) {
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pr_err("Unable to register omapdss device\n");
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return r;
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}
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/* create devices for dss hwmods */
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if (cpu_is_omap24xx()) {
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curr_dss_hwmod = omap2_dss_hwmod_data;
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oh_count = ARRAY_SIZE(omap2_dss_hwmod_data);
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} else if (cpu_is_omap34xx()) {
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curr_dss_hwmod = omap3_dss_hwmod_data;
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oh_count = ARRAY_SIZE(omap3_dss_hwmod_data);
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} else {
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curr_dss_hwmod = omap4_dss_hwmod_data;
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oh_count = ARRAY_SIZE(omap4_dss_hwmod_data);
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}
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/*
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* First create the pdev for dss_core, which is used as a parent device
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* by the other dss pdevs. Note: dss_core has to be the first item in
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* the hwmod list.
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*/
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dss_pdev = create_dss_pdev(curr_dss_hwmod[0].dev_name,
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curr_dss_hwmod[0].id,
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curr_dss_hwmod[0].oh_name,
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board_data, sizeof(*board_data),
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NULL);
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if (IS_ERR(dss_pdev)) {
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pr_err("Could not build omap_device for %s\n",
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curr_dss_hwmod[0].oh_name);
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return PTR_ERR(dss_pdev);
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}
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for (i = 1; i < oh_count; i++) {
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pdev = create_dss_pdev(curr_dss_hwmod[i].dev_name,
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curr_dss_hwmod[i].id,
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curr_dss_hwmod[i].oh_name,
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board_data, sizeof(*board_data),
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dss_pdev);
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if (IS_ERR(pdev)) {
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pr_err("Could not build omap_device for %s\n",
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curr_dss_hwmod[i].oh_name);
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return PTR_ERR(pdev);
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}
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}
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/* Create devices for DPI and SDI */
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pdev = create_simple_dss_pdev("omapdss_dpi", -1,
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board_data, sizeof(*board_data), dss_pdev);
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if (IS_ERR(pdev)) {
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pr_err("Could not build platform_device for omapdss_dpi\n");
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return PTR_ERR(pdev);
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}
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if (cpu_is_omap34xx()) {
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pdev = create_simple_dss_pdev("omapdss_sdi", -1,
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board_data, sizeof(*board_data), dss_pdev);
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if (IS_ERR(pdev)) {
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pr_err("Could not build platform_device for omapdss_sdi\n");
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return PTR_ERR(pdev);
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}
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}
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return 0;
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}
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static void dispc_disable_outputs(void)
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{
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u32 v, irq_mask = 0;
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bool lcd_en, digit_en, lcd2_en = false, lcd3_en = false;
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int i;
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struct omap_dss_dispc_dev_attr *da;
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struct omap_hwmod *oh;
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oh = omap_hwmod_lookup("dss_dispc");
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if (!oh) {
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WARN(1, "display: could not disable outputs during reset - could not find dss_dispc hwmod\n");
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return;
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}
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if (!oh->dev_attr) {
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pr_err("display: could not disable outputs during reset due to missing dev_attr\n");
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return;
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}
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da = (struct omap_dss_dispc_dev_attr *)oh->dev_attr;
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/* store value of LCDENABLE and DIGITENABLE bits */
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v = omap_hwmod_read(oh, DISPC_CONTROL);
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lcd_en = v & LCD_EN_MASK;
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digit_en = v & DIGIT_EN_MASK;
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/* store value of LCDENABLE for LCD2 */
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if (da->manager_count > 2) {
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v = omap_hwmod_read(oh, DISPC_CONTROL2);
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lcd2_en = v & LCD_EN_MASK;
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}
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/* store value of LCDENABLE for LCD3 */
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if (da->manager_count > 3) {
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v = omap_hwmod_read(oh, DISPC_CONTROL3);
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lcd3_en = v & LCD_EN_MASK;
|
|
}
|
|
|
|
if (!(lcd_en | digit_en | lcd2_en | lcd3_en))
|
|
return; /* no managers currently enabled */
|
|
|
|
/*
|
|
* If any manager was enabled, we need to disable it before
|
|
* DSS clocks are disabled or DISPC module is reset
|
|
*/
|
|
if (lcd_en)
|
|
irq_mask |= 1 << FRAMEDONE_IRQ_SHIFT;
|
|
|
|
if (digit_en) {
|
|
if (da->has_framedonetv_irq) {
|
|
irq_mask |= 1 << FRAMEDONETV_IRQ_SHIFT;
|
|
} else {
|
|
irq_mask |= 1 << EVSYNC_EVEN_IRQ_SHIFT |
|
|
1 << EVSYNC_ODD_IRQ_SHIFT;
|
|
}
|
|
}
|
|
|
|
if (lcd2_en)
|
|
irq_mask |= 1 << FRAMEDONE2_IRQ_SHIFT;
|
|
if (lcd3_en)
|
|
irq_mask |= 1 << FRAMEDONE3_IRQ_SHIFT;
|
|
|
|
/*
|
|
* clear any previous FRAMEDONE, FRAMEDONETV,
|
|
* EVSYNC_EVEN/ODD, FRAMEDONE2 or FRAMEDONE3 interrupts
|
|
*/
|
|
omap_hwmod_write(irq_mask, oh, DISPC_IRQSTATUS);
|
|
|
|
/* disable LCD and TV managers */
|
|
v = omap_hwmod_read(oh, DISPC_CONTROL);
|
|
v &= ~(LCD_EN_MASK | DIGIT_EN_MASK);
|
|
omap_hwmod_write(v, oh, DISPC_CONTROL);
|
|
|
|
/* disable LCD2 manager */
|
|
if (da->manager_count > 2) {
|
|
v = omap_hwmod_read(oh, DISPC_CONTROL2);
|
|
v &= ~LCD_EN_MASK;
|
|
omap_hwmod_write(v, oh, DISPC_CONTROL2);
|
|
}
|
|
|
|
/* disable LCD3 manager */
|
|
if (da->manager_count > 3) {
|
|
v = omap_hwmod_read(oh, DISPC_CONTROL3);
|
|
v &= ~LCD_EN_MASK;
|
|
omap_hwmod_write(v, oh, DISPC_CONTROL3);
|
|
}
|
|
|
|
i = 0;
|
|
while ((omap_hwmod_read(oh, DISPC_IRQSTATUS) & irq_mask) !=
|
|
irq_mask) {
|
|
i++;
|
|
if (i > FRAMEDONE_IRQ_TIMEOUT) {
|
|
pr_err("didn't get FRAMEDONE1/2/3 or TV interrupt\n");
|
|
break;
|
|
}
|
|
mdelay(1);
|
|
}
|
|
}
|
|
|
|
#define MAX_MODULE_SOFTRESET_WAIT 10000
|
|
int omap_dss_reset(struct omap_hwmod *oh)
|
|
{
|
|
struct omap_hwmod_opt_clk *oc;
|
|
int c = 0;
|
|
int i, r;
|
|
|
|
if (!(oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS)) {
|
|
pr_err("dss_core: hwmod data doesn't contain reset data\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
|
|
if (oc->_clk)
|
|
clk_prepare_enable(oc->_clk);
|
|
|
|
dispc_disable_outputs();
|
|
|
|
/* clear SDI registers */
|
|
if (cpu_is_omap3430()) {
|
|
omap_hwmod_write(0x0, oh, DSS_SDI_CONTROL);
|
|
omap_hwmod_write(0x0, oh, DSS_PLL_CONTROL);
|
|
}
|
|
|
|
/*
|
|
* clear DSS_CONTROL register to switch DSS clock sources to
|
|
* PRCM clock, if any
|
|
*/
|
|
omap_hwmod_write(0x0, oh, DSS_CONTROL);
|
|
|
|
omap_test_timeout((omap_hwmod_read(oh, oh->class->sysc->syss_offs)
|
|
& SYSS_RESETDONE_MASK),
|
|
MAX_MODULE_SOFTRESET_WAIT, c);
|
|
|
|
if (c == MAX_MODULE_SOFTRESET_WAIT)
|
|
pr_warning("dss_core: waiting for reset to finish failed\n");
|
|
else
|
|
pr_debug("dss_core: softreset done\n");
|
|
|
|
for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
|
|
if (oc->_clk)
|
|
clk_disable_unprepare(oc->_clk);
|
|
|
|
r = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0;
|
|
|
|
return r;
|
|
}
|