![Tony Lindgren](/assets/img/avatar_default.png)
These changes fix some of the more meaningful warnings that smatch returns for the OMAP subarch code, and unwraps strings that are wrapped at the 80-column boundary, to conform with the current practice. Basic build, boot, and PM logs are available here: http://www.pwsan.com/omap/testlogs/warnings_a_cleanup_3.7/20120912025927/ -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQIcBAABAgAGBQJQUKL1AAoJEMePsQ0LvSpL+a8QAJlJR9uwqUKu60GfbQEeegce k6pr0xXYvHEmbro/v6O4ezs2o716EBgwBWnId97oOZvVnwhPbEHR87UH8FFOIWOQ +/ui5MxXtYWNjYcDOzdF95reFM1szAAxQu8k9wXg+WBtZ4zCkhknpoftShRbOdg0 BgO0r1iY/wuoFaYgGFKSNdObPVgSTENjbtg/LVvB/V3PQjYmUBosJVH0tPO/LQio pWhozfFuiWbARYxPg6dMOn8yQ5mCeWErpv4WZjM+dgcrkLYyPdI2uUS3Ka8F7Az2 ImC+k0gU6WwkjyKqv/SG2wg5+3Sh8ZZsX0EKXwq0gQEmLWacENS1ELRT3+HcxGru HoAhE46URb4NGzBt7rkIkGg0HcajfORDtZSrGfsEclDmrVV5+JgUzC+PEDiwSxVU LqpJIZ8lxjqBNPSlmXqtEgTG32M6E9fDII8JdGC64vUv+vXzuhpJCXF78I8+A+Hv oSBbTOCzYGz1xp06G6Hzadpo5I1LocBRemsnhw2O9oNDdUZxiGo/qJcWfk2wpMQ6 4c/kHbYEsJ6/7eVe5kNtdkeptAXp1AFO5XIhQpSAs1O1Rr++nDNahaUJA56xev8x GoEZCYLGMGpQnINW6g0Srzwp8n1ywSgt3Gt2fbDTAP+Q02DPT3IIWWs4LlIDIrjZ w0q1kAp1+In5is3pxJvT =ythb -----END PGP SIGNATURE----- Merge tag 'omap-cleanup-b-for-3.7' of git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into cleanup-makefile-sparse smatch and string-wrapping cleanups for the OMAP subarch code. These changes fix some of the more meaningful warnings that smatch returns for the OMAP subarch code, and unwraps strings that are wrapped at the 80-column boundary, to conform with the current practice. Basic build, boot, and PM logs are available here: http://www.pwsan.com/omap/testlogs/warnings_a_cleanup_3.7/20120912025927/
189 lines
5.4 KiB
C
189 lines
5.4 KiB
C
/*
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* linux/arch/arm/mach-omap2/prcm.c
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*
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* OMAP 24xx Power Reset and Clock Management (PRCM) functions
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*
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* Copyright (C) 2005 Nokia Corporation
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*
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* Written by Tony Lindgren <tony.lindgren@nokia.com>
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*
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* Copyright (C) 2007 Texas Instruments, Inc.
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* Rajendra Nayak <rnayak@ti.com>
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*
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* Some pieces of code Copyright (C) 2005 Texas Instruments, Inc.
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* Upgraded with OMAP4 support by Abhijit Pagare <abhijitpagare@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/delay.h>
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#include <linux/export.h>
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#include "common.h"
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#include <plat/prcm.h>
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#include "clock.h"
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#include "clock2xxx.h"
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#include "cm2xxx_3xxx.h"
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#include "prm2xxx_3xxx.h"
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#include "prm44xx.h"
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#include "prminst44xx.h"
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#include "cminst44xx.h"
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#include "prm-regbits-24xx.h"
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#include "prm-regbits-44xx.h"
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#include "control.h"
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void __iomem *prm_base;
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void __iomem *cm_base;
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void __iomem *cm2_base;
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void __iomem *prcm_mpu_base;
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#define MAX_MODULE_ENABLE_WAIT 100000
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u32 omap_prcm_get_reset_sources(void)
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{
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/* XXX This presumably needs modification for 34XX */
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if (cpu_is_omap24xx() || cpu_is_omap34xx())
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return omap2_prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTST) & 0x7f;
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if (cpu_is_omap44xx())
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return omap2_prm_read_mod_reg(WKUP_MOD, OMAP4_RM_RSTST) & 0x7f;
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return 0;
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}
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EXPORT_SYMBOL(omap_prcm_get_reset_sources);
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/* Resets clock rates and reboots the system. Only called from system.h */
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void omap_prcm_restart(char mode, const char *cmd)
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{
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s16 prcm_offs = 0;
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if (cpu_is_omap24xx()) {
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omap2xxx_clk_prepare_for_reboot();
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prcm_offs = WKUP_MOD;
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} else if (cpu_is_omap34xx()) {
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prcm_offs = OMAP3430_GR_MOD;
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omap3_ctrl_write_boot_mode((cmd ? (u8)*cmd : 0));
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} else if (cpu_is_omap44xx()) {
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omap4_prminst_global_warm_sw_reset(); /* never returns */
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} else {
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WARN_ON(1);
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}
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/*
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* As per Errata i520, in some cases, user will not be able to
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* access DDR memory after warm-reset.
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* This situation occurs while the warm-reset happens during a read
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* access to DDR memory. In that particular condition, DDR memory
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* does not respond to a corrupted read command due to the warm
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* reset occurrence but SDRC is waiting for read completion.
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* SDRC is not sensitive to the warm reset, but the interconnect is
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* reset on the fly, thus causing a misalignment between SDRC logic,
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* interconnect logic and DDR memory state.
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* WORKAROUND:
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* Steps to perform before a Warm reset is trigged:
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* 1. enable self-refresh on idle request
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* 2. put SDRC in idle
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* 3. wait until SDRC goes to idle
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* 4. generate SW reset (Global SW reset)
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*
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* Steps to be performed after warm reset occurs (in bootloader):
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* if HW warm reset is the source, apply below steps before any
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* accesses to SDRAM:
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* 1. Reset SMS and SDRC and wait till reset is complete
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* 2. Re-initialize SMS, SDRC and memory
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*
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* NOTE: Above work around is required only if arch reset is implemented
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* using Global SW reset(GLOBAL_SW_RST). DPLL3 reset does not need
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* the WA since it resets SDRC as well as part of cold reset.
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*/
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/* XXX should be moved to some OMAP2/3 specific code */
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omap2_prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, prcm_offs,
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OMAP2_RM_RSTCTRL);
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omap2_prm_read_mod_reg(prcm_offs, OMAP2_RM_RSTCTRL); /* OCP barrier */
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}
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/**
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* omap2_cm_wait_idlest - wait for IDLEST bit to indicate module readiness
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* @reg: physical address of module IDLEST register
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* @mask: value to mask against to determine if the module is active
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* @idlest: idle state indicator (0 or 1) for the clock
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* @name: name of the clock (for printk)
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*
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* Returns 1 if the module indicated readiness in time, or 0 if it
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* failed to enable in roughly MAX_MODULE_ENABLE_WAIT microseconds.
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*
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* XXX This function is deprecated. It should be removed once the
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* hwmod conversion is complete.
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*/
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int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, u8 idlest,
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const char *name)
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{
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int i = 0;
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int ena = 0;
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if (idlest)
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ena = 0;
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else
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ena = mask;
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/* Wait for lock */
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omap_test_timeout(((__raw_readl(reg) & mask) == ena),
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MAX_MODULE_ENABLE_WAIT, i);
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if (i < MAX_MODULE_ENABLE_WAIT)
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pr_debug("cm: Module associated with clock %s ready after %d loops\n",
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name, i);
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else
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pr_err("cm: Module associated with clock %s didn't enable in %d tries\n",
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name, MAX_MODULE_ENABLE_WAIT);
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return (i < MAX_MODULE_ENABLE_WAIT) ? 1 : 0;
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};
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void __init omap2_set_globals_prcm(struct omap_globals *omap2_globals)
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{
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if (omap2_globals->prm)
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prm_base = omap2_globals->prm;
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if (omap2_globals->cm)
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cm_base = omap2_globals->cm;
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if (omap2_globals->cm2)
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cm2_base = omap2_globals->cm2;
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if (omap2_globals->prcm_mpu)
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prcm_mpu_base = omap2_globals->prcm_mpu;
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if (cpu_is_omap44xx() || soc_is_omap54xx()) {
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omap_prm_base_init();
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omap_cm_base_init();
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}
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}
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/*
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* Stubbed functions so that common files continue to build when
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* custom builds are used
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* XXX These are temporary and should be removed at the earliest possible
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* opportunity
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*/
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int __weak omap4_cminst_wait_module_idle(u8 part, u16 inst, s16 cdoffs,
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u16 clkctrl_offs)
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{
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return 0;
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}
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void __weak omap4_cminst_module_enable(u8 mode, u8 part, u16 inst,
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s16 cdoffs, u16 clkctrl_offs)
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{
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}
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void __weak omap4_cminst_module_disable(u8 part, u16 inst, s16 cdoffs,
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u16 clkctrl_offs)
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{
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}
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