![Stephen Warren](/assets/img/avatar_default.png)
When changing a PLL's rate, it must have no active children. The CPU clock cannot be stopped, and CPU clock's divider is not used. The old clock driver used to handle this by internally reparenting the CPU clock onto a different PLL when changing the CPU clock rate. However, the new common-clock based clock driver does not do this, and probably cannot do this due to the locking issues it would cause. To solve this, have the Tegra cpufreq driver explicitly perform the reparenting operations itself. This is probably reasonable anyway, since such reparenting is somewhat a matter of policy (e.g. which alternate clock source to use, whether to leave the CPU clock a child of the alternate clock source if it's running at the desired rate), and hence is something more appropriate for the cpufreq driver than the core clock driver anyway. Cc: Prashant Gaikwad <pgaikwad@nvidia.com> Cc: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
298 lines
6.6 KiB
C
298 lines
6.6 KiB
C
/*
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* arch/arm/mach-tegra/cpu-tegra.c
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*
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* Copyright (C) 2010 Google, Inc.
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*
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* Author:
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* Colin Cross <ccross@google.com>
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* Based on arch/arm/plat-omap/cpu-omap.c, (C) 2005 Nokia Corporation
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/sched.h>
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#include <linux/cpufreq.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/suspend.h>
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#include <mach/clk.h>
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/* Frequency table index must be sequential starting at 0 */
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static struct cpufreq_frequency_table freq_table[] = {
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{ 0, 216000 },
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{ 1, 312000 },
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{ 2, 456000 },
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{ 3, 608000 },
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{ 4, 760000 },
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{ 5, 816000 },
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{ 6, 912000 },
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{ 7, 1000000 },
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{ 8, CPUFREQ_TABLE_END },
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};
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#define NUM_CPUS 2
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static struct clk *cpu_clk;
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static struct clk *pll_x_clk;
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static struct clk *pll_p_clk;
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static struct clk *emc_clk;
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static unsigned long target_cpu_speed[NUM_CPUS];
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static DEFINE_MUTEX(tegra_cpu_lock);
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static bool is_suspended;
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static int tegra_verify_speed(struct cpufreq_policy *policy)
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{
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return cpufreq_frequency_table_verify(policy, freq_table);
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}
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static unsigned int tegra_getspeed(unsigned int cpu)
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{
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unsigned long rate;
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if (cpu >= NUM_CPUS)
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return 0;
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rate = clk_get_rate(cpu_clk) / 1000;
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return rate;
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}
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static int tegra_cpu_clk_set_rate(unsigned long rate)
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{
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int ret;
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/*
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* Take an extra reference to the main pll so it doesn't turn
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* off when we move the cpu off of it
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*/
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clk_prepare_enable(pll_x_clk);
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ret = clk_set_parent(cpu_clk, pll_p_clk);
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if (ret) {
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pr_err("Failed to switch cpu to clock pll_p\n");
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goto out;
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}
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if (rate == clk_get_rate(pll_p_clk))
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goto out;
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ret = clk_set_rate(pll_x_clk, rate);
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if (ret) {
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pr_err("Failed to change pll_x to %lu\n", rate);
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goto out;
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}
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ret = clk_set_parent(cpu_clk, pll_x_clk);
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if (ret) {
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pr_err("Failed to switch cpu to clock pll_x\n");
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goto out;
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}
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out:
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clk_disable_unprepare(pll_x_clk);
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return ret;
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}
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static int tegra_update_cpu_speed(unsigned long rate)
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{
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int ret = 0;
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struct cpufreq_freqs freqs;
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freqs.old = tegra_getspeed(0);
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freqs.new = rate;
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if (freqs.old == freqs.new)
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return ret;
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/*
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* Vote on memory bus frequency based on cpu frequency
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* This sets the minimum frequency, display or avp may request higher
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*/
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if (rate >= 816000)
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clk_set_rate(emc_clk, 600000000); /* cpu 816 MHz, emc max */
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else if (rate >= 456000)
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clk_set_rate(emc_clk, 300000000); /* cpu 456 MHz, emc 150Mhz */
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else
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clk_set_rate(emc_clk, 100000000); /* emc 50Mhz */
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for_each_online_cpu(freqs.cpu)
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cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
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#ifdef CONFIG_CPU_FREQ_DEBUG
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printk(KERN_DEBUG "cpufreq-tegra: transition: %u --> %u\n",
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freqs.old, freqs.new);
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#endif
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ret = tegra_cpu_clk_set_rate(freqs.new * 1000);
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if (ret) {
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pr_err("cpu-tegra: Failed to set cpu frequency to %d kHz\n",
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freqs.new);
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return ret;
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}
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for_each_online_cpu(freqs.cpu)
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cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
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return 0;
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}
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static unsigned long tegra_cpu_highest_speed(void)
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{
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unsigned long rate = 0;
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int i;
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for_each_online_cpu(i)
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rate = max(rate, target_cpu_speed[i]);
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return rate;
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}
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static int tegra_target(struct cpufreq_policy *policy,
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unsigned int target_freq,
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unsigned int relation)
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{
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unsigned int idx;
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unsigned int freq;
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int ret = 0;
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mutex_lock(&tegra_cpu_lock);
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if (is_suspended) {
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ret = -EBUSY;
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goto out;
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}
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cpufreq_frequency_table_target(policy, freq_table, target_freq,
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relation, &idx);
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freq = freq_table[idx].frequency;
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target_cpu_speed[policy->cpu] = freq;
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ret = tegra_update_cpu_speed(tegra_cpu_highest_speed());
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out:
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mutex_unlock(&tegra_cpu_lock);
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return ret;
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}
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static int tegra_pm_notify(struct notifier_block *nb, unsigned long event,
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void *dummy)
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{
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mutex_lock(&tegra_cpu_lock);
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if (event == PM_SUSPEND_PREPARE) {
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is_suspended = true;
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pr_info("Tegra cpufreq suspend: setting frequency to %d kHz\n",
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freq_table[0].frequency);
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tegra_update_cpu_speed(freq_table[0].frequency);
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} else if (event == PM_POST_SUSPEND) {
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is_suspended = false;
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}
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mutex_unlock(&tegra_cpu_lock);
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return NOTIFY_OK;
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}
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static struct notifier_block tegra_cpu_pm_notifier = {
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.notifier_call = tegra_pm_notify,
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};
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static int tegra_cpu_init(struct cpufreq_policy *policy)
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{
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if (policy->cpu >= NUM_CPUS)
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return -EINVAL;
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cpu_clk = clk_get_sys(NULL, "cpu");
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if (IS_ERR(cpu_clk))
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return PTR_ERR(cpu_clk);
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pll_x_clk = clk_get_sys(NULL, "pll_x");
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if (IS_ERR(pll_x_clk))
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return PTR_ERR(pll_x_clk);
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pll_p_clk = clk_get_sys(NULL, "pll_p");
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if (IS_ERR(pll_p_clk))
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return PTR_ERR(pll_p_clk);
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emc_clk = clk_get_sys("cpu", "emc");
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if (IS_ERR(emc_clk)) {
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clk_put(cpu_clk);
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return PTR_ERR(emc_clk);
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}
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clk_prepare_enable(emc_clk);
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clk_prepare_enable(cpu_clk);
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cpufreq_frequency_table_cpuinfo(policy, freq_table);
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cpufreq_frequency_table_get_attr(freq_table, policy->cpu);
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policy->cur = tegra_getspeed(policy->cpu);
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target_cpu_speed[policy->cpu] = policy->cur;
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/* FIXME: what's the actual transition time? */
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policy->cpuinfo.transition_latency = 300 * 1000;
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policy->shared_type = CPUFREQ_SHARED_TYPE_ALL;
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cpumask_copy(policy->related_cpus, cpu_possible_mask);
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if (policy->cpu == 0)
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register_pm_notifier(&tegra_cpu_pm_notifier);
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return 0;
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}
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static int tegra_cpu_exit(struct cpufreq_policy *policy)
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{
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cpufreq_frequency_table_cpuinfo(policy, freq_table);
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clk_disable_unprepare(emc_clk);
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clk_put(emc_clk);
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clk_put(cpu_clk);
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return 0;
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}
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static struct freq_attr *tegra_cpufreq_attr[] = {
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&cpufreq_freq_attr_scaling_available_freqs,
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NULL,
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};
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static struct cpufreq_driver tegra_cpufreq_driver = {
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.verify = tegra_verify_speed,
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.target = tegra_target,
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.get = tegra_getspeed,
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.init = tegra_cpu_init,
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.exit = tegra_cpu_exit,
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.name = "tegra",
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.attr = tegra_cpufreq_attr,
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};
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static int __init tegra_cpufreq_init(void)
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{
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return cpufreq_register_driver(&tegra_cpufreq_driver);
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}
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static void __exit tegra_cpufreq_exit(void)
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{
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cpufreq_unregister_driver(&tegra_cpufreq_driver);
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}
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MODULE_AUTHOR("Colin Cross <ccross@android.com>");
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MODULE_DESCRIPTION("cpufreq driver for Nvidia Tegra2");
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MODULE_LICENSE("GPL");
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module_init(tegra_cpufreq_init);
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module_exit(tegra_cpufreq_exit);
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