![Alex Elder](/assets/img/avatar_default.png)
This patch includes code implementing the modem functionality. There are several communication paths between the AP and modem, separate from the main data path provided by IPA. SMP2P provides primitive messaging and interrupt capability, and QMI allows more complex out-of-band messaging to occur between entities on the AP and modem. (SMP2P and QMI support are added by the next patch.) Management of these (plus the network device implementing the data path) is done by code within "ipa_modem.c". Sort of unrelated, this patch also includes the code supporting the microcontroller CPU present on the IPA. The microcontroller can be used to implement special handling of packets, but at this time we don't support that. Still, it is a component that needs to be initialized, and in the event of a crash we need to do some synchronization between the AP and the microcontroller. Signed-off-by: Alex Elder <elder@linaro.org> Signed-off-by: David S. Miller <davem@davemloft.net>
212 lines
6.7 KiB
C
212 lines
6.7 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved.
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* Copyright (C) 2018-2020 Linaro Ltd.
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*/
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#include <linux/types.h>
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#include <linux/io.h>
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#include <linux/delay.h>
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#include "ipa.h"
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#include "ipa_clock.h"
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#include "ipa_uc.h"
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/**
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* DOC: The IPA embedded microcontroller
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*
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* The IPA incorporates a microcontroller that is able to do some additional
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* handling/offloading of network activity. The current code makes
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* essentially no use of the microcontroller, but it still requires some
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* initialization. It needs to be notified in the event the AP crashes.
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*
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* The microcontroller can generate two interrupts to the AP. One interrupt
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* is used to indicate that a response to a request from the AP is available.
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* The other is used to notify the AP of the occurrence of an event. In
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* addition, the AP can interrupt the microcontroller by writing a register.
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*
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* A 128 byte block of structured memory within the IPA SRAM is used together
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* with these interrupts to implement the communication interface between the
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* AP and the IPA microcontroller. Each side writes data to the shared area
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* before interrupting its peer, which will read the written data in response
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* to the interrupt. Some information found in the shared area is currently
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* unused. All remaining space in the shared area is reserved, and must not
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* be read or written by the AP.
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*/
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/* Supports hardware interface version 0x2000 */
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/* Offset relative to the base of the IPA shared address space of the
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* shared region used for communication with the microcontroller. The
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* region is 128 bytes in size, but only the first 40 bytes are used.
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*/
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#define IPA_MEM_UC_OFFSET 0x0000
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/* Delay to allow a the microcontroller to save state when crashing */
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#define IPA_SEND_DELAY 100 /* microseconds */
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/**
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* struct ipa_uc_mem_area - AP/microcontroller shared memory area
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* @command: command code (AP->microcontroller)
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* @command_param: low 32 bits of command parameter (AP->microcontroller)
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* @command_param_hi: high 32 bits of command parameter (AP->microcontroller)
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*
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* @response: response code (microcontroller->AP)
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* @response_param: response parameter (microcontroller->AP)
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*
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* @event: event code (microcontroller->AP)
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* @event_param: event parameter (microcontroller->AP)
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*
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* @first_error_address: address of first error-source on SNOC
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* @hw_state: state of hardware (including error type information)
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* @warning_counter: counter of non-fatal hardware errors
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* @interface_version: hardware-reported interface version
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*/
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struct ipa_uc_mem_area {
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u8 command; /* enum ipa_uc_command */
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u8 reserved0[3];
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__le32 command_param;
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__le32 command_param_hi;
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u8 response; /* enum ipa_uc_response */
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u8 reserved1[3];
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__le32 response_param;
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u8 event; /* enum ipa_uc_event */
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u8 reserved2[3];
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__le32 event_param;
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__le32 first_error_address;
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u8 hw_state;
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u8 warning_counter;
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__le16 reserved3;
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__le16 interface_version;
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__le16 reserved4;
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};
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/** enum ipa_uc_command - commands from the AP to the microcontroller */
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enum ipa_uc_command {
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IPA_UC_COMMAND_NO_OP = 0,
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IPA_UC_COMMAND_UPDATE_FLAGS = 1,
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IPA_UC_COMMAND_DEBUG_RUN_TEST = 2,
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IPA_UC_COMMAND_DEBUG_GET_INFO = 3,
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IPA_UC_COMMAND_ERR_FATAL = 4,
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IPA_UC_COMMAND_CLK_GATE = 5,
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IPA_UC_COMMAND_CLK_UNGATE = 6,
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IPA_UC_COMMAND_MEMCPY = 7,
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IPA_UC_COMMAND_RESET_PIPE = 8,
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IPA_UC_COMMAND_REG_WRITE = 9,
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IPA_UC_COMMAND_GSI_CH_EMPTY = 10,
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};
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/** enum ipa_uc_response - microcontroller response codes */
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enum ipa_uc_response {
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IPA_UC_RESPONSE_NO_OP = 0,
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IPA_UC_RESPONSE_INIT_COMPLETED = 1,
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IPA_UC_RESPONSE_CMD_COMPLETED = 2,
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IPA_UC_RESPONSE_DEBUG_GET_INFO = 3,
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};
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/** enum ipa_uc_event - common cpu events reported by the microcontroller */
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enum ipa_uc_event {
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IPA_UC_EVENT_NO_OP = 0,
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IPA_UC_EVENT_ERROR = 1,
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IPA_UC_EVENT_LOG_INFO = 2,
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};
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static struct ipa_uc_mem_area *ipa_uc_shared(struct ipa *ipa)
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{
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u32 offset = ipa->mem_offset + ipa->mem[IPA_MEM_UC_SHARED].offset;
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return ipa->mem_virt + offset;
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}
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/* Microcontroller event IPA interrupt handler */
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static void ipa_uc_event_handler(struct ipa *ipa, enum ipa_irq_id irq_id)
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{
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struct ipa_uc_mem_area *shared = ipa_uc_shared(ipa);
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struct device *dev = &ipa->pdev->dev;
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if (shared->event == IPA_UC_EVENT_ERROR)
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dev_err(dev, "microcontroller error event\n");
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else
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dev_err(dev, "unsupported microcontroller event %hhu\n",
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shared->event);
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}
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/* Microcontroller response IPA interrupt handler */
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static void ipa_uc_response_hdlr(struct ipa *ipa, enum ipa_irq_id irq_id)
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{
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struct ipa_uc_mem_area *shared = ipa_uc_shared(ipa);
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/* An INIT_COMPLETED response message is sent to the AP by the
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* microcontroller when it is operational. Other than this, the AP
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* should only receive responses from the microcontroller when it has
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* sent it a request message.
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*
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* We can drop the clock reference taken in ipa_uc_init() once we
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* know the microcontroller has finished its initialization.
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*/
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switch (shared->response) {
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case IPA_UC_RESPONSE_INIT_COMPLETED:
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ipa->uc_loaded = true;
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ipa_clock_put(ipa);
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break;
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default:
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dev_warn(&ipa->pdev->dev,
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"unsupported microcontroller response %hhu\n",
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shared->response);
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break;
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}
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}
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/* ipa_uc_setup() - Set up the microcontroller */
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void ipa_uc_setup(struct ipa *ipa)
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{
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/* The microcontroller needs the IPA clock running until it has
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* completed its initialization. It signals this by sending an
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* INIT_COMPLETED response message to the AP. This could occur after
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* we have finished doing the rest of the IPA initialization, so we
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* need to take an extra "proxy" reference, and hold it until we've
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* received that signal. (This reference is dropped in
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* ipa_uc_response_hdlr(), above.)
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*/
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ipa_clock_get(ipa);
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ipa->uc_loaded = false;
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ipa_interrupt_add(ipa->interrupt, IPA_IRQ_UC_0, ipa_uc_event_handler);
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ipa_interrupt_add(ipa->interrupt, IPA_IRQ_UC_1, ipa_uc_response_hdlr);
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}
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/* Inverse of ipa_uc_setup() */
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void ipa_uc_teardown(struct ipa *ipa)
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{
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ipa_interrupt_remove(ipa->interrupt, IPA_IRQ_UC_1);
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ipa_interrupt_remove(ipa->interrupt, IPA_IRQ_UC_0);
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if (!ipa->uc_loaded)
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ipa_clock_put(ipa);
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}
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/* Send a command to the microcontroller */
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static void send_uc_command(struct ipa *ipa, u32 command, u32 command_param)
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{
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struct ipa_uc_mem_area *shared = ipa_uc_shared(ipa);
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shared->command = command;
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shared->command_param = cpu_to_le32(command_param);
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shared->command_param_hi = 0;
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shared->response = 0;
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shared->response_param = 0;
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iowrite32(1, ipa->reg_virt + IPA_REG_IRQ_UC_OFFSET);
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}
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/* Tell the microcontroller the AP is shutting down */
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void ipa_uc_panic_notifier(struct ipa *ipa)
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{
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if (!ipa->uc_loaded)
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return;
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send_uc_command(ipa, IPA_UC_COMMAND_ERR_FATAL, 0);
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/* give uc enough time to save state */
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udelay(IPA_SEND_DELAY);
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}
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