![Linus Torvalds](/assets/img/avatar_default.png)
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
400 lines
12 KiB
C
400 lines
12 KiB
C
/* sun4m_irq.c
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* arch/sparc/kernel/sun4m_irq.c:
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*
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* djhr: Hacked out of irq.c into a CPU dependent version.
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*
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* Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
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* Copyright (C) 1995 Miguel de Icaza (miguel@nuclecu.unam.mx)
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* Copyright (C) 1995 Pete A. Zaitcev (zaitcev@yahoo.com)
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* Copyright (C) 1996 Dave Redman (djhr@tadpole.co.uk)
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*/
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#include <linux/config.h>
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#include <linux/errno.h>
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#include <linux/linkage.h>
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#include <linux/kernel_stat.h>
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#include <linux/signal.h>
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#include <linux/sched.h>
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#include <linux/ptrace.h>
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#include <linux/smp.h>
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#include <linux/interrupt.h>
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#include <linux/slab.h>
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#include <linux/init.h>
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#include <linux/ioport.h>
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#include <asm/ptrace.h>
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#include <asm/processor.h>
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#include <asm/system.h>
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#include <asm/psr.h>
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#include <asm/vaddrs.h>
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#include <asm/timer.h>
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#include <asm/openprom.h>
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#include <asm/oplib.h>
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#include <asm/traps.h>
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#include <asm/pgalloc.h>
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#include <asm/pgtable.h>
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#include <asm/smp.h>
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#include <asm/irq.h>
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#include <asm/io.h>
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#include <asm/sbus.h>
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#include <asm/cacheflush.h>
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static unsigned long dummy;
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struct sun4m_intregs *sun4m_interrupts;
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unsigned long *irq_rcvreg = &dummy;
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/* These tables only apply for interrupts greater than 15..
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*
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* any intr value below 0x10 is considered to be a soft-int
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* this may be useful or it may not.. but that's how I've done it.
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* and it won't clash with what OBP is telling us about devices.
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*
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* take an encoded intr value and lookup if it's valid
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* then get the mask bits that match from irq_mask
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*
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* P3: Translation from irq 0x0d to mask 0x2000 is for MrCoffee.
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*/
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static unsigned char irq_xlate[32] = {
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/* 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, a, b, c, d, e, f */
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0, 0, 0, 0, 1, 0, 2, 0, 3, 0, 4, 5, 6, 14, 0, 7,
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0, 0, 8, 9, 0, 10, 0, 11, 0, 12, 0, 13, 0, 14, 0, 0
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};
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static unsigned long irq_mask[] = {
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0, /* illegal index */
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SUN4M_INT_SCSI, /* 1 irq 4 */
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SUN4M_INT_ETHERNET, /* 2 irq 6 */
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SUN4M_INT_VIDEO, /* 3 irq 8 */
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SUN4M_INT_REALTIME, /* 4 irq 10 */
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SUN4M_INT_FLOPPY, /* 5 irq 11 */
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(SUN4M_INT_SERIAL | SUN4M_INT_KBDMS), /* 6 irq 12 */
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SUN4M_INT_MODULE_ERR, /* 7 irq 15 */
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SUN4M_INT_SBUS(0), /* 8 irq 2 */
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SUN4M_INT_SBUS(1), /* 9 irq 3 */
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SUN4M_INT_SBUS(2), /* 10 irq 5 */
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SUN4M_INT_SBUS(3), /* 11 irq 7 */
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SUN4M_INT_SBUS(4), /* 12 irq 9 */
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SUN4M_INT_SBUS(5), /* 13 irq 11 */
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SUN4M_INT_SBUS(6) /* 14 irq 13 */
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};
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static int sun4m_pil_map[] = { 0, 2, 3, 5, 7, 9, 11, 13 };
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unsigned int sun4m_sbint_to_irq(struct sbus_dev *sdev, unsigned int sbint)
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{
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if (sbint >= sizeof(sun4m_pil_map)) {
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printk(KERN_ERR "%s: bogus SBINT %d\n", sdev->prom_name, sbint);
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BUG();
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}
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return sun4m_pil_map[sbint] | 0x30;
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}
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inline unsigned long sun4m_get_irqmask(unsigned int irq)
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{
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unsigned long mask;
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if (irq > 0x20) {
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/* OBIO/SBUS interrupts */
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irq &= 0x1f;
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mask = irq_mask[irq_xlate[irq]];
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if (!mask)
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printk("sun4m_get_irqmask: IRQ%d has no valid mask!\n",irq);
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} else {
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/* Soft Interrupts will come here.
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* Currently there is no way to trigger them but I'm sure
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* something could be cooked up.
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*/
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irq &= 0xf;
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mask = SUN4M_SOFT_INT(irq);
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}
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return mask;
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}
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static void sun4m_disable_irq(unsigned int irq_nr)
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{
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unsigned long mask, flags;
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int cpu = smp_processor_id();
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mask = sun4m_get_irqmask(irq_nr);
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local_irq_save(flags);
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if (irq_nr > 15)
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sun4m_interrupts->set = mask;
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else
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sun4m_interrupts->cpu_intregs[cpu].set = mask;
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local_irq_restore(flags);
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}
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static void sun4m_enable_irq(unsigned int irq_nr)
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{
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unsigned long mask, flags;
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int cpu = smp_processor_id();
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/* Dreadful floppy hack. When we use 0x2b instead of
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* 0x0b the system blows (it starts to whistle!).
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* So we continue to use 0x0b. Fixme ASAP. --P3
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*/
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if (irq_nr != 0x0b) {
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mask = sun4m_get_irqmask(irq_nr);
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local_irq_save(flags);
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if (irq_nr > 15)
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sun4m_interrupts->clear = mask;
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else
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sun4m_interrupts->cpu_intregs[cpu].clear = mask;
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local_irq_restore(flags);
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} else {
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local_irq_save(flags);
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sun4m_interrupts->clear = SUN4M_INT_FLOPPY;
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local_irq_restore(flags);
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}
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}
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static unsigned long cpu_pil_to_imask[16] = {
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/*0*/ 0x00000000,
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/*1*/ 0x00000000,
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/*2*/ SUN4M_INT_SBUS(0) | SUN4M_INT_VME(0),
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/*3*/ SUN4M_INT_SBUS(1) | SUN4M_INT_VME(1),
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/*4*/ SUN4M_INT_SCSI,
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/*5*/ SUN4M_INT_SBUS(2) | SUN4M_INT_VME(2),
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/*6*/ SUN4M_INT_ETHERNET,
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/*7*/ SUN4M_INT_SBUS(3) | SUN4M_INT_VME(3),
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/*8*/ SUN4M_INT_VIDEO,
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/*9*/ SUN4M_INT_SBUS(4) | SUN4M_INT_VME(4) | SUN4M_INT_MODULE_ERR,
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/*10*/ SUN4M_INT_REALTIME,
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/*11*/ SUN4M_INT_SBUS(5) | SUN4M_INT_VME(5) | SUN4M_INT_FLOPPY,
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/*12*/ SUN4M_INT_SERIAL | SUN4M_INT_KBDMS,
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/*13*/ SUN4M_INT_AUDIO,
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/*14*/ SUN4M_INT_E14,
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/*15*/ 0x00000000
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};
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/* We assume the caller has disabled local interrupts when these are called,
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* or else very bizarre behavior will result.
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*/
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static void sun4m_disable_pil_irq(unsigned int pil)
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{
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sun4m_interrupts->set = cpu_pil_to_imask[pil];
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}
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static void sun4m_enable_pil_irq(unsigned int pil)
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{
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sun4m_interrupts->clear = cpu_pil_to_imask[pil];
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}
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#ifdef CONFIG_SMP
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static void sun4m_send_ipi(int cpu, int level)
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{
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unsigned long mask;
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mask = sun4m_get_irqmask(level);
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sun4m_interrupts->cpu_intregs[cpu].set = mask;
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}
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static void sun4m_clear_ipi(int cpu, int level)
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{
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unsigned long mask;
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mask = sun4m_get_irqmask(level);
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sun4m_interrupts->cpu_intregs[cpu].clear = mask;
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}
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static void sun4m_set_udt(int cpu)
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{
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sun4m_interrupts->undirected_target = cpu;
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}
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#endif
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#define OBIO_INTR 0x20
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#define TIMER_IRQ (OBIO_INTR | 10)
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#define PROFILE_IRQ (OBIO_INTR | 14)
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struct sun4m_timer_regs *sun4m_timers;
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unsigned int lvl14_resolution = (((1000000/HZ) + 1) << 10);
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static void sun4m_clear_clock_irq(void)
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{
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volatile unsigned int clear_intr;
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clear_intr = sun4m_timers->l10_timer_limit;
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}
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static void sun4m_clear_profile_irq(int cpu)
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{
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volatile unsigned int clear;
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clear = sun4m_timers->cpu_timers[cpu].l14_timer_limit;
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}
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static void sun4m_load_profile_irq(int cpu, unsigned int limit)
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{
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sun4m_timers->cpu_timers[cpu].l14_timer_limit = limit;
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}
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char *sun4m_irq_itoa(unsigned int irq)
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{
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static char buff[16];
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sprintf(buff, "%d", irq);
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return buff;
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}
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static void __init sun4m_init_timers(irqreturn_t (*counter_fn)(int, void *, struct pt_regs *))
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{
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int reg_count, irq, cpu;
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struct linux_prom_registers cnt_regs[PROMREG_MAX];
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int obio_node, cnt_node;
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struct resource r;
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cnt_node = 0;
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if((obio_node =
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prom_searchsiblings (prom_getchild(prom_root_node), "obio")) == 0 ||
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(obio_node = prom_getchild (obio_node)) == 0 ||
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(cnt_node = prom_searchsiblings (obio_node, "counter")) == 0) {
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prom_printf("Cannot find /obio/counter node\n");
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prom_halt();
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}
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reg_count = prom_getproperty(cnt_node, "reg",
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(void *) cnt_regs, sizeof(cnt_regs));
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reg_count = (reg_count/sizeof(struct linux_prom_registers));
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/* Apply the obio ranges to the timer registers. */
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prom_apply_obio_ranges(cnt_regs, reg_count);
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cnt_regs[4].phys_addr = cnt_regs[reg_count-1].phys_addr;
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cnt_regs[4].reg_size = cnt_regs[reg_count-1].reg_size;
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cnt_regs[4].which_io = cnt_regs[reg_count-1].which_io;
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for(obio_node = 1; obio_node < 4; obio_node++) {
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cnt_regs[obio_node].phys_addr =
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cnt_regs[obio_node-1].phys_addr + PAGE_SIZE;
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cnt_regs[obio_node].reg_size = cnt_regs[obio_node-1].reg_size;
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cnt_regs[obio_node].which_io = cnt_regs[obio_node-1].which_io;
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}
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memset((char*)&r, 0, sizeof(struct resource));
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/* Map the per-cpu Counter registers. */
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r.flags = cnt_regs[0].which_io;
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r.start = cnt_regs[0].phys_addr;
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sun4m_timers = (struct sun4m_timer_regs *) sbus_ioremap(&r, 0,
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PAGE_SIZE*SUN4M_NCPUS, "sun4m_cpu_cnt");
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/* Map the system Counter register. */
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/* XXX Here we expect consequent calls to yeld adjusent maps. */
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r.flags = cnt_regs[4].which_io;
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r.start = cnt_regs[4].phys_addr;
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sbus_ioremap(&r, 0, cnt_regs[4].reg_size, "sun4m_sys_cnt");
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sun4m_timers->l10_timer_limit = (((1000000/HZ) + 1) << 10);
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master_l10_counter = &sun4m_timers->l10_cur_count;
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master_l10_limit = &sun4m_timers->l10_timer_limit;
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irq = request_irq(TIMER_IRQ,
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counter_fn,
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(SA_INTERRUPT | SA_STATIC_ALLOC),
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"timer", NULL);
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if (irq) {
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prom_printf("time_init: unable to attach IRQ%d\n",TIMER_IRQ);
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prom_halt();
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}
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if (!cpu_find_by_instance(1, NULL, NULL)) {
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for(cpu = 0; cpu < 4; cpu++)
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sun4m_timers->cpu_timers[cpu].l14_timer_limit = 0;
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sun4m_interrupts->set = SUN4M_INT_E14;
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} else {
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sun4m_timers->cpu_timers[0].l14_timer_limit = 0;
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}
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#ifdef CONFIG_SMP
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{
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unsigned long flags;
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extern unsigned long lvl14_save[4];
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struct tt_entry *trap_table = &sparc_ttable[SP_TRAP_IRQ1 + (14 - 1)];
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/* For SMP we use the level 14 ticker, however the bootup code
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* has copied the firmwares level 14 vector into boot cpu's
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* trap table, we must fix this now or we get squashed.
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*/
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local_irq_save(flags);
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trap_table->inst_one = lvl14_save[0];
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trap_table->inst_two = lvl14_save[1];
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trap_table->inst_three = lvl14_save[2];
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trap_table->inst_four = lvl14_save[3];
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local_flush_cache_all();
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local_irq_restore(flags);
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}
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#endif
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}
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void __init sun4m_init_IRQ(void)
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{
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int ie_node,i;
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struct linux_prom_registers int_regs[PROMREG_MAX];
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int num_regs;
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struct resource r;
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int mid;
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local_irq_disable();
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if((ie_node = prom_searchsiblings(prom_getchild(prom_root_node), "obio")) == 0 ||
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(ie_node = prom_getchild (ie_node)) == 0 ||
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(ie_node = prom_searchsiblings (ie_node, "interrupt")) == 0) {
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prom_printf("Cannot find /obio/interrupt node\n");
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prom_halt();
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}
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num_regs = prom_getproperty(ie_node, "reg", (char *) int_regs,
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sizeof(int_regs));
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num_regs = (num_regs/sizeof(struct linux_prom_registers));
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/* Apply the obio ranges to these registers. */
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prom_apply_obio_ranges(int_regs, num_regs);
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int_regs[4].phys_addr = int_regs[num_regs-1].phys_addr;
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int_regs[4].reg_size = int_regs[num_regs-1].reg_size;
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int_regs[4].which_io = int_regs[num_regs-1].which_io;
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for(ie_node = 1; ie_node < 4; ie_node++) {
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int_regs[ie_node].phys_addr = int_regs[ie_node-1].phys_addr + PAGE_SIZE;
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int_regs[ie_node].reg_size = int_regs[ie_node-1].reg_size;
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int_regs[ie_node].which_io = int_regs[ie_node-1].which_io;
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}
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memset((char *)&r, 0, sizeof(struct resource));
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/* Map the interrupt registers for all possible cpus. */
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r.flags = int_regs[0].which_io;
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r.start = int_regs[0].phys_addr;
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sun4m_interrupts = (struct sun4m_intregs *) sbus_ioremap(&r, 0,
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PAGE_SIZE*SUN4M_NCPUS, "interrupts_percpu");
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/* Map the system interrupt control registers. */
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r.flags = int_regs[4].which_io;
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r.start = int_regs[4].phys_addr;
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sbus_ioremap(&r, 0, int_regs[4].reg_size, "interrupts_system");
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sun4m_interrupts->set = ~SUN4M_INT_MASKALL;
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for (i = 0; !cpu_find_by_instance(i, NULL, &mid); i++)
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sun4m_interrupts->cpu_intregs[mid].clear = ~0x17fff;
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if (!cpu_find_by_instance(1, NULL, NULL)) {
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/* system wide interrupts go to cpu 0, this should always
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* be safe because it is guaranteed to be fitted or OBP doesn't
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* come up
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*
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* Not sure, but writing here on SLAVIO systems may puke
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* so I don't do it unless there is more than 1 cpu.
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*/
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irq_rcvreg = (unsigned long *)
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&sun4m_interrupts->undirected_target;
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sun4m_interrupts->undirected_target = 0;
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}
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BTFIXUPSET_CALL(sbint_to_irq, sun4m_sbint_to_irq, BTFIXUPCALL_NORM);
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BTFIXUPSET_CALL(enable_irq, sun4m_enable_irq, BTFIXUPCALL_NORM);
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BTFIXUPSET_CALL(disable_irq, sun4m_disable_irq, BTFIXUPCALL_NORM);
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BTFIXUPSET_CALL(enable_pil_irq, sun4m_enable_pil_irq, BTFIXUPCALL_NORM);
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BTFIXUPSET_CALL(disable_pil_irq, sun4m_disable_pil_irq, BTFIXUPCALL_NORM);
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BTFIXUPSET_CALL(clear_clock_irq, sun4m_clear_clock_irq, BTFIXUPCALL_NORM);
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BTFIXUPSET_CALL(clear_profile_irq, sun4m_clear_profile_irq, BTFIXUPCALL_NORM);
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BTFIXUPSET_CALL(load_profile_irq, sun4m_load_profile_irq, BTFIXUPCALL_NORM);
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BTFIXUPSET_CALL(__irq_itoa, sun4m_irq_itoa, BTFIXUPCALL_NORM);
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sparc_init_timers = sun4m_init_timers;
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#ifdef CONFIG_SMP
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BTFIXUPSET_CALL(set_cpu_int, sun4m_send_ipi, BTFIXUPCALL_NORM);
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BTFIXUPSET_CALL(clear_cpu_int, sun4m_clear_ipi, BTFIXUPCALL_NORM);
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BTFIXUPSET_CALL(set_irq_udt, sun4m_set_udt, BTFIXUPCALL_NORM);
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#endif
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/* Cannot enable interrupts until OBP ticker is disabled. */
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}
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